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LH5P8128-80
Datasheet (Sharp)
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Datasheet LH5P8128TR-80, LH5P8128TR-60, LH5P8128T-80, LH5P8128T-60, LH5P8128T-10 Datasheet (Sharp)

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Page 1
LH5P8128
CMOS 1 M (12 8K × 8 ) Pseudo-Static RAM
FEATURES
•• 131,072 × 8 bi t orga niza tion
•• Access times (MAX.): 60/80/100 ns
•• Cycle ti mes (MIN.): 100/13 0/160 ns
•• Sing le +5 V p owe r su ppl y
•• Powe r consu mption :
•• TTL compatible I/O
•• Available for auto-refresh and self-refresh
modes
•• 512 refresh cycle s/8 ms
•• Compatible with stan dard 1M
SRAM pinout
•• Packages: 32-pi n , 600 -mil DIP 32-pi n , 525 -mil S OP 32-pi n , 8 × 20 mm
2
TSOP (Type I)
DESCRIPTION
The LH5P8128 is a 1M bit Pseudo-Static RAM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circ uitry with a DRAM memory cell for pseudo static operation which elimi­nates external clock inputs, while having the same pinout as industry standard SRAMs. Moreover, due to the functional similarities between PSRAMs and SRAMs, existing 128K × 8 SRAM sockets can be filled with the LH5P8128 with little or no changes. The advantage is the cost savings realized with the lower cost PSRAM.
The LH5P812 8 PSR AM has the ability to fill the gap between DRA M and SRAM b y offering low cost, low power standby and a simple interface.
PIN CONNECTIONS
5P8128-1
TOP VIEW
5 6 7 8
11
12
A
0
A
3
26 25 24 23 22
21
18
A
5
A
4
9
10
A
1
A
2
20 19
A
6
A
9
A
11
A
10
13 14 15
28 27
I/O
0
A
13
16
17
I/O
2
OE
CE
1
A
7
GND
I/O
4
I/O
3
I/O
5
A
8
32-PIN DIP 32-PIN SOP
3 4
A
12
30 29
CE
2
A
14
R/W
1
2
A
16
32
31
V
CC
RFSH
A
15
I/O
1
I/O
6
I/O
7
Figure 1. Pin Connections for DIP and
SOP Packages
2 3
4 5 6
9
10
7 8
A
9
11
1
32 31 30
29
26 25
28 27
24 23
OE
A
10
32-PIN TSOP (Type I)
12
15 16
13
14
21 20
22
19
17
18
A
11
A
13
A
8
CE
2
R/W
A
15
RFSH
I/O
2
I/O
1
A
1
A
3
I/O
7
CE
1
I/O
5
I/O
6
GND
I/O
4
I/O
3
I/O
0
A
0
A
2
5P8128-1A
V
CC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
NOTE: Reverse bend available on request.
Figure 2. Pin Connections for TSOP Package
1
Page 2
I/O
1
CLOCK
GENERATOR
CE
1
R/W
A
12
A
13
A
14
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A
10
A
2
A
1
A
0
COLUMN
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
REFRESH ADDRESS COUNTER
DATA
IN
BUFFER
DATA
OUT
BUFFER
I/O
SELECTOR
COLUMN
DECODER
SENSE
AMPS
MEMORY
ARRAY
ROW
DECODER
EXT/INT
ADDRESS
MUX
REFRESH
CONTROLLER
REFRESH
TIMER
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
BB
GENERATOR
GND
V
CC
A
15
A
16
5P8128-2
I/O
0
RFSH
OE
12 11 10
9 8 7 6
5 27 26 23
25
4 28
3 31
2
22
1
24
29
16 32
13 14 15 17 18 19 20
21
CE
2
30
NOTE: Pin numbers apply to the 32-pin DIP or SOP.
Figure 3. LH5P8128 Block Diagram
PIN DESCRIPTION
SIGNA L PIN N AME
A0 - A
16
Addre ss input
R/W Read/ Writ e in put
OE Outpu t E nab le Inp ut
SIGNAL PIN NAME
CE1, CE
2
Chip E nab le inp ut
RFSH Refres h i npu t
I/O0 - I/O
7
Data i npu t/o utp ut
LH5P8128 CMOS 1 M (128K × 8) Pseudo-Static RAM
2
Page 3
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Operat ing cu rre nt
LH5P8128-60
I
CC1
tRC = tRC (MIN)
104
mA 1, 2
LH5P8128-80 70 LH5P8128-10 50
Standb y c urr ent
TTL Input
I
CC2
1
mA
1, 3
CMOS Input 0.2 1, 4
Self-r efr esh av era ge curren t
TTL Input
I
CC3
1
mA
1, 5
CMOS Input 0.2 1, 6
Input lea kag e c urr ent
I
LI
0 V ≤ VIN ≤ 6.5 V
0 V except on test pins
-10 10 µA
I/O le aka ge cur ren t I
LO
0 V ≤ V
OUT
≤ VCC + 0.3 V
Output in high-
impedance state
-10 10
µA
Output HI GH vol tag e V
OH
I
OUT
= -1 mA 2.4 V
Output LO W v olt age V
OL
I
OUT
= 4 mA 0.4 V
NOTES:
1. Specified values are with outputs open.
2. Depends on the cycle time.
3.
CE1 = VIH, RFSH = V
IH
4. CE1 = VCC - 0.2 V, RFSH = VCC - 0.2 V
5.
CE1 = VIH, RFSH = V
IL
6. CE1 = VCC - 0.2 V, RFSH = 0.2 V
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Appli ed v ol tag e on an y p ins V
T
-1.0 to +7.0 V 1
Output sh ort ci rcu it c urr ent I
O
50 mA
Power dis sipati on P
D
600 mW
Operat ing te mpe ratu re Topr 0 to +70
°C
Storag e t emp era ture Tstg -55 to +150
°C
NOTE:
1. The m aximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age
V
CC
4.5 5.0 5.5 V
GND000V
Input vol tage
V
IH
2.4 VCC + 0.3 V
V
IL
-1.0 0.8 V
CAPACITANCE (TA = 0 to +70°C, f = 1MHz, VCC = 5.0 V ±10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
Input cap acitan ce
A
0
- A
16
C
IN1
8pF
R/W,
OE C
IN2
5pF
CE1, CE
2
C
IN3
5pF
RFSH C
IN4
5pF
Input/ out put ca pac ita nce I/O
0
- I/O
7
C
OUT1
10 pF
DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%)
CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8128
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AC ELECTRICAL CHARACTERISTICS
1,2,3
(TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER SYMBOL
LH5P8128-60 LH5P8128-80 LH5P8128-10
UNIT NOTE
MIN. MAX. MIN. MAX. MIN. MAX.
Rand om read , w rit e c ycl e t ime t
RC
100 130 160 ns
Read mo dif y wr ite cy cle ti me
t
RMW
165 195 235 ns
CE p uls e w idt h
t
CE
60 10,000 80 10,000 100 10,000 ns
CE p rec har ge t ime
t
P
40 40 50 ns
Addr ess se tup ti me
t
AS
000ns4
Addr ess ho ld time
t
AH
15 20 25 ns 4
Read co mma nd s et up t ime t
RCS
000ns
Read co mma nd h ol d ti me
t
RCH
000ns
CE a cce ss tim e
t
CEA
60 80 100 ns 5
OE a cce ss tim e t
OEA
25 30 35 ns 5
CE t o o utpu t i n L ow- Z
t
CLZ
20 20 20 ns
OE to output in Low-Z t
OLZ
000ns
Outp ut e na ble fro m e nd o f w rit e t
WLZ
000ns
Chip di sab le to o utp ut in Hig h-Z t
CHZ
20 25 30 ns
Outp ut d is abl e to ou tpu t i n H igh -Z t
OHZ
20 25 30 ns
Write ena ble to ou tpu t in Hi gh- Z t
WHZ
20 25 30 ns
OE s etu p ti me t
OES
000ns
OE h old tim e t
OEH
10 10 10 ns
Write com man d p uls e w idt h t
WP
30 30 30 ns
Write com man d s etu p t ime t
WCS
30 30 30 ns
Write com man d h old ti me t
WCH
40 50 60 ns
Data se tup tim e f rom wri te t
DSW
25 30 35 ns 6
Data se tup tim e f rom
CE t
DS C
25 30 35 ns 6
Data ho ld t ime fr om w rit e t
DHW
000ns6
Data ho ld t ime fr om
CE t
DHC
000ns6
Transi tion time (ris e and fall) t
T
335335335ns
Refr esh tim e i nte rva l t
REF
888ms
Refr esh co mman d h old ti me t
RHC
15 15 15 ns
Auto re fres h c yc le t ime t
FC
100 130 160 ns
Refr esh de lay tim e f rom
CE t
RFD
30 40 50 ns
Refr esh pu lse wi dth (Aut o re fre sh)
t
FAP
30 8,000 30 8,000 30 8,000 ns
Refr esh pre ch arge ti me (Aut o re fre sh)
t
FP
30 30 30 ns
Refr esh pu lse wi dth (Se lf ref res h) t
FAS
8,000 8,000 8,000 ns
CE d ela y t ime fro m re fre sh prec har ge ( Sel f r efr esh )
t
FR S
140 160 190 ns
NOTES:
1. In order to initialize the circuit,
CE1 should be kept at VIH or CE
2
should be kept at VIL for 10 0 µs after power-up, followed by at least 8 dummy cycles.
2. AC characteristics are m easur ed at tT = 5 ns.
3. AC characteristics are measured at the following condition (see figure at right).
4. Address is latched at the negative edge of CE1 or at the positive edge of CE
2
.
5. M easured with a load equivalent to 2TTL + 100 pF.
6. Data is latched at the positive edge of W/R or at the positive edge of CE1 or at the negative edge of CE2.
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
OUTPUT
INPUT
5P8128-3
Figure 4. AC Characterist ics
LH5P8128 CMOS 1 M (128K × 8) Pseudo-Static RAM
4
Page 5
t
AS
t
AH
ADDRESS
INPUT
t
P
t
RC
t
CE
CE
1
V
IH
V
IL
t
RCS
R/W
V
IH
V
IL
t
OEA
t
CEA
t
OHZ
t
OLZ
t
CLZ
t
CHZ
t
RCH
t
RHC
t
FRS
t
FP
t
RFD
I/O0 - I/O
7
V
OH
V
OL
RFSH
V
IH
V
IL
CE
2
V
IH
V
IL
A0 - A
16
V
IH
V
IL
OE
V
IH
V
IL
5P8128-4
VALID-DATA OUTPUT
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 5. Read Cycle
CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8128
5
Page 6
t
AS
t
AH
ADDRESS
INPUT
t
P
t
RC
t
CE
CE
1
V
IH
V
IL
t
OES
R/W
V
IH
V
IL
t
DSW
t
DSC
t
OEH
t
RHC
t
FRS
t
FP
t
RFD
I/O0 - I/O
7
V
OH
V
OL
RFSH
V
IH
V
IL
CE
2
V
IH
V
IL
A0 - A
16
V
IH
V
IL
OE
V
IH
V
IL
5P8128-5
DATA INPUT
t
WCS
t
WCH
t
WP
t
DHW
t
DHC
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 6. Write Cycle 1 (OE = HIGH)
LH5P8128 CMOS 1 M (128K × 8) Pseudo-Static RAM
6
Page 7
t
AS
t
AH
ADDRESS
INPUT
t
P
t
RC
t
CE
CE
1
V
IH
V
IL
R/W
V
IH
V
IL
t
DSW
t
DSC
t
RHC
t
FRS
t
FP
t
RFD
RFSH
V
IH
V
IL
CE
2
V
IH
V
IL
A0 - A
16
V
IH
V
IL
OE
V
IH
V
IL
5P8128-6
VALID DATA INPUT
t
WCS
t
WCH
t
WP
t
DHW
t
DHC
t
WHZ
t
CLZ
V
OH
V
OL
V
IH
V
IL
I/O0 - I/O
7
D
IN
D
OUT
t
OHZ
t
WLZ
t
OLZ
t
CHZ
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 7. Write Cycle 2 (OE Clock)
CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8128
7
Page 8
t
AS
t
AH
ADDRESS
INPUT
t
P
t
RC
t
CE
CE
1
V
IH
V
IL
R/W
V
IH
V
IL
t
DSW
t
DSC
t
RHC
t
FRS
t
FP
t
RFD
RFSH
V
IH
V
IL
CE
2
V
IH
V
IL
A0 - A
16
V
IH
V
IL
OE
V
IH
V
IL
5P8128-7
VALID DATA INPUT
t
WCS
t
WCH
t
WP
t
DHW
t
DHC
t
WHZ
t
CLZ
V
OH
V
OL
V
IH
V
IL
I/O0 - I/O
7
D
IN
D
OUT
t
WLZ
t
CHZ
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 8. Write Cycle 3 (OE = LOW)
LH5P8128 CMOS 1 M (128K × 8) Pseudo-Static RAM
8
Page 9
t
AS
t
AH
ADDRESS
INPUT
t
P
t
RMW
CE
1
V
IH
V
IL
R/W
V
IH
V
IL
t
DSW
t
DSC
t
RHC
t
FRS
t
FP
t
RFD
RFSH
V
IH
V
IL
CE
2
V
IH
V
IL
A0 - A
16
V
IH
V
IL
OE
V
IH
V
IL
5P8128-8
DATA INPUT
t
DHW
t
DHC
t
OHZ
V
OH
V
OL
V
IH
V
IL
D
IN
D
OUT
t
OLZ
t
WLZ
t
CHZ
t
CEA
t
RCS
t
WCS
t
WP
DATA OUTPUT
t
OEA
t
WHZ
t
CLZ
I/O0 - I/O
7
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 9. Read-Modify-Write Cycle
CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8128
9
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t
AS
t
AH
ADDRESS
INPUT
t
P
t
RC
t
CE
CE
1
V
IH
V
IL
R/W
V
IH
V
IL
t
RHC
t
FRS
t
FP
t
RFD
RFSH
V
IH
V
IL
CE
2
V
IH
V
IL
A0 - A
8
V
IH
V
IL
OE
V
IH
V
IL
5P8128-9
V
OH
V
OL
I/O0 - I/O
7
t
OES
t
RCH
t
RCS
t
OEH
HIGH-Z
NOTE: A9 - A16 = Don't Care.
Figure 10. CE Only Refresh
CE
1
V
IH
V
IL
CE
2
V
IH
V
IL
CE
1
V
IH
V
IL
t
RFD
HIGH-Z
t
FP
t
FAS
t
FRS
t
RHC
CE
2
V
IH
V
IL
5P8128-10
V
OH
V
OL
RFSH
V
IH
V
IL
I/O0 - I/O
7
OR
NOTE: OE, R/W, A0 - A16 = Don't Care.
Figure 11. Self Refres h Cycle
LH5P8128 CMOS 1 M (128K × 8) Pseudo-Static RAM
10
Page 11
CE
1
V
IH
V
IL
CE
2
V
IH
V
IL
V
OH
V
OL
CE
1
V
IH
V
IL
t
RFD
t
FP
t
FC
HIGH-Z
t
FC
t
FP
t
FAP
t
FAP
t
FP
t
RHC
CE
2
V
IH
V
IL
RFSH
V
OH
V
OL
5P8128-11
I/O0 - I/O
7
OR
NOTE: OE, R/W, A
0
- A16 = Don't Care.
Fig ure 12. Auto Refres h Cycle
CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8128
11
Page 12
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050] TYP.
32
17
161
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100] TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
41.30 [1.626]
40.70 [1.602]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.50 [0.177]
4.00 [0.157]
15.24 [0.600] TYP.
32DIP (DIP032-P-0600)
116
1732
32DIP
32-pin, 600-mi l DIP
PACKAGE DIAGRAMS
LH5P8128 CMOS 1 M (128K × 8) Pseudo-Static RAM
12
Page 13
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32TSOP (Type I) (TSOP032-P-0820)
20.30 [0.799]
19.70 [0.776]
18.60 [0.732]
18.20 [0.717]
19.00 [0.748]
8.20 [0.323]
7.80 [0.307]
0.15 [0.006]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047] MAX.
0.20 [0.008]
0.10 [0.004]
0.30 [0.012]
0.10 [0.004]
0.50 [0.020] TYP.
32
1
32TSOP
16
1.10 [0.043]
0.90 [0.035]
17
0.425 [0.017]
32-pin, 8 × 20 mm2 TSOP (Type I)
60 60 80 80 10 100
LH5P8128
Device TypeXPackage
- ##
Speed
5P8128-12
CMOS 1M (128K x 8) Pseudo-Static RAM
Blank 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) T 32-pin, 8 x 20 mm
2
TSOP (Type I) (TSOP032-P-0820)
TR 32-pin, 8 x 20 mm
2
TSOP (Type I) Reverse bend (TSOP032-P-0820)
Example: LH5P8128N-60 (CMOS 1M (128K x 8) Pseudo-Static RAM, 60 ns, 32-pin, 525-mil SOP)
Access Time (ns)
ORDERING INFORMATION
CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8128
13
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