Datasheet LH540203U-50, LH540203U-25, LH540203U-20, LH540203U-15, LH540203K-50 Datasheet (Sharp)

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Page 1

LH540203

CMOS 2048 × 9 Asynchron ous FIFO

FEATURES

•• Fast Acces s Times : 15/20/ 25/ 35/50 ns

•• Fast- Fall-Through Time Ar chitect ure Based on

CMOS Dual-Port SRAM Tec hnology

•• Input Port and Output Port Have Entirely Indepen dent Timing

•• Expandable in Width and Depth

•• Full, Half-Full, and Empty Status Flags

•• Data Retransmission Capability

•• TTL-Compa tible I/O

•• Pin and Functionally Comp atible with Sharp LH5498

and with Am/IDT/ MS7203

•• Control Signals Assertive- LO W for Noise Immunit y

•• Packages:

28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC

FUNCTIONAL DESCRIP TIO N

The LH540203 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-po rt SRAM technology, capable of storing up to 2048 nine-bit words. It foll ows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540203 wor d m ay consist of a st andard eight -b it by te , toget her with a parity bit or a block-marking/ fram ing bit.

The input and output ports operate entirely independent ly of each other , unless the LH540203 becomes either tota lly full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, assertive- LOW con trol input s: Wr ite (W) for data ent r y at t he input por t, or Read ( R) for data retrieval at the output port .

Full, Half-Full, and Empty status flags monitor the extent to which the interna l memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempt ing to write addition al words into an already-f ull LH540203, or by att empting to r ead additional words from an already-empty LH540203. When an LH540203 is operating in a depth-cas caded configuration, the Half-Full Flag is not available.

PIN CONNECTIONS

28-PIN PDIP 28-PIN SOJ

1 2

28 27 26 25 24 23 22

21 20 19 18 17 16 15

Figure 1. Pin Connections fo r PDIP and

SOJ * Packages

FL/RT RS EF

XO/HF Q

TOP VIEW

540203-2D

32-PIN PLCC TOP VIEW

XI FF Q

NOTE: * = No external electrical connections are allowed.

11 12NC 13

D3D

5 6 7 8 9

NC*

FL/RT

XO/HF

540203-3D

Figure 2. Pi n Connecti ons for PLCC Package

* This is a final data sheet; except that all references to the SOJ package have Advance Information status .

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LH540203 CMOS 2048 × 9 Asynchronous FIFO

FUN CTIONAL DESCRIPTION (con t’d)

Data w ords are read out from the LH540203’s output port in precisely the same order that the y were writt en in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since the addressing sequence for a FIFO device’s memory is internally predefined, no external a ddressing inform ation is required for the operation of the LH540203 device.

Drop-in-replacement compatibility is maintained with both larger sizes and smaller sizes of industry-standard nine-bit asynchronous FIFOs. The only change is in the number of internally-stored data words implied by the states of the Full Flag and the Half-Full Flag.

The Retran smit (RT) cont r ol s ignal c auses the int ern a l FIFO- memo ry- ar ray re ad- addr ess po in ter t o be set back to zero, to point to the LH540203’s f irs t physical mem ory location, without affecting the internal FIF O-memoryarray write -ad dress pointer. Thus, the Retransmit cont rol signal provides a mechanism whereby a block of data, delimited by the zero physical address and the current write-a ddr ess- po int er value, may be read out an arbit rary number of times. The o nly rest riction s are t hat neither the read-address pointer nor the write-address pointer ma y ‘wrap ar ound’ during t his entire pro cess, i.e., advance past physical location zero after traversing the entire memory. The retransmit facility is not available when an LH540203 is operating in a depth-expanded configuration.

repea tedly

The Reset (RS) control signal returns the LH540203 to an initial state, empty and ready to be filled. An LH5 40203 sho uld be reset dur ing every syst em p ower- up sequence. A reset operation causes the internal FIFOmem or y-arr ay writ e-a ddr ess p ointe r , as we ll as the rea daddress pointer, to be set back to zero, to point to the LH540203 ’s first physical mem ory locat ion. Any info rmation which previously had been stored within the LH5 40203 is not recoverable af ter a reset operat ion.

A cascading (depth-expansion) scheme may be implemented by using the Expansion In (XI) input signal and the Expansion Out (XO/HF) output signal. This allows a deeper ‘effective FIFO’ to be implemented by using two or more LH540203 devices, without incurring additional laten cy (‘fallthro ugh’ or ‘bubblethrough’) d elays, and without the necessity of storing and r et rieving any given dat a word more tha n once. In this casc aded oper at ing mode , one LH540203 device must be designated as the ‘firstload’ or ‘master’ device, by grounding its First-Load (FL/RT) control input; the remaining LH540203 devices are designated as ‘slaves,’ by tying their FL/RT inputs HIGH. Because of the need to share control signals on pins, the Half- Full Flag and the retransm ission ca pability are not available for either ‘master’ or ‘slave’ LH540203 devices operating in cascaded mode.

RESET

LOGIC

INPUT

PORT

CONTROL

WRITE

POINTER

DATA INPUTS

- D

DUAL-PORT

RAM

ARRAY

2048 x 9

READ

POINTER

OUTPUT

PORT

CONTROL

. . .

DATA OUTPUTS

- Q

EF FF

XO/HF

540203-1

FL/RT

FLAG

LOGIC

EXPANSION

LOGIC

Figure 3. LH540203 Bloc k Diagram

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CMOS 2048 × 9 Asynchronous FIFO LH540203

PIN DESCRIPTIONS

O/Z

I O O

Input Data Bus Output Data Bus Write Request Read Request Empty Flag Full Flag

DESCRIPTION

PIN PIN TYPE

D0 – D

Q0 – Q

W R EF FF

NOTE:

1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

PIN PIN TYPE

XO/HF XI FL/RT RS V

I I

I V V

Expansion Out/Half-Full Flag Expansion In First Load/Retransmit Reset Positive Power Supply Ground

DESCRIPTION

OPERATIONAL DESCRIPT ION

Reset

The LH540 203 is r eset whenever the Reset input (RS) is taken LO W. A reset operat ion initializes bot h the readaddress pointer and the write- add res s point er to point to location zero, the first physical memory location. During a reset operation, the state of the XI and FL/RT inputs determines whethe r the device is in standalone mode or in depth- cascaded mode. (See Tables 1 and 2.) The reset operation forces the Empty Flag EF to be asserted (EF = LOW ), and t he Half-Full Flag HF and the Full Flag FF to be de assert ed (HF = FF = HIGH); the Data Out pins (D0 – D8) are for ced int o a hig h-im peda nce stat e.

A reset oper at ion is required when ever the LH540 203 first is powered up. The Read (R) and Write (W) inputs may be in any state when the re set oper atio n is initiated; but they must be HIGH, before the reset operation is terminated by a rising edge of RS, by a time t Read) or t

(for Write) respectively. (See Figure 10.)

WRSS

Write

A write cycle is initiated by a falling edge of the Write (W) contr ol input . Data setup tim es and hold times must be observed for the data inputs (D0 – D8). Write operations may occur independently of any ongoing read operation s. However , a write operat ion is possible only if the FIFO is not full, (i. e., if the Ful l Flag FF is HIGH).

At the fa lling e dge of W for the first write o peration after the memory is half filled, the Half-Full Flag is asserted (HF = LOW). It remains asserted until the difference between the write pointer and the read pointer indicates that the data words remaining in the LH540203 are filling the FIFO memory to less than or equal to one-half of its total capacity. The Half-Full Flag is deasserted (HF = HIGH) by the appropriate rising edge of R. (See Table 3.)

The Full F lag is as serted (FF = LOW) at the falling edge of W for the write operation which fills the last available location in the FIFO memory array. FF = LOW inhibits further write oper ations until FF is cleared by a va lid r ead

RRSS

(for

operation. The Full Flag is deasser ted (FF = HIGH) after the next rising edge of R releases anot he r mem ory lo cation. (See Table 3.)

Read

A read cycle is initiated by a falling edge of the Read (R) control input. Read data becomes valid at the data output s (Q0 – Q8) after a time tA from the falling e dge of R. After R goes HIGH, the data outputs return to a high-impedance stat e. Read oper ations m ay occur in dependently of any ongoing write operations. However, a read operation is possible only i f the FIFO is not empty (i.e., if the Empty Flag EF is HIGH).

The LH5402 03 ’s internal read-address and wri t eadd ress point er s oper ate in suc h a way that con secut ive read operations always access data words in the same order that they wer e written . The Empty Flag is asse rted (EF = LOW) after that falling edge of R which accesses the last available data word in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another valid data wor d. (See Table 3.)

Data Flow-Through

Read-data flow- throu gh mode occurs when the Read (R) cont rol inpu t is brought LOW while the FIFO is empty , and is held LOW in antic ipation of a write cycle. At the end of the next write cycle, the Empty F lag EF momentarily is deasserted, and the data word just written becomes available at the data outputs (Q0 – Q8) after a maximum time of t

+ tA. Additional write operations may occur

WEF

while the R input remains LOW; but only data from the first write operation flows through to the data outputs. Additional data words, if any, may be accessed only by toggling R.

Write-data flow-through mode occurs when the Write (W) input is brought LOW while t he FIFO is full, and is held LOW in anticipation of a read cycle. At the end of the read cycle, the Full Flag momentarily is deasserted, but then immediately is reasserted in response to W being held LOW. A data word is written into the FIFO on the rising edge of W, which may occur no sooner than t

RFF

+ t

after the read oper ation.

WPW

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LH540203 CMOS 2048 × 9 Asynchronous FIFO

OPERATIONAL DESCRIPTI ON (cont’ d)

Retransmit

The FIFO can be made to reread previously-read data by means of the Retransmit function. A retransmit operation is initiated by pulsing the W must be deasserted (HIGH) for the duration of the retransmit pulse. The FIFO’s internal read-address pointer is reset to point to location zero, the first physical memory location, while the internal write-address pointer remains unchanged.

After a retransmit operation, those data words in the region in between the read-address pointer and the write-address pointer may be reaccessed by subsequent read operations. A retransmit operation may affect the state of the status flags the relocation of the read-address pointer. There is no restriction on the number of times that a block of data within an LH540203 may be read out, by repeating the retransmit operation and the subsequent read operations.

The maximum length of a data block which may be retransmitted is 2048 words. Note that if the write-address pointer ever ‘wraps around’ (i.e., passes location zero more than once) during a sequence of retransmit operations, some data words will be lost.

RT input LOW. Both R and

FF, HF, and EF, depending on

Table 2. Expansion-Pin Usage Acco rding t o

Grouping Mode

I/O PIN

XI Grounded

STANDALONE

CASCADED

MASTER

From (n-1st

CASCADED

FIFO)

XO/HF

FL/RT

Becomes HF

Becomes RT

To (n+1st FIFO)

Grounded (Logic LOW)

Table 3. Status Flags

NUMBER OF UNREAD DATA

WORDS PRESENT WITHIN

2048 × 9 FIFO

FF HF EF

0HHL

1 to 1024 H H H

1025 to 2047 H L H

SLAVE

From XO (n-1st FIFO)

To XI (n+1st FIFO)

Logic HIGH

The Retransmit function is not available when the LH540203 is operating in depth-cascaded mode, because the

FL/RT control pin must be used for first-load

selection rather than for retransmission control.

Table 1. Grouping-Mode Determinatio n

During a Reset Operation

FL/

NOTES:

1. A re set operation forces XO HIGH for the n

2. The terms ‘master’ and ‘slave’ refer to opera tion in depth-cas-

3. H = HIGH; L = LOW; X = Don’t Care.

XI HIGH for the (n+1)st FIFO. caded grouping mode.

MODE

Cascaded

Slave Cascaded

Master

Standalone

XO/HF

USAGEXIUSAGE

XO XI FL

XO XI FL HF (none) RT

FIFO, thus forcing

FL/RT

USAGE

2048 L L H

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CMOS 2048 × 9 Asynchronous FIFO LH540203

OPER ATIONAL MO DES

Standalo n e Configuration

When depth cascading is not required for a given application, the LH540203 is placed in st anda lone mode by tying the Expansion In input (XI) to gro und. This input is interna lly samp led during a reset operatio n. (See Table 1.)

WRITE

DATA IN

- D

FULL FLAG

LH540203

Width Expansion

Word -width expansion is imp lemented by placing multiple LH540203 devices in parallel. Each LH540203 should be configured for standalone mode. In this arrangem ent, the behavior of the status flags is ident ical for all devices; so, in principle, a representative value for each of these flags could be der ived from any one device . In practice, it is be tter to derive ‘composite’ flag values using external logic, since there may be minor speed variat ions between differe nt actua l devices. (See Figures 4, 5, an d 6 .)

READ

DATA OUT

- Q

EMPTY FLAG

DATA IN

- D

WRITE

FULL FLAG

RESET

W FF RS

Figur e 4. Standalone FI FO (2048 × 9)

LH540203

RETRANSMIT

RT 9

EMPTY FLAG READ

RETRANSMIT

540203-17

DATA OUT

- Q

Figure 5. FIFO Word-Width Expansion ( 2048 × 18)

540203-18

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LH540203 CMOS 2048 × 9 Asynchronous FIFO

OPER ATIONAL MO DES (cont’d )

Depth Cascading

Depth cascading is implemented by configuring the required nu mber of LH540203s in dept h-casca ded mode. In this arrangem ent, the FIFOs are c onnected in a circular fashion, with the Expansion Out output (XO) of each device tied to the Expansion In input (XI) of the next device. One FIFO in the c ascad e must be designat ed as the ‘f irst - load’ device, by t ying its First Load input ( FL/RT) to ground. Al l ot her devices m ust have th eir FL/R T inpu ts tied HIGH. In this mode, W and R signals are share d by all devices, while logic within each LH540203 controls the steering of data. Only one LH540203 is enabled during any given write cycle; thus, the common Data In inputs of

DATA IN

- D

LH540203

all devices are tied together. Likewise, only one LH540203 is enabled during any given read cycle; thus, the common Da ta Out outputs of all devices are wireORed toget her.

In depth-cascaded mode, external logic should be used t o gene rate a composite F u ll Flag and a compos ite Empty Flag, by ANDing the FF ou tputs of all LH540203 devices together and ANDing the EF outputs of all devices together. Since FF and EF are assertive-LOW sign als , this ‘ANDing’ actually is implemented using an a sser tive-HIGH physical OR gate. The Half-Full Flag and the Retr ansm it funct ion are not available in depth- casc aded mode.

Vcc

DATA OUT

- Q

FULL

LH540203

Vcc

Figur e 6. FIFO Depth Cascadi ng (6144 × 9)

EMPTY

540203-19

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CMOS 2048 × 9 Asynchronous FIFO LH540203

OPER ATIONAL MO DES (cont’d )

Compound FIFO Expansion

A combination of word-width expansion and depth cascading may be implemented easily by operating groups of depth- casc aded FI FO s in parallel.

Bidirect ional FIFO Operat ion

Bidirectional data buff ering between two systems may be implemente d by operating LH540203 devices in parallel, b ut in o pposite direct ions. The Dat a In in puts of ea ch

- Q

R W RS

DATA IN

LH540203

DEPTH EXPANSION

BLOCK

D0 - D

N-1

D9 - D

N-1

LH540203

DEPTH EXPANSION

LH540203 are tied to the corresponding Data Out outputs of another LH540 203, which is operating in the opposite directio n, to form a single b idirectional bus inte rface. Care must be tak en to assur e th at the app ropriat e re ad, write , and flag signals are routed to each system. Both wordwidth expansion and depth cascading may be used in bidirectional applications.

Q0 - Q

BLOCK

D18 - D

N-1

Q0 - Q

N-10

DEPTH EXPANSION

N-9 - DN-1

Q0 - Q

LH540203

BLOCK

N-1

ARRAY STORES N-BIT WORDS.

DATA OUT

540203-20

Figure 7. Compound FIFO Expansion

FFa

LH540203

0 - 8

SYSTEM A SYSTEM B

0 - 8

EFa

HFa RTa

LH540203

0 - 8

Rb EFb

HFb RTb

FFb

Figur e 8. Bidirect i onal FIFO Operat io n

(2048 × 9 × 2)

540203-21

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LH540203 CMOS 2048 × 9 Asynchronous FIFO

ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING

Supply Voltage to VSS Potential –0.5 V to 7 V Signal Pin Voltag e to VSS Potential

DC Output Curr ent

–0.5 V to VCC + 0.5 V (not to exceed 7 V)

± 50 mA Stor age Temp era ture Range –65oC to 150oC Power Dissip ation (Package Limit ) 1.0 W DC Volta ge Applied to Outputs In High-Z State –0.5 V to VCC + 0.5 V (not to exceed 7 V)

NOTES:

1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions outside of those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended period s ma y affect reliability.

2. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle .

3. Outputs should not be shorted for more than 30 seconds. No more than one output sho uld b e shorted at any time.

OPERATING RANGE

SYMBOL PARAMETER MIN MAX UNIT

VCCSu pply V olta ge

T em peratur e, Ambient

070

°C

4.5 5.5 V

VILLogic LO W Input Vo ltage V

NOTE:

1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle .

Su pply V olta ge

Logic HIG H Input V olt age

00V

–0.5 0.8 V

2.0 VCC + 0.5 V

DC ELECTRICAL CHARACTERISTICS (Over Operat ing Range)

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT

CC2

CC3

NOTE:

1. I

Input Leakage Current VCC = 5.5 V, VIN = 0 V to V Outp ut Leakage Cur re nt R ≥ VIH, 0 V ≤ V

Outp ut HIGH V ol t age IOH = –2.0 mA Outp ut LOW V ol t age IOL = 8.0 mA Average Supply Current Average Standby Current Power Down Curr ent

, I

CC2

, and I

are dependent upon actual output loading and cycl e r a tes. Specified values are with outputs open.

CC3

Measur ed at f = 40 MHz

All Input s = V

All Input s = VCC – 0. 2 V

CC –10 10 µA

OUT

≤ V

–10 10 µA

2.4 V

0.4 V

100 mA

15 mA

5mA

Page 9

CMOS 2048 × 9 Asynchronous FIFO LH540203

AC TEST CONDITIONS

PARAMETER RATING

Input Pulse Levels Input Rise and Fall T imes (10% t o 90% ) Input Timing Reference Levels Output Re ferenc e Levels Output Load , Timin g T es ts

CAP ACITANCE

1,2

PARAMET ER RA TING

CIN (Input Capacitance) C

(Output Capacitanc e)

OUT

NOTES:

1. Sample tested only.

2. Capacitances are maximum values at 25 with VIN = 0 V.

VSS to 3 V

5 ns

1.5 V

Figure 9

5 pF 7 pF

C, measured at 1.0 MHz,

+5 V

1.1 k Ω

DEVICE UNDER

TEST

INCLUDES JIG AND SCOPE CAPACITANCES

680 Ω

30 pF

Fig ur e 9. Out put Lo a d Circ uit

540203-4

Page 10

LH540203 CMOS 2048 × 9 Asynchronous FIFO

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER

RPW

RLZ

WLZ

RHZ

WPW

RSC

RSR

RRSS

WRSS

RTC

RTR

EFL

HFH,FFH

REF

RFF

WEF

WFF

WHF

RHF

XOL

XOH

XIR

XIS

NOTES:

1. All timing measurements are performed at ‘AC Test Condition’ levels.

2. Pulse widths le ss than minimum value are not allowed.

Read Cycle Time Access T im e Read Recovery Time Read Pulse Wi dt h Data Bus Active from Read LOW Data Bus Active from Write HIGH

3,4

Data Valid from Re ad Pulse HIGH Data Bus High-Z from Read HIGH

Write Cy cle T i me 25 – 30 – 35 – 45 – 65 – ns Write Pulse Width

Write Re cove ry Time Data Setup Time 12–12–12–15–20–ns Data Hold Time 0–0–0–0–0–ns

Reset Cycle Time Reset Pulse Width

Reset Recovery Time 10–10–10–10–15–ns Read HIGH to RS HIGH 15–20–25–35–50–ns Write HIGH to RS HIGH

Retransmi t Cycl e Time 25 – 30 – 35 – 45 – 65 – ns Retransmit Pulse Width

Retransmi t Reco ve ry Time 10 – 10 – 10 – 10 – 15 – ns

Reset LOW t o Em pty Flag LOW – 25 – 30 – 35 – 45 – 65 ns Reset LOW to Half-Full and Full

Flags HIGH Read LOW to Em p ty F la g LO W Read HIGH t o Fu ll Flag HIGH – 15 – 20 – 25 – 35 – 45 ns Write H IG H to Em pty Flag HIGH – 15 – 20 – 25 – 35 – 45 ns Write LOW to Fu ll Fla g LOW – 15 – 20 – 25 – 35 – 45 ns Write LOW to Hal f- Full Flag LO W Read HIGH to Half-Full Flag HIGH

Expansion Out LO W – 18 – 20 – 25 – 35 – 50 ns Expansion Out HIG H Expansion In Pulse Width Expansion In Re cove ry Time Expansion in Setu p Time 7 – 10 – 10 – 15 – 15 – ns

(Over Operating Range)

= 15 ns tA = 20 ns tA = 25 ns tA = 35 ns tA = 50 ns

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

READ CYCLE TIMING

25–30–35–45–65–ns

–15–20–25–35–50ns 10–10–10–10–15–ns 15–20–25–35–50–ns

5–5–5–5–5–ns 10–10–10–10–10–ns

5–5–5–5–5–ns

–15–15–15–15–20ns

WRITE CYCLE TIMING

15–20–25–35–50–ns 10–10–10–10–15–ns

RESET TIMING

25–30–35–45–65–ns 15–20–25–35–50–ns

15–20–25–35–50–ns

RETRANSMIT TIMING

15–20–25–35–50–ns

FLAG TIMING

–25–30–35–45–65ns

–15–20–25–35–45ns

EXPANSION TIMING

–18–20–25–35–50ns 15–20–25–35–50–ns 10–10–10–10–10–ns

UNIT

Page 11

CMOS 2048 × 9 Asynchronous FIFO LH540203

TIMING DIAGRAMS

RSC

R,W

FF,HF

NOTES:

RSC

= tRS + t

1. t

2. W and R ≥ V

3. The Data Out pins (D

RSR

around the rising edge of RS.

- D8) are forced into a

high-impedance state whenever EF = LOW.

RRSS

WRSS

EFL

FFHtHFH

Figure 10. Reset Timing

RPW

RSR

540203-14

Q0 - Q

D0 - D

RLZ

VALID DATA OUT

WPW

VALID DATA OUT

RHZ

VALID DATA IN

540203-5

Figure 1 1 . Asynchronous Write and Read Operat ion

Page 12

LH540203 CMOS 2048 × 9 Asynchronous FIFO

TIMING DI AGRAMS (cont ’d)

LAST WRITE FIRST READ

RFF

WFF

540204-6

Figure 12. Full Flag From Last Writ e to Firs t Read

LAST READ FIRST WRITE

REF

WEF

NOTE: The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.

Figure 13. Empty Flag From Last Read to First Writ e

540203-7

Page 13

CMOS 2048 × 9 Asynchronous FIFO LH540203

TIMING DI AGRAMS (cont ’d)

D0 - D

Q0 - Q

NOTES:

= t

1. t

RPE

2. t

3. The Data Out pins (D high-impedance state whenever EF = LOW.

RPW

: Effective Read Pulse Width after Empty Flag HIGH.

RPE

- D8) are forced into a

VALID DATA IN

t t

WEF

WLZ

REF

Figur e 14. Read Data Flow-Throu gh

RPE

VALID DATA OUT

540203-8

D0 - D

Q0 - Q

NOTES:

1. t

WPF

2. t

WPF

= t

WPW.

: Effective Write Pulse Width after Full Flag HIGH.

VALID DATA OUT

Figure 15. Write Data Flow-Through

RFF

WFF

WPF

VALID DATA IN

540203-9

Page 14

LH540203 CMOS 2048 × 9 Asynchronous FIFO

TIMING DI AGRAMS (cont ’d)

WEF

RPE

NOTES:

= t

1. t

RPE

2. t

3. The Data Out pins (D high-impedance state whenever EF = LOW.

RPW

: Effective Read Pulse Width after Empty Flag HIGH.

RPE

- D8) are forced into a

Figure 16. Empty Flag T iming

540203-10

NOTES:

= t

1. t

WPF

2. t

WPW.

: Effective Write Pulse Width after Full Flag HIGH.

WPF

HALF-FULL

OR LESS

RFF

Figure 17. Full Flag Ti mi n g

MORE THAN

HALF-FULL

WPF

HALF-FULL

OR LESS

540203-11

WHF

Figure 18. Half-Full Flag Timing

RHF

540203-12

Page 15

CMOS 2048 × 9 Asynchronous FIFO LH540203

TIMING DI AGRAMS (cont ’d)

RTR

R,W

NOTES:

1. t

2. FF, HF, and EF may change state during retransmit; but they will become valid by t

RTC

= tRT + t

RTR

RTC

WRITE TO LAST

AVAILABLE

LOCATION

540203-13

Figure 19 . Retransm it Timin g

READ FROM

LAST VALID

LOCATION

XOL

XOH

XOL

XOH

540203-15

Figure 20. Expansion-Out Timing

XIS

WRITE TO FIRST

AVAILABLE

LOCATION

XIR

XIS

READ FROM FIRST

VALID

LOCATION

540203-16

Figur e 21. Expansion-In Timi ng

Page 16

LH540203 CMOS 2048 × 9 Asynchronous FIFO

PACKAGE DIAGRAMS

28DIP (DIP28-W-300)

2.54 [0.100] TYP.

DIMENSIONS IN MM [INCHES]

34.80 [1.370]

34.54 [1.360]

0.53 [0.021]

0.38 [0.015]

MAXIMUM LIMIT

MINIMUM LIMIT

7.49 [0.295]

7.11 [0.280]

3.30 [0.130]

4.57 [0.180] MAX

3.43 [0.135]

3.18 [0.125]

0.51 [0.020] MIN

DETAIL

0° TO 15°

0.30 [0.012]

0.20 [0.008]

7.62 [0.300] TYP.

28DIP-3

28-pin, 300-mil PDI P

28SOJ (SOJ28-P-300)

28 15

7.9 [0.311]

7.5 [0.295]

114

18.7 [0.736]

18.3 [0.720]

1.15 [0.045]

0.85 [0.033]

1.27 [0.050] TYP.

DIMENSIONS IN MM [INCHES]

0.53 [0.021]

0.33 [0.013]

MAXIMUM LIMIT

MINIMUM LIMIT

8.63 [0.340]

8.23 [0.324]

0.102 [0.004]

0.20 [0.008]

3.7 [0.146]

3.3 [0.130]

DETAIL

2.6 [0.102]

2.2 [0.087]

0.64 [0.025] MIN

0.8 [0.031]

0.6 [0.024]

7.0 [0.276]

6.6 [0.260]

28SOJ300

28-pin, 300-mil SOJ

Page 17

CMOS 2048 × 9 Asynchronous FIFO LH540203

32PLCC (PLCC32-P-R450)

1.27 [0.050]

4 SIDES BSC

15.11 [0.595]

14.86 [0.585]

14.05 [0.553]

13.89 [0.547]

11.51 [0.453]

11.35 [0.447]

12.57 [0.495]

12.32 [0.485]

DETAIL

0.81 [0.032]

0.66 [0.026]

13.46 [0.530]

12.45 [0.490]

3.56 [0.140]

0.10 [0.004]

DIMENSIONS IN MM (INCHES)

3.12 [0.123]

MAXIMUM LIMIT

MINIMUM LIMIT

ORDERING INFO RMATION

LH540203

Device Type

Package

10.92 [0.430]

9.91 [0.390]

32-pi n, 450-mi l PLCC

- ##

Speed

15 20

Access Time (ns)

25 35 50

2.41 [0.095]

1.52 [0.060]

0.38 [0.015] MIN

0.53 [0.021]

0.33 [0.013]

32PLCC

D 28-pin, 300-mil Plastic DIP (DIP28-W-300) K 28-pin, 300-mil SOJ * (SOJ28-P-300) U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450)

CMOS 2048 x 9 FIFO

* Contact a Sharp representative for availability of SOJ package.

Example: LH540203U-25 (CMOS 2048 x 9 FIFO, 32-pin PLCC, 25 ns)

540203MD