Page 1
LH53517
CMOS 512K (64K × 8) MROM
FEATURES
•• 65,536 words × 8 bi t organi zation
•• Access time: 150 ns (MAX.)
•• Low-pow er consumption :
Operating : 16 5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Mask-pro grammable OE /
OE
•• Packages:
28-pi n , 600 -mil DIP
28-pi n , 450 -mil S OP
28-pi n , 8 × 13.4 mm
2
TSOP (Type I)
DESCRIPTION
The LH53517 is a mask-programmable ROM organized as 65,536 × 8 bits. It is f abricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
53517-1
TOP VIEW
1
2
3
4
7
8A
2
A
5
26
25
24
23
22
21
18
15
A
7
A
6
5
6
A
3
A
4
20
19
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
9
10
11
28
27 A
14
A
1
V
CC
12 17 D
5
16 D
4
D
1
D
2
A
0
D
0
A
9
OE/OE
28-PIN DIP
28-PIN SOP
13
14
Figure 1. Pin Connections for DI P and
SOP Packages
2
3
4
5
6
9
10
7
8
A
11
11
1
28
27
26
25
22
21
24
23
20
19
A
10
28-PIN TSOP (Type I)
12
13
14
17
16
18
15
OE/OE
A
8
A
9
A
12
D
2
D
1
A
1
D
7
CE
D
5
D
6
GND
D
4
D
3
D
0
A
0
53517-2
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
TOP VIEW
A
15
A
14
A
13
NOTE: Reverse bend available on request.
Figure 2. Pin Connect ions for TSOP Package
1
Page 2
NOTE:
1. Active level of OE/OE is mask-programm able.
TRUTH TABLE
CE OE/OE DATA OUTPUT CURRENT CONSUMPTION
HX
High-Z
Standby
L
L/H
Operating
H/L Output
NOTE:
X = H or L
ABSOLUTE MAXIMUM RATINGS
53517-3
A
2
A
11
A
10
A
9
A
8
A
7
28
23
21
24
25
5
8
A
6
A
5
V
CC
A
3
MEMORY
MATRIX
(65,536 x 8)
SENSE AMPLIFIER
14
4
GND
7
3
A
4
6
A
12
2
OE/OE
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
13
26
A
14
27
TIMING
GENERATOR
A
15
1
DATA
OUTPUT BUFFER
A
1
A
0
9
10
22
20
1617
18
11
19
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
15
12
13
NOTE: Pin numbers apply to the 28-pin DIP or SOP.
Figure 3. LH53517 Block Diagr am
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A0 – A
15
Addre ss inp ut
D0 – D
7
Data out put
CE Chip ena ble in put
SIGNAL PIN NAME NOTE
OE/OE Outp ut e nab le inp ut 1
V
CC
Power s upp ly (+5 V )
GND Groun d
LH53517 CMOS 512K MROM
2
Page 3
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
–0.3 to VCC + 0.3 V
Operat ing te mpe ratu re Topr 0 to +70
°C
Storage temperature Tstg –65 to +150
°C
RECOMMENDED OPERATING CONDITIO NS (T
A
= 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. M AX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ± 10%, TA = 0 t o +70°C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input ‘Lo w’ voltage V
IL
–0.3 0.8 V
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Output ‘L ow’ v olt age V
OL
IOL = 1 .6 m A 0.4 V
Output ‘H igh ’ vol tag e V
OH
IOH = –4 00 µA
2.4 V
Input lea kag e c urr ent
| I
LI
|
V
IN
= 0 V to V
CC
10 µA
Output leakage current | I
LO
|V
OUT
= 0 V to V
CC
10
µA
1
Operat ing cu rre nt
I
CC1
tRC = 15 0 n s 30
mA 2
I
CC2
tRC = 1 µs
15
I
CC3
tRC = 15 0 n s 25
mA 3
I
CC4
tRC = 1 µs12
Standb y c urr ent
I
SB1
CE = V
IH
2mA
I
SB2
CE = VCC – 0.2 V 100 µA
Input cap acitan ce C
IN
f = 1 MHz
T
A
= 25°C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE/OE = V
IH
, OE = V
IL
2. VIN = VIH/VIL, CE = VIL, outputs open
3. V
IN
= ( VCC – 0. 2 V), 0.2 V, CE = 0.2 V, outputs open
AC CHARACTERISTICS (V
CC
= 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read c yc le t ime t
RC
150 ns
Addres s a cc ess ti me t
AA
150 ns
Chip e nab le acc es s ti me t
ACE
150 ns
Output en abl e d ela y t ime t
OE
10 80 ns
Output ho ld time t
OH
5ns
CE to out put in Hig h-Z t
CHZ
70 ns 1
OE to out put in Hig h-Z t
OHZ
70 ns 1
NOTE:
1. T his is the time required for the output to become high-impedance.
CMOS 512K MROM LH53517
3
Page 4
AC TEST CONDITIONS
PARAMETE R RATING
Input voltage amplitude 0.6 V to 2.4 V
Input ris e/f all tim e 10 ns
Input ref erence level 1.5 V
Output reference level 0.8 V and 2.2 V
Output load condition 1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that
a hig h-frequency bypass capaci tor be connected between the VCC pin and the GND pin.
t
OE
(NOTE)
t
AA
A0 - A
15
t
OHZ
t
CHZ
D0 - D
7
53517-4
t
RC
t
ACE
CE
OE
t
OH
DATA VALID
(NOTE)
(NOTE)
OE
NOTE: Data becomes valid after the intervals t
AA
, t
ACE
, and t
OE
from address
input, chip enable, and output enable, respectively have been met.
Figure 4. Timi n g Diagram
LH53517 CMOS 512K MROM
4
Page 5
PACKAGE DIAGRAMS
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28DIP (DIP028-P-0600)
114
1528
28DIP-2
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
36.30 [1.429]
35.70 [1.406]
0° TO 15°
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
28-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOP (SOP028-P-0450)
12.40 [0.488]
11.60 [0.457]
8.80 [0.346]
8.40 [0.331]
10.60 [0.417]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
28 15
141
1.70 [0.067]
1.70 [0.067]
28SOP
28-pin, 450-mil S OP
CMOS 512K MROM LH53517
5
Page 6
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28TSOP (TSOP028-P-0813)
28
1
28TSOP
14
15
0.28 [0.011]
0.12 [0.005]
0.55 [0.022]
TYP.
12.00 [0.472]
11.60 [0.457]
13.70 [0.539]
13.10 [0.516]
8.20 [0.323]
7.80 [0.307]
0.15 [0.006]
1.10 [0.043]
0.90 [0.035]
1.20 [0.047]
MAX.
12.60 [0.496]
12.20 [0.480]
0.20 [0.008]
0.10 [0.004]
0.20 [0.008]
0.00 [0.000]
1.10 [0.043]
0.90 [0.035]
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
0 - 10°
DETAIL
0.425 [0.017]
28-pin, 8 × 13 mm2 TSOP (Type I)
D 28-pin, 600-mil DIP (DIP028-P-0600)
N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13.4 mm
2
TSOP (Type I) (TSOP028-P-0813)
TR 28-pin, 8 x 13 mm
2
TSOP (Type I) Reverse bend (TSOP028-P-0813)
LH53517
Device Type
X
Package
53517-5
Example: LH53517D (CMOS 512K (64K x 8) Mask Programmable ROM, 28-pin, 600-mil DIP)
CMOS 512K (64K x 8) Mask Programmable ROM
ORDERING INFORMATION
LH53517 CMOS 512K MROM
6
Loading...