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LH5332600
CMOS 32M (4M × 8/2M × 16) MROM
FEATURES
•• 4,194,304 × 8 bi t organ izatio n
(Byte mode: BYTE = VIL)
2,097,1 52 × 16 bit organi zation
(Word mode: BYTE = VIH)
•• Access time: 100 ns (MAX.)
•• Supply curre nt :
– Operating: 100 mA (MAX.)
– Standby: 100 µA (MAX.)
•• TTL compatible I/O
•• Three-state output
•• Singl e +5 V p owe r su ppl y
•• Static operation
•• Packages:
44-pi n , 600 -mil S OP
48-pi n , 1 2 mm × 18 mm
2
TSOP (Type I)
•• Others :
– Non programmab le
– Not de sign ed o r rate d as rad iatio n
hardene d
– CMOS process (P typ e sil icon
substrate)
DESCRIPTION
The LH5332600 is a 32M-bit mask-programmable
ROM organized a s 4 ,194,304 × 8 bits (Byte mode) or
2,097,152 × 16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
5332600N-1
TOP VIEW
5
6
7
8
11
12
34
33
32
31
30
29
26
9
10
28
27
A
15
A
16
BYTE
13
14
15
36
35
A
13
16
25
D15/A
-1
(NOTE)
D
13
D
5
D
6
A
14
44-PIN SOP
3
4
38
37
1
2
40
39
A
10
D
14
D
7
24
23
V
CC
D
4
D
12
17
18
19
20
A
9
A
11
A
12
41
A
8
A
19
A
20
42
21
OE
A
1
A
0
GND
CE
A
2
D
8
D
9
A
3
A
4
A
5
A
6
D
1
A
7
D
2
D
3
D
10
A
17
A
18
D
0
GND
D1122
NC
43
44
NOTE: The D15/A-1 pin becomes LSB address input (A-1)
when the BYTE pin is set to be LOW in byte mode and
data output (D
15
) when set to be HIGH in word mode.
Figure 1. SOP Pin Connections
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5332600T-1
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7
A
11
A
12
39
38
D
7
D
3
10
11
12
47
46
D
15/A-1
(NOTE)
A
9
13
36
35
A
8
48-PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE
D
10
GND
48
1
A
16
BYTE
22
27
D
0
GND
23
26
V
CC
24
25
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
A
19
A
20
A
18
A
17
NOTE: The D15/A-1 pin becomes LSB address input (A-1)
when the BYTE pin is set to be LOW in byte mode and
data output (D
15
) when set to be HIGH in word mode.
Figure 2. TSOP Pin Connections
LH5332600 CMOS 32 M (4M x 8/2M x 16) MROM
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5332600N-2
A
4
A
3
A
13
A
12
A
11
A
10
A
9
37
38
39
40
4
7
8
A
8
A
7
A
5
MEMORY
MATRIX
(4,194,304 x 8)
(2,097,152 x 16)
SENSE AMPLIFIER
42
33
6
A
1
A
0
10
11
A
2
9
41
A
6
5
A
14
36
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
15
35
A
16
34
12
TIMING
GENERATOR
A
17
3
BYTE
A
18
2
A
19
43
A
20
44
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
14
OE
DATA SELECTOR/OUTPUT BUFFER
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
22
20
18
16
26
19
17
15
21
30
24
25
27
29
31
28
31
A
-1
V
CC
23
GND
13 32
Figure 3. LH5332600 Block Diagram
PIN DESCRIPTION
SIGNA L PIN NAME
A
-1
- A
20
Addr ess in put
D
0
- D
15
Data ou tput
BYTE
×8bit / ×16 bi t
(byt e/wo rd) mo de
sele ct input
CE Chip en abl e in pu t
SIGNAL PIN NAME
OE Outpu t e nab le i np ut
V
CC
Power su ppl y
GND Groun d
NC
No co nne cti on
(Non wire bonding)
CMOS 32M (4M x 8/2M x 16) MROM LH5332600
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TRUTH TABLE
CE OE BYTE
A
-1
(D15)
DATA OUTPUT AD DRESS INPUT
SUPPLY
CURRENT
D
0
- D
7
D8 - D
15
LSB MSB
H X X X High-Z High-Z
Standby (ISB)
L H X X High-Z High-Z
Operating
LL H D
0
- D
7
D8 - D
15
A
0
A
20
Operating
LL L L D
0
- D
7
High-Z A
-1
A
20
Operating
LL L H D
8
- D
15
High-Z A
-1
A
20
Operating
NOTES:
X = Don’t care; High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
-0.3 to +7.0 V
Input vol tage V
IN
-0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
-0.3 to VCC + 0.3 V
Operat ing te mpe ratu re
T
OPR
0 to +70 °C
Storag e t emp era ture T
STG
-65 to +150
°C
RECOMMENDED OPERATING CON DITIONS (TA = 0 to +7 0°C)
PARAMETER SYMBOL M IN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ± 10%, TA = 0 to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input ‘Hi gh’ voltage V
IH
2.2 V
CC
+ 0.3 V
Input ‘Lo w’ voltage V
IL
-0.3 0.8 V
Output ‘H igh ’ vol tag e V
OH
IOH = -400 µA 2.4 V
Output ‘L ow’ v olt age V
OL
IOL = 2 .0 mA 0.4 V
Input lea kag e c urr ent
| I
LI
|
V
IN
= 0 V to V
CC
10 µA
Output le aka ge cur ren t | I
LO
|V
OUT
= 0 V to V
CC
10
µA
1
Operat ing cu rre nt
I
CC1
tRC = 10 0 n s
100
mA 2
I
CC2
tRC = 1 µs
90
Standb y c urr ent
I
SB1
CE = V
IH
2mA
I
SB2
CE = VCC - 0.2 V
100
µA
Input cap acitan ce
C
IN
f = 1 MHz , tA = 25°C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE = VIH, OE = V
IH
2. VIN = VIH or VIL, CE = VIL, output is open
LH5332600 CMOS 32 M (4M x 8/2M x 16) MROM
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AC ELECTICAL CHARACTERISTICS (V
CC
= 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL MI N. MAX. UNIT NOTE
Read c yc le t ime t
RC
100
ns
Addres s a cc ess ti me t
AA
100 ns
Chip e nab le acc es s ti me t
ACE
100 ns
Output en abl e d ela y t ime
t
OE
50 ns
Output ho ld time
t
OH
5 ns
Output fl oat ing tim e
t
CHZ
40 ns
1
t
OHZ
40 ns
NOTE:
1. Determ ined by the time f or the output to be opened. (Irrespective of out put voltage)
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude 0.4 V to 2.6 V
Input rise/fall time 10 ns
Input sig nal fall time 10 ns
Input ref erence level 1.5 V
Output re fere nc e le ve l 1.5 V
Output load condition 1TTL + 100 pF
CAUTION
It is recommended that a decoupling capacitor be connected between VCC and GND-Pin.
CMOS 32M (4M x 8/2M x 16) MROM LH5332600
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t
AA
A
-1
- A
20
t
OHZ
t
CHZ
D0 - D
7
5332600N-3
t
RC
t
ACE
CE
DATA VALID
(NOTE)
(NOTE)
OE
t
OE
(NOTE)
t
OLZ
t
OH
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, or tOE, have concluded.
Figure 4. Byte Mode (BYTE = VIL)
t
AA
A
-1
- A
20
t
OHZ
t
CHZ
5332600N-4
t
RC
t
ACE
CE
DATA VALID
(NOTE)
(NOTE)
OE
t
OE
(NOTE)
(D0 - D15)
t
OH
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, or tOE, have concluded.
Figure 5. Word Mode (BYT E = VIH)
LH5332600 CMOS 32 M (4M x 8/2M x 16) MROM
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DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
44SOP (SOP044-P-0600)
16.40 [0.646]
15.60 [0.614]
13.40 [0.528]
13.00 [0.512]
14.40 [0.567]
28.40 [1.118]
28.00 [1.102]
0.15 [0.006]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
1.275 [0.050]
2.9 [0.114]
2.5 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
44
23
221
3.25 [0.128]
2.45 [0.096]
44SOP
2.9 [0.114]
2.5 [0.098]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
0.80 [0.031]
0 - 10°
SEE
DETAIL
DETAIL
PACKAGE DIAGRAM
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
48TSOP (TSOP048-P-1218)
18.40 [0.724]
17.60 [0.693]
16.60 [0.654]
16.20 [0.638]
17.00 [0.669]
12.20 [0.480]
11.80 [0.465]
0.15 [0.006]
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047]
MAX.
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.10 [0.004]
0.30 [0.012]
0.10 [0.004]
48
25
241
0.425 [0.017]
48TSOP
0.50 [0.020]
TYP.
CMOS 32M (4M x 8/2M x 16) MROM LH5332600
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LH5332600
Device Type
X
Package
5332600N-5
Example: LH5332600N (CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP)
CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM
N 44-pin, 600-mil SOP (SOP044-P-0600)
T 48-pin, 12 mm x 18 mm
2
TSOP (Type I) (TSOP048-P-1218)
ORDERING INFORMATION
LH5332600 CMOS 32 M (4M x 8/2M x 16) MROM
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