Page 1
LH532600
FEATURES
•• 262,144 w ords × 8 b it organ izatio n
(Byte mode)
131,072 words × 16 bit orga niza tion
(Word mode)
•• Access time: 100 ns (MAX.)
•• Static operation
•• TTL compatib le I/O
•• Three-state outputs
•• Singl e +5 V po we r su ppl y
•• Powe r consu mption :
Operating : 412.5 mW (MAX.)
Standby: 550 µW (MAX.)
•• Mask-programmable control pin:
Pin 1 = OE
1
/OE1/DC
•• Packa ges:
40-pi n , 600 - mil D IP
40-pi n , 525 - mil S OP
48-pi n , 1 0 × 20 mm
2
TSOP (Type I)
DESCRIPTION
The LH532600 is a 2M-bit mask-programmable ROM
organized as 262,144 × 8 bits (Byte mode) or 131,072
× 16 bits (Word mode) that can be selected by BYTE
input pin. It is fabricated using silicon- gate CMOS process technology.
PIN CONNECTIONS
CMOS 2M (256K × 8 /128K × 16) MROM
532600-1
TOP VIEW
2
3
4
5
8
9
A
1
A
4
37
36
35
34
33
32
29
26
A
6
A
5
6
7
A
2
A
3
31
30
A
12
A
14
A
16
D15/A
-1
(LSB)
D
6
10
11
12
39
38
13
28
D
7
27
D
14
CE
GND
A
13
40-PIN DIP
40-PIN SOP
14
15
16
17
18
19
20
23
25
24
22
21
V
CC
D
10
D
3
D
2
OE
D
1
D
9
D
8
D
11
A
15
BYTE
D
13
40
1
A
7
OE1/OE1/DC
A
8
GND
D
0
A
0
A
9
A
10
A
11
D
5
D
12
D
4
Figure 1. Pin Connections for DIP and
SOP Packages
1
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532600-2
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7
A
11
A
12
39
38
D
7
D
3
10
11
12
47
46
D
15/A-1
A
9
13
36
35
A
8
48 PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE
D
10
GND
48
1
A
16
BYTE
22
27
D
0
GND
23
26
V
CC
24
25
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
NC
NC
NC
OE
1
/OE1/DC
NOTE: Reverse bend available on request.
Figure 2. Pin Connections for TS OP Packag e
LH532600 CMOS 2M MROM
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532600-3
A
3
A
2
A
12
A
11
A
10
A
9
A
8
36
37
38
39
3
6
7
A
7
A
6
A
4
MEMORY
MATRIX
(262,144 x 8)
(131,072 x 16)
SENSE AMPLIFIER
2
31
5
40
A
5
4
A
13
35
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
34
A
15
33
10
TIMING
GENERATOR
A
16
32
BYTE
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
1
OE1/OE1/
DC
DATA SELECTOR/OUTPUT BUFFER
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
20
18
16
14
24
17
15
13
19
28
22
23
25
27
29
26
29
A
-1
V
CC
21
GND
11 30
A
1
8
A
0
9
12
OE
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH532600 Block Diag ram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A–1 – A
16
Addres s i npu t 1
D
0
– D
15
Data o utp ut 1
BYTE Byte/w ord mo de swi tch 1
CE Chip e nab le inp ut
SIGNAL PIN NAME NOTE
OE Output en abl e i npu t
OE
1
/OE1/DC Output en abl e i npu t 2, 3
V
CC
Power su ppl y (+ 5 V)
GND Ground
NOTES:
1. The D15/A–1 pin becomes LSB address input (A–1) when the B YTE pin is set to be LOW in byte mode, and data output (D15) when set to
be HIGH in word mode.
2. Active levels of OE
1
/OE1/DC are mask-progr ammable. When DC is selected out of OE1/OE1/DC, it is fixed to an active level. Then it is
recommended to apply either V
IH
or VIL to the DC p in.
3. DC = Don’t care.
CMOS 2M MROM LH532600
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TRUTH TABLE
CE OE OE1/OE
1
BYTE
A
–1
(D15)
DATA OUTPUT ADDRESS INPUT
S UP P LY CU RR EN T
D
0
– D
7
D8 – D
15
LSB MSB
H X X X X High-Z High-Z – – Standby
L H X X X High-Z High-Z – – Operating
L X L/H X X High-Z High-Z – – Operating
LLH/LH–D
0
– D
7
D8 – D
15
A
0
A
16
Operating
LLH/LL LD
0
– D
7
High-Z A
–1
A
16
Operating
LLH/LLHD
8
– D
15
High-Z A
–1
A
16
Operating
NOTE:
X = H or L, High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
–0.3 to VCC + 0.3 V
Operat ing te mpe ratu re
Topr 0 to +70 °C
Storage temperature Tstg –65 to +150
°C
RECOMMENDED OPERATING CON DITIONS (TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Input ‘Lo w’ voltage V
IL
– 0.3 0.8 V
Output ‘H igh ’ vol tag e V
OH
IOH = –4 00 µA
2.4 V
Output ‘L ow’ v olt age V
OL
IOL = 2. 0 m A 0.4 V
Input leakage current | I
Ll
|VIN = 0 V to V
CC
10
µA
Output le aka ge cur ren t | I
LO
|V
OUT
= 0 V to V
CC
10
µA
1
Operat ing cu rre nt
I
CC1
tRC = 100 ns 75 mA 2
I
CC2
tRC = 1 µs65mA2
I
CC3
tRC = 100 ns
70 mA 3
I
CC4
tRC = 1 µs
60 mA 3
Standb y c urr ent
I
SB1
CE = V
IH
3 mA
I
SB2
CE = VCC – 0.2 V 100
µA
Input cap acitan ce C
IN f = 1 M Hz
T
A
= 25°C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE/OE/OE1 = VIH, O E1 = V
IL
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
LH532600 CMOS 2M MROM
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AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read c yc le t ime t
RC
100 ns
Addres s a cc ess ti me t
AA
100 ns
Chip e nab le acc es s ti me t
ACE
100 ns
Output en abl e d ela y t ime t
OE
55 ns
Output ho ld time t
OH
5ns
CE to out put in Hig h-Z t
CHZ
55 ns 1
OE to out put in Hig h-Z t
OHZ
NOTE:
1. Th is is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PA RAMETER RATING
Input vol tage ampl itude
0.4 to 2.6 V
Input rise/fall time 10 ns
Input/ out put ref ere nce le vel
1.5 V
Output load condition 1 TTL + 100 pF
CAUTION
To stabili ze the pow er suppl y, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
CMOS 2M MROM LH532600
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A
-1
- A
16
t
OHZ
t
CHZ
532600-4
t
RC
CE
OE/OE1/
OE
1
t
OH
DATA VALID
NOTE: The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or tOE, have concluded.
t
OE
t
ACE
t
AA
D0 - D
7
(NOTE)
(NOTE)
(NOTE)
Figure 4. Byte Mode (BYTE = VIL)
A0 - A
16
t
OHZ
t
CHZ
532600-5
t
RC
CE
OE/OE1/
OE
1
t
OH
DATA VALID
t
OE
t
ACE
t
AA
D0 - D
15
(NOTE)
(NOTE)
(NOTE)
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, or tOE, have concluded.
Figure 5. Word Mode (BYTE = VIH)
LH532600 CMOS 2M MROM
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PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.40 [0.213]
4.80 [0.189]
3.55 [0.140]
2.95 [0.116]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
52.30 [2.059]
51.70 [2.035]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.55 [0.179]
3.95 [0.156]
15.24 [0.600]
TYP.
40DIP (DIP040-P-0600)
120
2140
40DIP
40-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
40SOP (SOP040-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
26.50 [1.043]
26.10 [1.028]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
40
21
201
1.40 [0.055]
1.40 [0.055]
40SOP
40-pin, 525-mil SOP
CMOS 2M MROM LH532600
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ORDERING INFORMATION
D 40-pin, 600-mil DIP (DIP040-P-0600)
N 40-pin, 525-mil SOP (SOP040-P-0525)
T 48-pin, 10 x 20 mm
2
TSOP (Type I) (TSOP048-P-1020)
TR 48-pin, 10 x 20 mm
2
TSOP (Type I) Reverse bend (TSOP048-P-1020)
LH532600
Device Type
X
Package
532600-6
Example: LH532600D (CMOS 2M (256K x 8 or 128K x 16 ) Mask-Programmable ROM, 40-pin, 600-mil DIP)
CMOS 2M (256K x 8 or 128K x 16) Mask-Programmable ROM
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
48TSOP (TSOP048-P-1218)
18.40 [0.724]
17.60 [0.693]
16.60 [0.654]
16.20 [0.638]
17.00 [0.669]
12.20 [0.480]
11.80 [0.465]
0.15 [0.006]
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047]
MAX.
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.10 [0.004]
0.30 [0.012]
0.10 [0.004]
48
25
241
0.425 [0.017]
48TSOP
0.50 [0.020]
TYP.
48-pin, 10 × 20 mm2 TSOP (Type I)
LH532600 CMOS 2M MROM
8
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