Datasheet LH532100BU-1, LH532100BSR-1, LH532100BS-1, LH532100BN-1, LH532100BD-1 Datasheet (Sharp)
...Page 1
LH532100B-1
CMOS 2 M (256K × 8) MROM
FEATURES
•• 262,144 w ords × 8 b it organ izatio n
•• Access time: 120 ns (MAX.)
•• Static operation
•• TTL compatib le I/O
•• Three-state outputs
•• Singl e +5 V po we r su ppl y
•• Powe r consu mption :
Operating : 27 5 mW (MAX.)
Standby: 550 µW (MAX.)
•• Mask-programmable control pin:
Pin 1 = OE
1
/OE1/DC
Pin 24 = OE/
OE
•• Packages:
32-pi n , 600 - mil D IP
32-pi n , 525 - mil S OP
32-pi n , 450 -mi l Q FJ (PLC C)
32-pi n , 8 × 20 mm
2
TSOP (Typ e I)
32-pi n , 400-mi l TSOP (Type II )
DESCRIPTION
The LH532100B-1 is a CMOS 2M-bit mask-programmable ROM organized a s 262,144 × 8 bits. It is fabricated using silicon-gate process technology.
PIN CONNECTIONS
532100B1-1
TOP VIEW
1
2
3
4
5
6
9
10
A
2
A
5
V
CC
28
27
26
25
24
23
20
17
A
7
A
6
7
8
A
3
A
4
22
21
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
11
12
13
32
31
30
29
A
14
A
1
14
15
16
19
D
5
18
D
4
D
1
D
2
A
0
D
0
A
9
A
16
OE/OE
32-PIN DIP
32-PIN SOP
OE1/OE1/DC
DC
A
17
Figure 1. Pin Connections for DIP and
SOP Packages
21
22
23
24
25
26
27
D
7
CE
A
10
A
9
A
8
13
12
11
10
9
8
D
0
A
0
A
1
A
2
A
5
5
30 31 32 4321
28
29
A
13
A
14
6
A
7
7
DC
17181920 16 15 14
D6D5D4D3GND
D2D
1
32-PIN QFJ TOP VIEW
532100B1-7
OE/OE
A
11
A
3
V
CC
OE
1
/OE
1
/DC
A
16A15A12
A
17
A
4
A
6
Figure 2. Pin Connections fo r QFJ
(PLCC) Package
1
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532100B1-2
TOP VIEW
2
3
4
5
8
9
V
CC
A
14
29
28
27
26
25
24
21
18
A
8
A
13
6
7
23
22
D
7
A
2
10
11
12
31
30
A
16
13
20
19
OE
1
/OE1/DC
32-PIN TSOP (Type I)
14
15
16
17
A
3
32
1
A
9
A
10
D
6
D
4
D
3
GND
D
2
D
5
D
0
A
0
A
1
A
11
A
15
A
12
A
7
A
6
A
5
A
17
DC
OE/OE
CE
A
4
D
1
Figure 3. Pin Connections fo r TSOP
(Type I) Package
1
2
3
4
7
8
A
7
30
29
28
27
26
25
22
19
A
15
A
12
5
6
A
6
24
23
A
16
DC
A
14
A
8
A
10
CE
D
5
9
10
11
32
31
12
21
D
7
20
D
6
A
0
D
0
A
2
A
1
A
13
13
14
A
9
532100B1-3
TOP VIEW32-PIN TSOP (Type II)
NOTE: Reverse bend available on request.
D
1
D215
16
GND
17
D
3
18
D
4
OE/OE
A
11
OE1/OE1/DC
A
5
A
4
A
3
A
17
V
CC
Figure 4. P in Connections for TSOP
(Type II) Package
LH532100B-1 CMOS 2M MROM
2
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532100B1-4
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
32
4
25
23
26
6
9
10
11
A
7
A
6
V
CC
A
4
18
19
20
13
21
D
0
MEMORY
MATRIX
(262,144 x 8)
SENSE AMPLIFIER
OUTPUT BUFFER
16
5
GND
D
1D2D3D4D5D6D7
17
14
15
8
27
A
5
7
A
13
28
ADDRESS BUFFER
CE
A
0
12
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
29
A
15
3
22
TIMING
GENERATOR
A
16
2
1
OE1/OE1/DC
A
17
30
24
OE/OE
NOTE: Pin numbers apply to the 32-pin DIP, SOP, QFJ, or TSOP (Type II).
Figure 5. LH532100B-1 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A0 – A
17
Addres s i npu t
D
0
– D
7
Data o utp ut
CE Chip e nab le inp ut
OE/
OE Output en abl e i npu t 1
SIGNAL PIN NAME NOTE
OE1/OE1/DC Output ena ble input 1, 2
V
CC
Power sup ply (+5 V)
GND Ground
NOTES:
1. Active levels of OE/OE and OE1/OE1/DC are mask-programmable. Selecting DC all ows the outputs to be active for both high and low levels
applied t o this p in. It is recommended to apply either a HIGH or a LOW to the D C p in.
2. DC = Don’t care.
CMOS 2M MROM LH532100B-1
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TRUTH TABLE
CE OE/OE OE1/OE
1
DATA OUTP UT SUPP LY C URRENT
H X X High-Z Standby
L L/H X High-Z Operating
L X L/H High-Z Operating
L H/L H/L Output Operating
NOTE:
X = H or L, High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
–0.3 to VCC + 0.3 V
Operat ing te mpe ratu re
Topr 0 to +70 °C
Storage temperature Tstg –65 to +150
°C
RECOMMENDED OPERATING CON DITIONS (TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. U NIT NOTE
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Input ‘Lo w’ voltage V
IL
–0.3 0.8 V
Output ‘H igh ’ vol tag e V
OH
IOH = –4 00 µA
2.4 V
Output ‘L ow’ v olt age V
OL
IOL = 2. 0 m A 0.4 V
Input leakage current | I
Ll
|VIN = 0 V to V
CC
10
µA
Output le aka ge cur ren t | I
LO
|V
OUT
= 0 V to V
CC
10
µA
1
Operat ing cu rre nt
I
CC1
tRC = 120 ns 50 mA 2
I
CC2
tRC = 1 µs45mA2
I
CC3
tRC = 120 ns 45 mA 3
I
CC4
tRC = 1 µs40mA3
Standb y c urr ent
I
SB1
CE = V
IH
3 mA
I
SB2
CE = VCC – 0.2 V 100
µA
Input cap acitan ce C
IN f = 1 M Hz
T
A
= 25°C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE/OE/OE1 = VIH, OE/OE1 = V
IL
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
LH532100B -1 CMOS 2M MROM
4
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AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read c yc le t ime t
RC
120 ns
Addres s a cc ess ti me t
AA
120 ns
Chip e nab le acc es s ti me t
ACE
120 ns
Output en abl e d ela y t ime t
OE
50 ns
Output ho ld time t
OH
10 ns
CE to out put in Hig h-Z t
CHZ
50 ns 1
OE to out put in Hig h-Z t
OHZ
NOTE:
1. Th is is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PA RAMETER RATING
Input vol tage ampl itude
0.6 V to 2.4 V
Input rise/fall time 10 ns
Input ref erence level
1.5 V
Output reference level 0.8 V and 2.2 V
Output load condition 1 TTL + 100 pF
CAUTION
To stabili ze the pow er suppl y, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
A0 - A
17
t
OHZ
t
CHZ
532100B1-5
t
RC
CE
OE/OE
1
OE/OE
1
t
OH
DATA VALID
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, or tOE, have concluded.
t
OE
t
ACE
t
AA
D0 - D
7
(NOTE)
(NOTE)
(NOTE)
Figure 6. Timing Diagram
CMOS 2M MROM LH532100B-1
5
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PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
41.30 [1.626]
40.70 [1.602]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
32DIP (DIP032-P-0600)
116
1732
32DIP
32-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
17
161
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
LH532100B -1 CMOS 2M MROM
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DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32TSOP (Type I) (TSOP032-P-0820)
20.30 [0.799]
19.70 [0.776]
18.60 [0.732]
18.20 [0.717]
19.00 [0.748]
8.20 [0.323]
7.80 [0.307]
0.15 [0.006]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047] MAX.
0.20 [0.008]
0.10 [0.004]
0.30 [0.012]
0.10 [0.004]
0.50 [0.020]
TYP.
32
1
32TSOP
16
1.10 [0.043]
0.90 [0.035]
17
0.425 [0.017]
32-pin, 8 × 20 mm2 TSOP (Type I)
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32TSOP (Type II) (TSOP032-P-0400)
12.30 [0.484]
11.30 [0.445]
10.40 [0.409]
10.00 [0.394]
11.00 [0.433]
10.60 [0.417]
21.20 [0.835]
20.80 [0.819]
0.15 [0.006]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047] MAX.
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
1
32TSOP400
16
1.10 [0.043]
0.90 [0.035]
17
0.4375 [0.017]
32-pin, 400-mil TSOP (Type II)
CMOS 2M MROM LH532100B-1
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ORDERING INFORMATION
LH532100B
Device TypeXPackage
532100B1-6
Example: LH532100BD-1 (CMOS 2M (256K x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP)
CMOS 2M (256K x 16) Mask-Programmable ROM
D 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
U 32-pin, 450-mil QFJ (PLCC) (QFJ032-P-R450)
T 32-pin, 8 x 20 mm
2
TSOP (Type I) (TSOP032-P-0820)
S 32-pin, 400-mil TSOP (Type II) (TSOP032-P-0400)
SR 32-pin, 400-mil TSOP (Type II) Reverse bend (TSOP032-P-0400)
-1
120 ns Version
11.40 [0.449]
0.25 [0.010]
1.20 [0.047]
1.20 [0.047]
2.30 [0.091]
1.90 [0.075]
3.50 [0.138]
3.10 [0.122]
14.00 [0.551]
20
2129
135
4
1
30
14
10.90 [0.429]
10.10 [0.398]
12.50 [0.492]
12.30 [0.484]
15.10 [0.594]
14.90 [0.587]
1.27 [0.050]
TYP.
0.56 [0.022]
0.36 [0.014]
13.50 [0.531]
12.70 [0.500]
32QFJ450
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM (INCHES)
32QFJ (QFJ032-P-R450)
32-pin, 450-mil QFJ (PLC C)
LH532100B -1 CMOS 2M MROM
8
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