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LH532048N
Datasheet (Sharp)
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Datasheet LH532048U, LH532048N Datasheet (Sharp)

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Page 1
LH532048
CMOS 2 M (12 8K × 16) MROM
FEATURES
•• 131,072 w ords × 16 bit orga niza ti on
•• Access time: 100 ns (MAX.)
•• Static operation
•• TTL compatib le I/O
•• Three-state outputs
•• Powe r consu mption :
Operating : 412.5 mW (MAX.) Standby: 550 µW (MAX.)
•• Packages: 40-pi n , 600 - mil D IP 40-pi n , 525 - mil S OP 44-pi n , 650 -mi l Q FJ (PLC C)
DESCRIPTION
The LH532048 is a 2M-bit mask-programmable ROM organized as 131,072 × 16 bits. It is fabricated using silicon-gate CMOS process technology.
PIN CONNECTIONS
532048-1
TOP VIEW
2 3 4 5
8 9
D
10
D
13
37 36
35 34
33 32
29
26
D
15
D
14
6 7
D
11
D
12
31
30
A
14
A
12
A
10
A
8
A
5
10
11
12
39 38
13
28
A
7
27
A
6
GND
A
13
40-PIN DIP 40-PIN SOP
14 15 16 17
18 19 20
23
25 24
22
21
A
0
D
1
D
0
D
2
D
4
D
3
D
5
OE
A
11
A
4
40
1
CE
NC
V
CC
GND
D
6
D
9
NC A
16
A
15
A
3
A
2
A
1
D
7
D
8
A
9
Figure 1. Pin Connections fo r DIP and
SOP Packages
532048-2
TOP VIEW
8 9
10
11
14 15
D
7
D
8
36 35
34 33
32
31
D
10
D
9
12 13
NC
GND
30 29
A
10
A
9
NC
A
7
16 17
38 37
A
11
D
6
D
5
GND
44-PIN PLCC
A
12
A
8
A
6
39
7
D
11
D
12
A
13
18 19 20 21 22 23 24 25 26 27 28
D
3
OE
NC
6 5 4 3 2 1 44 43 42 41 40
D
13
CENCNC
D
4
D2D1D
0
A0A1A2A3A
4
A
5
D14D
15
VCCNC
A16A15A
14
Figure 2. Pin Connections fo r QFJ
(PLCC) Package
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532048-3
A
3
A
2
A
12
A
11
A
10
A
9
A
8
34 33 32 31
27
24 23
A
7
A
6
A
4
MEMORY
MATRIX
(131,072 x 16)
SENSE AMPLIFIER
28
25
29
A
5
26
A
13
35
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
36
A
15
37
2
TIMING
GENERATOR
A
16
38
OUTPUT BUFFER
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
7 8
9
10
14
17 18 19
16
12
15
6
5
4
3
13
V
CC
40
GND
11 30
A
1
22
A
0
21
20
OE
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH532048 Block Diagram
PIN DESCRIPTION
SIGNAL PI N N AM E
A0 – A
16
Addres s i npu t
D
0
– D
15
Data o utp ut CE Chip e nab le inp ut OE Output en abl e i npu t
SIGNAL PIN NAME
V
CC
Power sup ply (+5 V)
GND Ground
NC No con nec tio n
LH532048 CMOS 2M MROM
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532048-4
A
3
A
2
A
12
A
11
A
10
A
9
A
8
38 37 36 35
30
27 26
A
7
A
6
A
4
MEMORY
MATRIX
(131,072 x 16)
SENSE AMPLIFIER
31
28
32
A
5
29
A
13
39
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
40
A
15
41
3
TIMING
GENERATOR
A
16
42
OUTPUT BUFFER
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
8
9 10 11
16
19 20 21
18
14
17
7
6
5
4
15
V
CC
44
GND
12 34
A
1
25
A
0
24
22
OE
NOTE: Pin numbers apply to the 44-pin QFJ.
Figure 4. LH532048 Block Diagram
CMOS 2M MROM LH532048
3
Page 4
TRUTH TABLE
CE OE DATA OUTPUT SUPPLY CURRENT
H X High-Z Standby L H High-Z Operating LL D
0
– D
15
Operating
NOTE:
X = H or L, High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age
V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
–0.3 to VCC + 0.3 V
Operat ing te mpe ratu re Topr 0 to +7 0
°C
Storag e t emp era ture
Tstg –65 to +150 °C
RECOMMENDED OPERATING CON DITIONS (TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL CONDI TIONS MIN. M AX. UNIT NOTE
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Input ‘Lo w’ voltage V
IL
– 0.3 0.8 V
Output ‘H igh ’ vol tag e
V
OH
IOH = –400 µA 2.4 V
Output ‘L ow’ v olt age V
OL
IOL = 2. 0 m A 0.4 V
Input lea kag e c urr ent
| I
Ll
|
V
IN
= 0 V to V
CC
10 µA
Output le aka ge cur ren t | I
LO
|V
OUT
= 0 V to V
CC
10
µA
1
Operat ing cu rre nt
I
CC1
tRC = 100 ns
75 mA 2
I
CC2
tRC = 1 µs
65 mA 2
I
CC3
tRC = 100 ns 70 mA 3
I
CC4
tRC = 1 µs
60 mA 3
Standb y c urr ent
I
SB1
CE = V
IH
3 mA
I
SB2
CE = VCC – 0.2 V 100
µA
Input cap acitan ce C
IN f = 1 M Hz
T
A
= 25°C
10 pF
Output ca pac ita nce
C
OUT
10 pF
NOTES:
1. CE/OE = V
IH
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
LH532048 CMOS 2M MROM
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AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read c yc le t ime t
RC
100 ns
Addres s a cc ess ti me t
AA
100 ns
Chip e nab le acc es s ti me t
ACE
100 ns
Output en abl e d ela y t ime t
OE
55 ns
Output ho ld time t
OH
0ns
CE to out put in Hig h-Z t
CHZ
50
ns
1
OE to out put in Hig h-Z t
OHZ
ns
NOTE:
1. Th is is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PA RAMETER RATING
Input vol tage ampl itude
0.4 V to 2.6 V Input rise/fall time 10 ns Input/ out put ref ere nce le vel
1.5 V
Output load condition 1 TTL + 100 pF
CAUTION
To stabili ze the pow er suppl y, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
A0 - A
16
t
OHZ
t
CHZ
532048-5
t
RC
CE
OE
t
OH
DATA VALID
NOTE: The output data becomes valid when the last intervals, t
AA
, t
ACE
, or tOE, have concluded.
t
OE
t
ACE
t
AA
D0 - D
15
(NOTE)
(NOTE)
(NOTE)
Figure 5. Timing Diagram
CMOS 2M MROM LH532048
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PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.40 [0.213]
4.80 [0.189]
3.55 [0.140]
2.95 [0.116]
2.54 [0.100] TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
52.30 [2.059]
51.70 [2.035]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.55 [0.179]
3.95 [0.156]
15.24 [0.600] TYP.
40DIP (DIP040-P-0600)
120
2140
40DIP
40-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
40SOP (SOP040-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
26.50 [1.043]
26.10 [1.028]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050] TYP.
40
21
201
1.40 [0.055]
1.40 [0.055]
40SOP
40-pin, 525-mil SOP
LH532048 CMOS 2M MROM
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ORDERING INFORMATION
D 40-pin, 600-mil DIP (DIP040-P-0600) N 40-pin, 525-mil SOP (SOP040-P-0525) U 44-pin, 650-mil QFJ (PLCC) (QFJ044-P-S650)
LH532048
Device Type
X
Package
532048-6
Example: LH532048D (CMOS 2M (128K x 16) Mask-Programmable ROM, 40-pin, 600-mil DIP)
CMOS 2M (128K x 16) Mask-Programmable ROM
4015
15
10
20 25
16.60 [0.654]
17.60 [0.693]
17.40 [0.685]
16.60 [0.654]
17.60 [0.693]
17.40 [0.685]
35
30
16.00 [0.630]
15.20 [0.598]
0.56 [0.022]
0.36 [0.014]
4.60 [0.181]
4.20 [0.165]
1.80 [0.071]
2.35 [0.093]
0.85 [0.033]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
44QFJ (QFJ044-P-0650)
44QFJ-2
0.25 [0.010]
C1.1
1.27 [0.050] TYP.
44-pin, 650-mil QFJ (PLC C)
CMOS 2M MROM LH532048
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