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LH532000B
FEATURES
•• 262,144 words × 8 bi t organ izatio n
(Byte mode)
131,072 w ords × 16 bit orga niza tio n
(Word mode)
••
BYTE input pin selects bit configu ration
•• Access times: 120/150 ns (MAX.)
•• Low-pow er consumptio n:
Operating : 27 5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Programmabl e OE /
OE and OE1/OE1/DC
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Packa ges:
40-pi n , 600 -mil DIP
40-pi n , 525 -mil S OP
48-pi n , 1 2 × 18 mm
2
TSOP (Type I)
••×16 word-wide pinout
DESCRIPTION
The LH532000B is a 2M-bit mask-programmable
ROM with two programmable memory organizations,
byte and word m odes. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
CMOS 2M (256K × 8/1 28K × 16) MROM
532000B-1
TOP VIEW
1
2
3
4
7
8
A
2
A
5
48
37
36
35
34
33
30
27
A
7
A
6
5
6
A
3
A
4
32
31
OE
1
/OE1/DC
A
10
A
11
A
13
A
15
BYTE
GND
D
14
9
10
11
40
39
A
9
A
1
12
29
D15/A
-1
(LSB)
28
D
7
OE/OE
A
0
CE
A
12
40-PIN DIP
40-PIN SOP
13
14
15
16
17
18
19
20
24
21
26
25
23
22
D
13
D
5
D
12
D
4
D
2
D
10
D
9
GND
D
8
D
1
D
0
D
3
D
11
V
CC
A
8
A
14
A
16
D
6
Figure 1. Pin Connections for DIP and
SOP Packages
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532000B-5
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7
A
11
A
12
39
38
D
7
D
3
10
11
12
47
46
D
15/A-1
A
9
13
36
35
A
8
48-PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE/OE
D
10
GND
48
1
A
16
BYTE
22
27
D
0
GND
23
26
V
CC
24
25
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
NC
NC
NC
OE
1
/OE1/DC
NOTE: Reverse bend available on request.
Figure 2. Pin Connections for TSOP Package
LH532000B CMOS 2M MROM
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NOTES:
1. D15/A–1 pin becomes LSB address input (A–1) when the bit configuration is set in byte mode,
and data output (D15) when in word mode. BYTE input pin se lects bit configur at ion.
2. The active levels of OE/
OE and OE1/OE1/DC are mask-program mable.
Select ing DC a llows the outputs to be act ive f or both high and low levels applied to this pin.
It is recommended to apply either a HIGH or a LOW to t he DC pin.
532000B-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
29
A
7
A
6
V
CC
A
4
MEMORY
MATRIX
(262,144 x 8)
(131,072 x 16)
SENSE AMPLIFIER
GND
A
5
A
13
ADDRESS BUFFER
A
0
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
A
14
A
15
TIMING
GENERATOR
A
16
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
A
-1
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
DATA SELECTOR/OUTPUT BUFFER
21 11
30
OE
BUFFER
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
31
OE1/OE1/DC
OE/OE
CE
BYTE
10
12
1
3
6
7
8
5
4
9
36
37
38
39
2
40
35
34
33
32
20
18
16
14
24
17
15
13
26
19
28
22
23
25
27
29
Figure 3. LH532000B Block Diagram
PIN DESCRIPTION
SIGNA L PIN N AME NOT E
A
–1
Addre ss input (BY TE mode) 1
A
0
– A
16
Addre ss inp ut
D
0
– D
15
Data out put 1
CE Chip ena ble in put
OE/
OE Outpu t e nab le inp ut 2
SIGNAL PIN NAME NO TE
OE1/OE1/DC
Outpu t en abl e i npu t o r
Don’t ca re
2
BYTE Byte/ wor d mo de swi tch
V
CC
Power su ppl y (+ 5 V)
GND Ground
CMOS 2M MROM LH532000B
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TRUTH TABLE
CE OE/OE OE1/OE1BYTE
A
–1
(D15)
DATA OUTPUT ADDRESS INPUT
SUPPLY CURRENT
D
0
– D
7
D8 – D
15
LSB MSB
H X X X X High-Z High-Z – – Standby (ISB)
L L/H X X X High-Z High-Z – – Operating (I
CC
)
L X L/H X X High-Z H igh-Z – – Operating (I
CC
)
L H/L H/L H
Input
inhibit
D
0
– D
7
D8 – D
15
A
0
A
16
Operating (ICC)
L H/L H/L L L D
0
– D
7
High-Z A
–1
A
16
Operating (ICC)
L H/L H/L L H D
8
– D
15
High-Z A
–1
A
16
Operating (ICC)
NOTE:
1. X = H or L, High-Z = High-impedance.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
–0.3 to VCC + 0.3 V
Operat ing te mpe ratu re
Topr 0 to +70 °C
Storag e t emp era ture Tstg –65 to +150
°C
RECOMMENDED OPERATING CON DITIONS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Lo w’ voltage V
IL
– 0.3 0.8 V
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Output ‘L ow’ v olt age V
OL
IOL = 2 .0 mA 0.4 V
Output ‘H igh ’ vol tag e
V
OH
IOH = –400 µA 2.4 V
Input lea kag e c urr ent
| I
LI
|
V
IN
= 0 V to V
CC
10 µA
Output le aka ge cur ren t
| I
LO
|
V
OUT
= 0 V to V
CC
10 µA1
Operat ing cu rre nt
I
CC1
tRC = tRC (MIN .) 50
mA 2
I
CC2
tRC = 1 µs45
I
CC3
tRC = tRC (MIN .) 45
mA 3
I
CC4
tRC = 1 µs40
Standb y c urr ent
I
SB1
CE = V
IH
3mA
I
SB2
CE = VCC - 0.2 V 100
µA
Input cap acitan ce C
IN
f = 1 MHz
T
A
= 25° C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. OE/OE1= VIL, CE/OE/OE1= V
IH
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC - 0.2 V) or 0. 2 V, CE = 0.2 V, outputs o pen
LH532000B CMOS 2M MROM
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AC CHARACTERISTICS (V
CC
= 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL
120 ns 150 ns
UNIT NOTE
MIN. MAX. MIN. MAX.
Read c yc le t ime t
RC
120 150 ns
Addres s a cc ess ti me t
AA
120 150 ns
Chip e nab le acc es s ti me t
AC E
120 150 ns
Output en abl e d ela y t ime t
OE
55 70 ns
Output ho ld time t
OH
510ns
CE to out put in Hig h-Z t
CHZ
55 70 ns
1
OE to out put in Hig h-Z t
OHZ
55 70 ns
NOTE:
1. Th is is the time required for th e output to become high-impedance.
AC TEST CONDITIONS
PA RAMETER RATING
Input voltage amplitude 0.6 V to 2.4 V
Input rise/fall time 10 ns
Input ref erence level 1.5 V
Output reference level 0.8 V and 2.2 V
Output load condit ion 1TTL +100 pF
CAUTION
To stabili ze the pow er suppl y, it is recommended that a high-frequency bypass capacitor b e connected between
the VCC pin and the GND pin.
t
OE
t
AA
(D
0
- D15)
t
OHZ
t
CHZ
532000B-3
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE 1)
D
0
- D
7
OE/OE
1
OE/OE
1
(A0 - A16)
A-
1
- A
16
1. Data becomes valid after tAA, t
ACE
, and tOE from address
input, chip enable or output enable, respectively have been met.
2. Applied to byte mode. Signals in parentheses apply to word mode.
NOTES:
(NOTE 1)
(NOTE 2)
(NOTE 2)
Figure 4. Timi ng Diagram
CMOS 2M MROM LH532000B
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PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.40 [0.213]
4.80 [0.189]
3.55 [0.140]
2.95 [0.116]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
52.30 [2.059]
51.70 [2.035]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.55 [0.179]
3.95 [0.156]
15.24 [0.600]
TYP.
40DIP (DIP040-P-0600)
120
2140
40DIP
40-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
40SOP (SOP040-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
26.50 [1.043]
26.10 [1.028]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
40
21
201
1.40 [0.055]
1.40 [0.055]
40SOP
40-pin, 525-mil SOP
LH532000B CMOS 2M MROM
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D 40-pin, 600-mil DIP (DIP040-P-0600)
N 40-pin, 525-mil SOP (SOP040-P-0525)
T 48-pin, 12 x 18 mm
2
TSOP (Type I) (TSOP048-P-1218)
TR 48-pin, 12 x 18 mm
2
TSOP (Type I) Reverse bend (TSOP048-P-1218)
LH532000B
Device Type
X
Package
532000B-4
Example: LH532000BD (CMOS 2M (256K x 8 or 128K x 16) Mask Programmable ROM, 40-pin, 600-mil DIP)
CMOS 2M (256K x 8 or 128K x 16) Mask Programmable ROM
ORDERING INFORMATION
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
48TSOP (TSOP048-P-1218)
18.40 [0.724]
17.60 [0.693]
16.60 [0.654]
16.20 [0.638]
17.00 [0.669]
12.20 [0.480]
11.80 [0.465]
0.15 [0.006]
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047]
MAX.
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.10 [0.004]
0.30 [0.012]
0.10 [0.004]
48
25
241
0.425 [0.017]
48TSOP
0.50 [0.020]
TYP.
48-pin, 12 × 18 mm2 TSOP (Type I)
CMOS 2M MROM LH532000B
7
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