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LH531V00
CM OS 1M (12 8 K × 8) MROM
FEATURES
•• 131,072 words × 8 b it organ izatio n
•• Access time: 100 ns (MAX.)
•• Power consu mption :
Operating : 27 5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Mask-programmable OE
1
/OE1/DC
•• Fully-static operatio n
•• TTL-compatib le I /O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Packa ges:
32-pi n , 600 -mil DIP
32-pi n , 525 -mil S OP
32-pi n , 8 × 20 mm
2
TSOP (Type I)
DESCRIPTION
The LH531V00 is a 1M-bit mask-progr ammable ROM
organized as 131,072 × 8 bits. It is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
531V00-1
TOP VIEW
1
2
3
4
5
6
9
10
A
2
A
5
V
CC
28
27
26
25
24
23
20
17
A
7
A
6
7
8
A
3
A
4
22
21
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
11
12
13
32
31
30
29
OE
1
/OE1/DC
A
14
A
1
14
15
16
19
D
5
18
D
4
D
1
D
2
A
0
D
0
A
9
A
16
OE
NC
NC
32-PIN DIP
32-PIN SOP
Figure 1. Pin Connections for DIP an d
SOP Packages
531V00-2
TOP VIEW
2
3
4
5
8
9
V
CC
A
14
29
28
27
26
25
24
21
18
A
8
A
13
6
7
NC
NC
23
22
D
7
A
2
10
11
12
31
30
CE
A
16
13
20
19
OE
1
/OE1/DC
32-PIN TSOP (Type I)
14
15
16
17
A
3
OE
32
1
A
9
D
1
A
10
D
6
D
4
D
3
GND
D
2
D
5
D
0
A
0
A
1
A
11
A
15
A
12
A
7
A
6
A
5
A
4
Figure 2. Pin Connections for TSOP Package
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NOTE:
1. Active level of OE1/OE1/DC is mask-programmable. When DC is selected out of OE1/OE1/DC, it is fixed to an active level.
Then it is recommended to apply either HIGH or LOW t o the D C p in.
531V00-3
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
32
4
25
23
26
6
9
10
11
A
7
A
6
V
CC
A
4
18
19
20
13
21
D
0
MEMORY
MATRIX
(131,072 x 8)
SENSE AMPLIFIER
OUTPUT BUFFER
16
5
GND
D
1D2D3D4D5D6D7
1
17
14
15
8
27
A
5
7
A
13
28
ADDRESS BUFFER
CE
A
0
12
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
29
A
15
3
22
TIMING
GENERATOR
A
16
2
OE1/OE1/DC
24
OE
NOTE: Pin numbers apply to the 32-pin DIP or SOP.
Figure 3. LH531V00 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A0 – A
16
Add ress in put
D
0
– D
7
Data ou tpu t
CE Chip En abl e i npu t
OE Outp ut Ena ble in put
SIGNAL PIN NAME NOTE
OE1/OE1/DC Outpu t E nab le inp ut 1
V
CC
Power s upp ly (+5 V )
GND Groun d
LH531V00 CMOS 1M MROM
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TRUTH TABLE
CE OE OE1/OE
1
D0 – D
7
SUPPLY CURRENT NOTE
H X X High-Z Standby (ISB)1
L H X High-Z Operating (I
CC
)1
L X L/H High-Z Operating (I
CC
)1
L L H/L D
0
– D
7
Operating (ICC)
NOTE:
1. X = H or L
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age
V
CC
–0.3 to +7.0 V
Input vol tage
V
IN
–0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
–0.3 to VCC + 0.3 V
Operating temperature Topr 0 to +70
°C
Storag e t emp era ture Tstg – 65 to +150
°C
RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70 °C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Lo w’ voltage V
IL
–0.3 0.8 V
Input ‘Hi gh’ voltage
V
IH
2.2 VCC + 0.3 V
Output ‘L ow’ v olt age V
OL
IOL = 2 .0 mA 0.4 V
Output ‘H igh ’ vol tag e V
OH
IOH = –400 µA
2.4 V
Input leakage current | I
LI
|VIN = 0 V to V
CC
10
µA
Output le aka ge cur ren t | I
LO
|V
OUT
= 0 V to V
CC
10
µA
1
Operat ing cu rre nt
I
CC1
tRC = 10 0 n s
50 mA
2
I
CC2
tRC = 1 µs
45 mA
I
CC3
tRC = 10 0 n s 45 mA
3
I
CC4
tRC = 1 µs
40 mA
Standb y c urr ent
I
SB1
CE = V
IH
3mA
I
SB2
CE = VCC – 0.2 V
100 µ A
Input cap acitan ce C
IN f = 1 MHz
T
A
= 25° C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE/OE = V
IH
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
CMOS 1M MROM LH531V00
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AC CHARACTERISTICS (V
CC
= 5 V ±10%, TA = 0°C to +70 °C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read c yc le t ime t
RC
100 ns
Addres s a cc ess ti me t
AA
100 ns
Chip e nab le acc es s ti me t
ACE
100 ns
Output en abl e d ela y t ime t
OE
50 ns
Output ho ld time t
OH
0ns
CE to out put in Hig h-Z t
CHZ
50 ns
1
OE to out put in Hig h-Z t
OHZ
50 ns
NOTE:
1. Th is is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude 0.6 V to 2.4 V
Input rise/fall time 10 ns
Input/ out put ref ere nce le vel 1.5 V
Output load condition 1TTL + 100 pF
CAUTION
To stabili ze the pow er suppl y, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
t
AA
A0 - A
16
t
OHZ
t
CHZ
D0 - D
7
531V00-4
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE)
(NOTE)
t
OE
(NOTE)
NOTE: The data becomes valid after the intervals, t
AA
, t
ACE
, or tOE, from address input, chip enable,
and output enable, respectively have been met.
OE/OE1/OE
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Figure 4. Timin g Diagram
LH531V00 CMOS 1M MROM
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PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
41.30 [1.626]
40.70 [1.602]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
32DIP (DIP032-P-0600)
116
1732
32DIP
32-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
17
161
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
CMOS 1M MROM LH531V00
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D 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
T 32-pin, 8 x 20 mm
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TSOP (Type I) (TSOP032-P-0820)
LH531V00
Device Type
X
Package
531V00-5
Example: LH531V00D (CMOS 1M (128K x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP)
CMOS 1M (128K x 8) Mask-Programmable ROM
ORDERING INFORMATION
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32TSOP (Type I) (TSOP032-P-0820)
20.30 [0.799]
19.70 [0.776]
18.60 [0.732]
18.20 [0.717]
19.00 [0.748]
8.20 [0.323]
7.80 [0.307]
0.15 [0.006]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047] MAX.
0.20 [0.008]
0.10 [0.004]
0.30 [0.012]
0.10 [0.004]
0.50 [0.020]
TYP.
32
1
32TSOP
16
1.10 [0.043]
0.90 [0.035]
17
0.425 [0.017]
32-pin, 8 × 20 mm2 TSOP (Type I)
LH531V00 CMOS 1M MROM
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