Page 1
LH531024
CMOS 1M (64K × 16 ) MROM
FEATURES
•• 65,536 words × 16 b it organ izatio n
•• Access time: 100 ns (MAX.)
•• Power consu mption :
Operating : 412.5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• JEDEC stan dard EPROM pinout (DIP)
•• Packages:
40-pi n , 600 -mil DIP
40-pi n , 525 -mil S OP
44-pi n , 650 -mil Q FJ (PLC C)
DESCRIPTION
The LH531024 is a mask-programmable ROM
organized as 65,536 × 16 bits. It is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
531024-1
TOP VIEW
1
2
3
4
7
8
D
11
D
14
38
37
36
35
34
33
30
27
CE
D
15
5
6
D
12
D
13
32
31
NC
NC
A
15
A
13
A
11
A
9
GND
A
6
9
10
11
40
39
NC
D
10
12
29
A
8
28
A
7
D
7
D
9
A
14
40-PIN DIP
40-PIN SOP
13
14
15
16
17
18
19
20
24
21
26
25
23
22
A
4
A
3
A
2
A
1
D
2
D
1
D
3
GND
D
5
D
4
D
6
D
0
OE
A
0
V
CC
A
12
A
10
A
5
D
8
Figure 1. Pin Connections for DI P and
SOP Packages
531024-2
TOP VIEW
40
7
8
11
12
D
8
D
11
37
36
35
34
33
32
29
D
12
9
10
D
9
D
10
31
30
A
11
A
10
GND
A
8
13
14
15
39
38
A
12
GND
16
D
5
NC
D
7
A
9
44-PIN PLCC
17
D
6
D
4
A
13
NC
A
7
41424344123456
D13D14D15CENCNC
VCCNCNCA15A
14
2827262524232221201918
D3D
2
D
1
OE
NC
A
0
A3A
4
A
6
A
5
A
2
A
1
D
0
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
Page 2
531024-3
40
MEMORY
MATRIX
(65,536 x 16)
SENSE AMPLIFIER
30
GND
20
OE
ADDRESS BUFFER
CE
ADDRESS DECODER
CE
BUFFER
2
TIMING
GENERATOR
A
5
A
4
A
3
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
6
A
7
A
15
A
2
A
1
A
0
33
29
26
25
31
27
32
28
24
23
22
21
36
35
34
37
11
V
CC
OE
BUFFER
COLUMN SELECTOR
D5D4D
3
D14D13D12D11D10D9D
8
D6D
7
D
15
D2D1D
0
OUTPUT BUFFER
543 6789101213141516171819
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH531024 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME
A0 – A
15
Addres s i npu t
D
0
– D
15
Data o utp ut
CE Chip E nab le inp ut
SIGNA L PIN NAME
OE Output ena ble in put
V
CC
Pow er supp ly (+5 V )
GND Grou nd
LH531024 CMOS 1M MROM
2
Page 3
531024-4
44
MEMORY
MATRIX
(65,536 x 16)
SENSE AMPLIFIER
34
GND
22
OE
ADDRESS BUFFER
CE
ADDRESS DECODER
CE
BUFFER
3
TIMING
GENERATOR
A
5
A
4
A
3
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
6
A
7
A
15
A
2
A
1
A
0
37
32
29
28
35
30
36
31
27
26
25
24
40
39
38
41
12
V
CC
OE
BUFFER
D5D4D
3
D14D13D12D11D10D9D
8
D6D
7
D
15
D2D1D
0
OUTPUT BUFFER
654 78910111415161718192021
COLUMN SELECTOR
NOTE: Pin numbers apply to the 44-pin QFJ.
Figure 4. LH531024 Block Diagram
CMOS 1M MROM LH531024
3
Page 4
TRUTH TABLE
CE OE D0 – D
15
SUPPLY CURRENT NOTE
HX
High-Z
Standby (ISB)1
LH
Operating (I
CC
)
LL D
0
– D
15
NOTE:
1. X = H or L.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC +0.3 V
Output vo lta ge V
OUT
–0.3 to VCC +0.3 V
Operat ing te mpe ratu re
Topr 0 to +70 °C
Storag e t emp era ture Tstg –65 to +150
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0°C to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Lo w’ voltage V
IL
–0.3 0.8 V
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Output ‘L ow’ v olt age V
OL
IOL = 2 .0 mA 0.4 V
Output ‘H igh ’ vol tag e
V
OH
IOH = –400 µA 2.4 V
Input leakage current | I
LI
|VIN = 0 V to V
CC
10 µA
Output le aka ge cur ren t
| I
LO
|
V
OUT
= 0 V to V
CC
10 µA1
Operat ing cu rre nt
I
CC1
tRC = 10 0 n s 75 mA
2
I
CC2
tRC = 1 µs65mA
I
CC3
tRC = 10 0 n s 70 mA
3
I
CC4
tRC = 1 µs60mA
Standb y c urr ent
I
SB1
CE = V
IH
3mA
I
SB2
CE = VCC – 0.2 V 100
µA
Input cap acitan ce C
IN
f = 1 MHz
T
A
= 25° C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE/OE = V
IH
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
LH531024 CMOS 1M MROM
4
Page 5
AC CHARACTERISTICS (V
CC
= 5 V ±10%, TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. T YP. MAX. UNIT NOTE
Read c yc le t ime t
RC
100 ns
Addres s a cc ess ti me t
AA
100 ns
Chip e nab le acc es s ti me t
ACE
100 ns
Output en abl e d ela y t ime t
OE
50 ns
Output ho ld time t
OH
5ns
CE to out put in Hig h-Z t
CHZ
50 ns
1
OE to out put in Hig h-Z t
OHZ
50 ns
NOTE:
1. T his is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude 0.4 V to 2.6 V
Input sig nal rise time 10 ns
Input/ out put ref ere nce le vel 1.5 V
Output lo ad con dit ion 1TTL +100 pF
CAUTION
To s tabilize the power supply, it is recommended that
a high -frequency bypass capacitor be connected between the VCC pin and the GND pin.
531024-5
t
OE
t
AA
D
0
- D
15
t
OHZ
t
CHZ
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE)
OE
A0 - A
15
NOTE: Data becomes valid after the intervals, tAA, t
ACE
, and tOE, from address
input, chip enable, and output enable, respectively have been met.
(NOTE)
(NOTE)
Figure 5. Timi ng Diagram
CMOS 1M MROM LH531024
5
Page 6
PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.40 [0.213]
4.80 [0.189]
3.55 [0.140]
2.95 [0.116]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
52.30 [2.059]
51.70 [2.035]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.55 [0.179]
3.95 [0.156]
15.24 [0.600]
TYP.
40DIP (DIP040-P-0600)
120
2140
40DIP
40-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
40SOP (SOP040-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
26.50 [1.043]
26.10 [1.028]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
40
21
201
1.40 [0.055]
1.40 [0.055]
40SOP
40-pin, 525-mil SOP
LH531024 CMOS 1M MROM
6
Page 7
404416
7
17
18 28
16.60 [0.654]
17.60 [0.693]
17.40 [0.685]
16.60 [0.654]
17.60 [0.693]
17.40 [0.685]
39
29
16.00 [0.630]
15.20 [0.598]
0.56 [0.022]
0.36 [0.014]
2.80 [0.110]
2.40 [0.094]
4.60 [0.181]
4.20 [0.165]
1.80 [0.071]
2.35 [0.093]
0.85 [0.033]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
44QFJ (QFJ044-P-S650)
44QFJ-1
0.25 [0.010]
C1.1
1.27 [0.050] TYP.
44-pin, 650-mi l QFJ (PLC C)
LH531024
Device Type
X
Package
531024-6
Example: LH531024N (CMOS 1M (64K x 16) Mask-Programmable ROM, 40-pin, 525-mil SOP)
CMOS 1M (64K x 16) Mask-Programmable ROM
D 40-pin, 600-mil DIP (DIP040-P-0600)
N 40-pin, 525-mil SOP (SOP040-P-0525)
U 44-pin, 650-mil QFJ (PLCC) (QFJ044-P-S650)
ORDERING INFORMATION
CMOS 1M MROM LH531024
7
Loading...