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LH531000B
CMOS 1M (128K × 8) MROM
FEATURES
•• 131,072 words × 8 bi t organ izatio n
•• Access time: 150 ns (MAX.)
•• Low powe r consumption :
Operating : 192.5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Programmable
CE/OE/ OE
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Packa ges:
28-pi n , 600 -mil DIP
28-pi n , 450 -mil S OP
•• Mask ROM specifi c pin out
DESCRIPTION
The LH531000B is a mask-programmable ROM
organized as 131,072 × 8 bits. I t is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
531000B-1
TOP VIEW
28-PIN DIP
28-PIN SOP
1
2
3
4
7
8
A
2
A
5
26
25
24
23
22
21
18
15
A
7
A
6
5
6
A
3
A
4
20
19
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
9
10
11
28
27
A
14
A
1
V
CC
12
17
D
5
16
D
4
D
1
D
2
A
0
D
0
A
9
/OE/OE
13
14
A
16
Figure 1. Pin Connections for DIP and
SOP Packages
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NOTE:
1. Active level of CE/OE/OE is mask-programmable.
TRUTH TABLE
PIN 20 CE OE/OE MODE D0 - D
7
SUPPLY CURRENT
CE type
L – Selected D
OUT
Operating (ICC)
H – Non selected High-Z Standby (I
SB
)
OE type
– H/L Selected D
OUT
Operating (ICC)
– L/H Non selected High-Z
531000B-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
28
2
23
21
24
4
7
8
9
A
7
A
6
V
CC
A
4
16
17
1811
19
D
0
MEMORY
MATRIX
(131,072 x 8)
SENSE AMPLIFIER
OUTPUT BUFFER
14
3
GND
D
1D2D3D4D5D6D7
15
12
13
6
25
A
5
5
A
13
26
ADDRESS BUFFER
A
0
10
ADDRESS DECODER
COLUMN SELECTOR
CE/OE
BUFFER
A
14
27
A
15
1
20
TIMING
GENERATOR
A
16
22
CE/OE/OE
Figure 2. LH531000B Block Diagram
PIN DESCRIPTI ON
SIGNAL PIN NAME NOTE
A0 - A
16
Add ress in put
D
0
- D
7
Data ou tpu t
CE/OE/OE
Chip En abl e i npu t o r
Outp ut Ena ble in put
1
SIGNAL PIN NAME NO TE
V
CC
Power s upp ly (+5 V )
GND Groun d
LH531000B CMOS 1M MROM
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ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC +0.3 V
Output vo lta ge V
OUT
–0.3 to VCC +0.3 V
Operating temperature Topr 0 to +70
°C
Storage temperature Tstg –65 to +150
°C
RECOMMENDED OPERATING CON DITIONS (TA = 0 to +70°C)
PA RAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Lo w’ voltage V
IL
–0.3 0.8 V
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Output ‘L ow’ v olt age V
OL
IOL = 2 .0 mA 0.4 V
Output ‘H igh ’ vol tag e V
OH
IOH = –400 µA
2.4 V
Input lea kag e c urr ent
| I
LI
|
V
IN
= 0 V to V
CC
10 µA
Output le aka ge cur ren t | I
LO
|V
OUT
= 0 V to V
CC
10
µA
1
Operat ing cu rre nt
I
CC1
tRC = 15 0 n s 35
mA 2
I
CC2
tRC = 1 µs
25
I
CC3
tRC = 15 0 n s 30
mA 3
I
CC4
tRC = 1 µs20
Standb y c urr ent
I
SB1
CE = V
IH
2mA
I
SB2
CE = VCC – 0.2 V 100
µA
Input cap acitan ce C
IN
f = 1 MHz
T
A
= 25° C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE/OE = V
IH,
OE = V
IL
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC - 0.2 V) or 0. 2 V. CE = 0.2 V, outputs o pen
AC CHARACTERISTICS (V
CC
= 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read c yc le t ime t
RC
150 ns
Addres s a cc ess ti me t
AA
150 ns
Chip e nab le acc es s ti me t
ACE
150 ns
Output en abl e t ime t
OE
70 ns
Output ho ld time t
OH
5ns
CE to out put in Hig h-Z t
CHZ
70 ns
1
OE to out put in Hig h-Z t
OHZ
70 ns
NOTE:
1. Th is is the time required for th e output to become high-impedance.
CMOS 1M MROM LH531000B
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AC TEST CON DITIONS
PA RAMETER RATING
Input voltage amplitude 0.6 V to 2.4 V
Input rise/fall time 10 ns
Input ref erence level
1.5 V
Output reference level 0.8 V and 2.2 V
Output lo ad con dit ion 1TTL +100 pF
t
OE
t
AA
A0 - A
16
t
OHZ
t
CHZ
D0 - D
7
531000B-3
t
RC
t
ACE
CE
OE
t
OH
DATA VALID
(NOTE)
(NOTE)
OE
NOTE: Data becomes valid after t
AA
, t
ACE
, and tOE from address
input, chip enable, and output enable, respectively have been met.
(NOTE)
Figure 3. Timi ng Diagram
LH531000B CMOS 1M MROM
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PACKAGE DIAGRAMS
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28DIP (DIP028-P-0600)
114
1528
28DIP-2
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
36.30 [1.429]
35.70 [1.406]
0° TO 15°
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
28-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOP (SOP028-P-0450)
12.40 [0.488]
11.60 [0.457]
8.80 [0.346]
8.40 [0.331]
10.60 [0.417]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
28 15
141
1.70 [0.067]
1.70 [0.067]
28SOP
28-pin, 450-mil SOP
CMOS 1M MROM LH531000B
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D 28-pin, 600-mil DIP (DIP028-P-0600)
N 28-pin, 450-mil SOP (SOP028-P-0450)
LH531000B
Device Type
X
Package
531000B-7
Example: LH531000BD (CMOS 1M (128K x 8) Mask Programmable ROM, 28-pin, 600-mil DIP)
CMOS 1M (128K x 8) Mask Programmable ROM
ORDERING INFOR MATION
LH531000B CMOS 1M MROM
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