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LH530800A-Y
FEATURES
•• 131,072 words × 8 b it organ izatio n
•• Access times:
500 ns (MAX.) at 2.6 V ≤ V
CC
< 4.5 V
150 ns (MAX.) at 4.5 V ≤ V
CC
≤ 5.5 V
•• Low-pow er con sumptio n:
Operating : 19 3 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Static operation
•• Three-state o utputs
•• Mask-programmable control pin:
Pin 24 = OE/
OE
•• Wide ra nge powe r supp ly :
2.6 V to 5.5 V
•• Packages:
32-pi n , 600 -mil DIP
32-pi n , 525 -mil S OP
DESCRIPTION
The LH530800A-Y is a 1M-bit mask-programmable
ROM organi zed as 131,072 × 8 bits. It is fabricated
using silicon-gate CMOS process technology.
PIN CONNECTIONS
CMOS 1M (128K × 8) 3 V-Drive MROM
530800A-Y-1
TOP VIEW
1
2
3
4
5
6
9
10
A
2
A
5
Vcc
28
27
26
25
24
23
20
17
A
7
A
6
7
8
A
3
A
4
22
21
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
11
12
13
32
31
30
29
NC
A
14
A
1
NC
14
15
16
19
D
5
18
D
4
D
1
D
2
A
0
D
0
A
9
A
16
OE/OE
NC
32-PIN DIP
32-PIN SOP
Figure 1. Pin Connections for DIP and
SOP Packages
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NOTE:
1. Active levels of OE/OE are mask-programmable.
TRUTH TABLE
CE OE/OE D0 - D
7
SUPPLY CURRENT NOTE
H X High-Z Standby (ISB)1
L L/H High-Z Operating (ICC)
L H/L D
OUT
Operating (ICC)
NOTE:
1. X = H or L
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
-0.3 to +7.0 V
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A0 - A
16
Addr ess in put
D
0
- D
7
Data Out put
CE C hip en abl e in pu t
OE/
OE Outp ut e nab le inp ut 1
SIGNAL PIN NAME NOTE
V
CC
Power su ppl y
GND
Groun d
NC No n c onn ect ion
530800A-Y-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
3
24
22
25
6
9
10
A
7
A
6
V
CC
A
4
17
18
191220
D
0
MEMORY
MATRIX
(131,072 x 8)
SENSE AMPLIFIER
5
GND
D
1D2D3D4D5D6D7
23
16
13
14
8
26
A
5
7
A
13
27
OE/OE
ADDRESS BUFFER
CE
A
0
11
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
28
A
15
2
21
TIMING
GENERATOR
A
16
1
OUTPUT BUFFER
4
311530
Figure 2. LH530800A-Y Block Diagram
LH530800A -Y CMOS 1M Mask-Programmable ROM
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Input vol tage V
IN
-0.3 to VCC +0.3 V
Output vo lta ge V
OUT
-0.3 to VCC +0.3 V
Operating temperature Topr 0 to +70
°C
Storag e t emp era ture
Tstg -65 to +150 °C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
2.6 5.5 V
DC CHARACTERISTICS (VCC = 2.6 V to 5.5 V, TA = 0 t o +70°C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Lo w’ voltage V
IL
-0.3 0.4 V
Input ‘Hi gh’ voltage V
IH
0.8 × V
CC
VCC + 0.3 V
Output ‘L ow’ v olt age V
OL
IOL = 400 µA0.4V
Output ‘H igh ’ vol tag e V
OH
IOH = -1 00 µA 0.8 × V
CC
V
Input lea kag e c urr ent
| I
LI
|
V
IN
= 0 V to V
CC
10 µA
Output le aka ge
curren t
| I
LO
|V
OUT
= 0 V t o V
CC
10 µA1
Operat ing cu rre nt
I
CC1
tRC = 1 50 ns 35 mA 2
I
CC2
tRC = 5 00 ns 18 mA 3
I
CC3
tRC = 5 00 ns 12 mA 4
Standb y c urr ent
I
SB1
CE = V
IH
2mA
I
SB2
CE = VCC - 0. 2 V 100
µA
Input cap acitan ce C
IN
f = 1 MH z
T
A
= 25°C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1.
CE/OE = VIH, OE = V
IL
2.
4.5 V ≤ V
CC
≤ 5.5 V, outputs open
3. 3.4 V < V
CC
< 4.5 V, out puts open
4.
2.6 V ≤ VCC ≤ 3. 4 V, outputs open
AC CHARACTERISTICS (TA = 0 to +70°C)
PARAMETER SYMBOL
2.6 V ≤ VCC < 4. 5 V 4. 5 V ≤ VCC ≤ 5. 5 V
UNIT NOTE
MIN. MAX. MIN. M AX.
Read c yc le t ime t
RC
500 150 ns
Addres s a cc ess ti me t
AA
500 150 ns
Chip e nab le acc es s ti me t
ACE
500 150 ns
Output en abl e d ela y t ime t
OE
200 80 ns
Output ho ld time t
OH
10 10 ns
CE to out put in Hig h-Z t
CHZ
150 80 ns
1
OE to out put in Hig h-Z t
OHZ
150 80 ns
NOTE:
1. T his is the time required for the output to become high-impedance.
CMOS 1M Mask-Programmable ROM LH530800A -Y
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AC TEST CONDITIONS
PARAMETER RATING
Input vol tage ampl itude
0.4 V to (0.8 × V
CC
) V
Input rise/fall time 10 ns
Input/ out put ref ere nce le vel 1.5 V
Output load condition 1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that
a hig h-frequency bypass capaci tor be connected between the VCC and the GND pin.
530800A-Y-4
t
OE
t
AA
D
0
- D
7
t
OHZ
t
CHZ
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE)
OE
OE
A0 - A
16
NOTE: Data becomes valid when the last intervals, tAA, t
ACE
, or tOE, have concluded.
(NOTE)
(NOTE)
Figure 3. Timin g Diagram
LH530800A -Y CMOS 1M Mask-Programmable ROM
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PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
41.30 [1.626]
40.70 [1.602]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
32DIP (DIP032-P-0600)
116
1732
32DIP
32-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
17
161
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
CMOS 1M Mask-Programmable ROM LH530800A -Y
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ORDERING INFORMATION
D 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
LH530800A
Device Type
X
Package
-Y
530800A-Y-3
Example: LH530800AD-Y (CMOS 1M (128K x 8) Mask-Programmable ROM,
Low-Voltage Operation, 32-pin, 600-mil DIP)
CMOS 1M (128K x 8) Mask-Programmable ROM
Low-Voltage Operation
LH530800A -Y CMOS 1M Mask-Programmable ROM
6
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