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LH530800A
CMOS 1M (128K × 8) MROM
FEATURES
•• 131,072 words × 8 bi t organ izatio n
•• Access time: 150 ns (MAX.)
•• Power consu mption :
Operating : 192.5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Packa ges:
32-pi n , 600 -mil DIP
32-pi n , 525 -mil S OP
32-pi n , 450 -mil Q FJ (PLC C)
•• JEDEC standard EPROM pinout (DIP)
DESCRIPTION
The LH530800A is a mask-programmable ROM
organized as 131,072 × 8 bits (1,048,576 bits). It is fabricated using silicon-gate CMOS process technology.
PIN CONNECTIONS
530800A-1
TOP VIEW
1
2
3
4
5
6
9
10
A
2
A
5
Vcc
28
27
26
25
24
23
20
17
A
7
A
6
7
8
A
3
A
4
22
21
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
11
12
13
32
31
30
29
NC
A
14
A
1
NC
14
15
16
19
D
5
18
D
4
D
1
D
2
A
0
D
0
A
9
A
16
OE/OE
NC
32-PIN DIP
32-PIN SOP
Figure 1. Pin Connections f or DIP and
SOP Packages
5
6
7
8
9
10
11
A
7
A
6
A
5
A
2
A
1
29
28
27
26
25
24
A
14
A
13
A
8
A
9
OE/OE
A
10
21
14
15
16 20
19
18
17
12
13
A
0
D
0
22
CE
D
7
23
D
1
1234323130
A
12A15A16
NC
VCCNC
NC
32-PIN QFJ TOP VIEW
530800A-7
A
4
A
3
A
11
D
2
GND
D
3D4D5D6
Figure 2. Pin Connections for QFJ
(PLCC) Package
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NOTE:
1. Active level of OE/OE is m ask-programm able.
TRUTH TABLE
CE OE/OE MODE D0 - D
7
SUPPLY CURRENT NOTE
H X Non selected High-Z Standby (ISB)1
L L/H Non selected High-Z Operating (I
CC
)
L H/L Selected D
OUT
Operating (ICC)
NOTE:
1. X = H or L.
530800A-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
32
4
25
23
26
6
9
10
11
A
7
A
6
V
CC
A
4
18
19
20
13
21
D
0
MEMORY
MATRIX
(131,072 x 8)
SENSE AMPLIFIER
16
5
GND
D
1D2D3D4D5D6D7
24
17
14
15
8
27
A
5
7
A
13
28
OE/OE
ADDRESS BUFFER
CE
A
0
12
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
29
A
15
3
22
TIMING
GENERATOR
A
16
2
OUTPUT BUFFER
Figure 3. LH530800A Block Diagram
PIN DESCRIPTI ON
SIGNAL PIN NAME NOTE
A0 - A
16
Addr ess in put
D
0
- D
7
Data Out put
CE Chip en abl e in pu t 1
OE/
OE Outp ut e nab le inp ut 1
SIGNAL PIN NAME NOTE
V
CC
Power su ppl y ( +5 V)
GND Groun d
NC No conne cti on
LH530800A CMOS 1M Mask-Programmable ROM
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ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC +0.3 V
Output vo lta ge V
OUT
–0.3 to VCC +0.3 V
Operating temperature Topr 0 to +70
°C
Storag e t emp era ture
Tstg –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70 °C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C)
PAR AMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Lo w’ voltage V
IL
–0.3 0.8 V
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Output ‘L ow’ v olt age V
OL
IOL = 2 .0 mA 0.4 V
Output ‘H igh ’ vol tag e
V
OH
IOH = –400 µA 2.4 V
Input leakage current | I
LI
|VIN = 0 V to V
CC
10
µA
Output le aka ge cur ren t
| I
LO
|
V
OUT
= 0 V to V
CC
10 µA1
Operat ing cu rre nt
I
CC1
tRC = 15 0 n s 35
mA 2
I
CC2
tRC = 1 µs25
I
CC3
tRC = 15 0 n s 30
mA 3
I
CC4
tRC = 1 µs20
Standb y c urr ent
I
SB1
CE = V
IH
2mA
I
SB2
CE = VCC - 0.2 V 100
µA
Input cap acitan ce C
IN f = 1 MHz
T
A
= 25° C
10 pF
Output ca pac ita nce
C
OUT
10 pF
NOTES:
1. CE/OE = V
IH
or OE = V
IL
2. VIN = VIH or VIL, CE = VIL, outputs open
3. V
IN
= ( VCC - 0.2 V) or 0. 2 V, CE = 0.2 V, outputs o pen
AC CHARACTERISTICS (V
CC
= 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read c yc le t ime t
RC
150 ns
Addres s a cc ess ti me t
AA
150 ns
Chip e nab le tim e t
ACE
150 ns
Output en abl e t ime t
OE
70 ns
Output ho ld time
t
OH
5ns
CE to out put in Hig h-Z t
CHZ
70 ns
1
OE to out put in Hig h-Z t
OHZ
70 ns
NOTE:
1. T his is the time required for the output to become high-impedance.
CMOS 1M Mask-P rogrammable ROM LH530800A
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AC TEST CON DITIONS
PARAMETER RATING
Input voltage amplitude 0.6 V to 2.4 V
Input rise/fall time 10 ns
Input ref erence level
1.5 V
Output reference level 0.8 V and 2.2 V
Output lo ad con dit ion 1TTL +100 pF
t
OE
(NOTE)
t
AA
A0 - A
16
t
OHZ
t
CHZ
D0 - D
7
530800A-3
t
RC
t
ACE
CE
OE
t
OH
DATA VALID
(NOTE)
(NOTE)
OE
NOTE: Data becomes valid after t
AA
, t
ACE
, and tOE from address
input, chip enable and output enable, respectively have been met.
Figure 4. Timi ng Diagram
LH530800A CMOS 1M Mask-Programmable ROM
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PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
41.30 [1.626]
40.70 [1.602]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
32DIP (DIP032-P-0600)
116
1732
32DIP
32-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
17
161
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
CMOS 1M Mask-P rogrammable ROM LH530800A
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D 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
U 32-pin, 450-mil QFJ (PLCC) (QFJ032-P-R450)
LH530800A
Device Type
X
Package
530800A-6
Example: LH530800AD (CMOS 1M (128K x 8) Mask Programmable ROM, 32-pin, 600-mil DIP)
CMOS 1M (128K x 8) Mask Programmable ROM
ORDERING INFORMATION
11.40 [0.449]
0.25 [0.010]
1.20 [0.047]
1.20 [0.047]
2.30 [0.091]
1.90 [0.075]
3.50 [0.138]
3.10 [0.122]
14.00 [0.551]
20
2129
135
4
1
30
14
10.90 [0.429]
10.10 [0.398]
12.50 [0.492]
12.30 [0.484]
15.10 [0.594]
14.90 [0.587]
1.27 [0.050]
TYP.
0.56 [0.022]
0.36 [0.014]
13.50 [0.531]
12.70 [0.500]
32QFJ450
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM (INCHES)
32QFJ (QFJ032-P-R450)
32-pin, 450-mi l QFJ (PLC C)
LH530800A CMOS 1M Mask-Programmable ROM
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