Page 1
LH5268A
CMOS 6 4K (8 K × 8) S tatic RA M
FEATURES
•• 8,192 × 8 bit orga niza ti on
•• Access time: 100 ns (MAX.)
•• Power consu mption :
Operating :
220 mW (MAX.)
55 mW (MAX.) (t
RC
, tWC = 1 µs)
Standb y:
220 µ W (MAX.)
Data reten tion:
3.0 µW (V
CC
= 3 V, TA = 25°C)
•• Fully-static operatio n
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• TTL compatible I/O
•• Packa ges:
28-pi n , 600 -mil DIP
28-pi n , 300 -mil SK-DIP
28-pi n , 450 -mil S OP
DESCRIPTION
The LH5268A is a static RAM organized as 8, 192 × 8
bits. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
1
2
3
4
7
8
A
2
A
5
26
25
24
23
22
21
18
15
A
7
A
6
5
6
A
3
A
4
20
19
A
12
GND
A
8
A
11
A
10
CE
1
9
10
11
28
27
WE
A
1
V
CC
12
17
16
A
0
I/O
1
A
9
13
14
NC
OE
I/O
2
I/O
3
I/O
7
I/O
6
I/O
5
I/O
4
I/O
8
CE
2
5268A-1
TOP VIEW28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
Figure 1. Pin Connections for DIP, SK-DIP,
and SOP Packages
1
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I/O
8
A
4
A
3
6
7
11
15
18
5268A-2
MEMORY
ARRAY
(128 x 512)
13
17
12
16
A
5
5
ROW ADDRESS
BUFFER
WE
A
6
4
A
7
3
27
A
8
25
ROW DECODERS
I/O
CIRCUITS
COLUMN DECODER
V
CC
GND
OE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
22
19
COLUMN ADDRESS
BUFFER
23
A
11A9A10A2
8
24
21
28
14
A
12
2
CE
1
20
26
CE
2
DATA CONTROL
A
0
10
A
1
9
Figure 2. LH5268A Block Diagram
PIN DESCRIPTION
SIGNA L PIN N AME
A0 - A
12
Addre ss inputs
CE1 - CE
2
Chip Ena ble in put
WE Write E na ble inp ut
OE Outpu t E nab le inp ut
SIGNAL PIN NAME
I/O1 - I/O
8
Data i npu ts and ou tpu ts
V
CC
Power sup ply
GND Ground
NC No connec tion
LH5268A CMOS 64K (8 K × 8) Static RAM
2
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TRUTH TABLE
CE
1
CE
2
WE OE MODE I/O1 - I/O
8
SUPPLY CURRENT NOTE
H X X X Deselect High-Z Standby (ISB)1
X L X X Deselect High-Z Standby (I
SB
)1
L H L X Write D
IN
Operating (ICC)1
L H H L Read D
OUT
Operating (ICC)
L H H H Output disable High-Z Operating (I
CC
)
NOTE:
1. X = H or L
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Suppl y v olt age V
CC
-0.3 to +7.0 V 1
Input vol tage V
IN
-0.3 to VCC + 0.3 V 1,2
Operat ing te mpe ratu re
Topr 0 to +70 °C
Storag e t emp era ture
Tstg -65 to +150 °C
NOTES:
1. The maximum applicable voltage on any pin w ith respect to GND.
2.
VIN (MIN.) = -3.0 V f or pulse width ≤50 ns.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Suppl y v olt age V
CC
4.5 5.0 5.5 V
Input vol tage
V
IH
2.2 VCC + 0.3 V
V
IL
-0.3 0.8 V 1
NOTE:
1.
V
IN
(MIN.) = -3.0 V f or pulse width ≤50 ns.
DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5 V ±10%)
PARAMETER SYMBOL CONDITI ONS MIN. MAX. UNIT NOTE
Input lea kage
curren t
I
LI
VIN = 0 to V
CC
-1 1 µA
Output le aka ge
curren t
I
LO
CE1 = VIH or CE2 = V
IL
or OE = VIH or WE = V
IL
V
I/O
= 0 V to V
CC
-1 1
µA
Operat ing cu rre nt I
CC
CE1 = VIL, VIN = VIL or V
IH
CE2 = VIH, I
I/O
= 0 mA
t
CYCLE
=
100 ns
40
mA
CE1 = 0.2 V, VIN = 0.2 V or
V
CC
- 0.2 V
CE
2
= VCC - 0.2 V, I
I/O
= 0 mA
t
CYCLE
=
1.0 µs
10
Standb y c urr ent
I
SB1
CE1 = V
IH or CE2
= V
IL
3mA
I
SB
CE2 ≤ 0.2 V or
CE1 ≥ VCC - 0.2 V
40
µA
1
Output vo lta ge
V
OL
IOL = 2.1 mA 0.4 V
V
OH
IOH = -1.0 mA
2.4 V
NOTE:
1.
CE
2
should be ≥ VCC - 0.2 V or ≤ 0.2 V when CE1 ≥ VCC - 0.2 V.
CMOS 64K (8K × 8) Static RAM LH5268A
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AC CHARACTERISTICS
(1) READ CYCLE (T
A
= 0 to +70°C, VCC = 5 V ±10%)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read c yc le t ime t
RC
100 ns
Addres s a cc ess ti me
t
AA
100 ns
Chip e nab le
acces s t ime
(
CE1)t
AC E 1
100 ns
(CE
2
)t
AC E 2
100 ns
Output en abl e a cce ss tim e t
OE
40 ns
Output ho ld time t
OH
10 ns
Chip e nab le to
output in Lo w-Z
(
CE1)t
LZ1
10 ns 1
(CE
2
)t
LZ2
10 ns 1
Output en abl e t o ou tpu t i n
Low-Z
t
OLZ
5ns1
Chip e nab le to
output in Hi gh- Z
(
CE1)t
HZ1
030ns1
(CE
2
)t
HZ2
030ns1
Output disable to outp ut in
High-Z
t
OHZ
020ns1
NOTE:
1.
Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition
from steady state levels into the test load.
(2) WRITE CYCLE (TA = 0 to +70°C, VCC = 5 V ±10%)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Write c ycl e t ime t
WC
100 ns
Chip e nab le to end of wri te t
CW
80 ns
Addres s v al id t o e nd of writ e t
AW
80 ns
Addres s s etu p t ime t
AS
0ns
Write p uls e w idt h t
WP
60 ns
Write re co ver y ti me t
WR
0ns
Data v ali d t o e nd of w rit e t
DW
40 ns
Data h old ti me t
DH
0ns
Output ac tiv e f rom end of wri te t
OW
10 ns 1
WE to out put in Hig h-Z t
WZ
030ns1
OE to out put in Hig h-Z t
OHZ
020ns1
NOTE:
1.
Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition
from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER MODE NOTE
Input voltage amplitude 0.6 to 2.4 V
Input rise/fall time 10 ns
Timing re fer enc e l eve l 1.5 V
Output load conditions 1TTL + C
L
(100 pF) 1
NOTE:
1. In cludes scope and jig capacitance.
LH5268A CMOS 64K (8 K × 8) Static RAM
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CAPACITANCE 1 (TA = 25°C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input cap acitan ce
C
IN
VIN = 0 V 7 pF
Input/ out put ca pac ita nce
C
I/O
V
I/O
= 0 V 10 pF
NOTE:
1. Th is parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS (TA = 0 to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Data r ete nti on
voltag e
V
CCDR
CE2 ≤ 0.2 V or
CE1 ≥ V
CCDR
- 0.2 V
2.0 5.5 V 1
Data r ete nti on
curren t
I
CCDR
V
CCDR
= 3 V,
CE
2
≤ 0.2 V or
CE1 ≥ V
CCDR
- 0.2 V
TA =
25°C
1
µA
1
20 µA
Chip d isa ble to
data r ete nti on
t
CDR
0ns
Recov ery tim e t
R
t
RC
ns 2
NOTES:
1.
CE
2
should be ≥ V
CCDR
- 0.2 V or ≤ 0.2 V when CE1 ≥ V
CCDR
- 0.2 V
2. t
RC
= Read cycle time
4.5 V
DATA RETENTION MODE
V
CC
0 V
2.2 V
t
CDR
5268A-6
t
R
V
CCDR
CE
1
CE1 ≥ V
CCDR
- 0.2 V
0 V
V
CCDR
0.8 V
4.5 V
DATA RETENTION MODE
t
CDR
t
R
CE2 CONTROL
CE
1
CONTROL (NOTE)
CE
2
0.2 V
NOTE: To control the data retention mode at CE
1
, fix the input level of CE2 between V
CCDR
and V
CCDR
- 0.2 V or 0 V to 0.2 V
during the data retention mode.
V
CC
CE2
≥
Figure 3. Low Voltage Data Retention
CMOS 64K (8K × 8) Static RAM LH5268A
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t
LZ1
t
ACE1
t
OHZ
D
OUT
DATA VALID
OE
t
RC
5268A-3
t
OLZ
NOTE: WE = 'HIGH.'
t
ACE2
t
AA
t
LZ2
CE
1
CE
2
t
HZ1
t
OE
t
OH
t
HZ2
A0 - A
12
Figure 4. Read Cycle
LH5268A CMOS 64K (8 K × 8) Static RAM
6
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DATA VALID
t
DH
t
DW
WE
D
IN
t
CW
t
WC
5268A-4
t
WR
t
CW
t
AW
CE
1
CE
2
t
AS
t
OHZ
t
WP
(NOTE 2)
t
WR
(NOTE 3)
D
OUT
(NOTE 1)
t
WR
1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).
2. t
CW
is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished.
3. t
AS
is defined as the time from address change to writing start.
4. t
WR
is defined as the time from writing finish to address change.
NOTES:
(NOTE 4)
OE
A0 - A
12
Figure 5. Write Cycl e 1
CMOS 64K (8K × 8) Static RAM LH5268A
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DATA VALID
t
DH
t
DW
WE
D
IN
t
CW
t
WC
5268A-5
t
WR
t
CW
t
AW
CE
1
CE
2
t
AS
t
WZ
t
WP
(NOTE 2)
(NOTE 4)
t
WR
(NOTE 3)
D
OUT
(NOTE 6)
(NOTE 1)
t
WR
t
OW
(NOTE 7)
1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).
2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished.
3. t
AS
is defined as the time from address change to writing start.
4. tWR is defined as the time from writing finish to address change.
5. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.
6. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.
7. If CE
1
HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the
outputs will remain high-impedance.
NOTES:
(NOTE 5)
A
0
- A
12
Figure 6. Write Cycl e 2
LH5268A CMOS 64K (8 K × 8) Static RAM
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PACKAGE DIAGRAMS
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28DIP (DIP028-P-0600)
114
1528
28DIP-2
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
36.30 [1.429]
35.70 [1.406]
0° TO 15°
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
28-pin, 600-mil DIP
28DIP (DIP028-P-0300)
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
114
1528
28DIP-6
7.05 [0.278]
6.65 [0.262]
0.51 [0.02] MIN.
4.40 [0.173]
4.00 [0.157]
3.40 [0.134]
3.00 [0.118]
2.54 [0.100]
TYP.
0.56 [0.022]
0.36 [0.014]
0.35 [0.014]
0.15 [0.006]
DETAIL
35.00 [1.378]
34.40 [1.354]
0° TO 15°
3.65 [0.144]
3.25 [0.128]
7.62 [0.300]
TYP.
28-pin, 300-mil DIP
CMOS 64K (8K × 8) Static RAM LH5268A
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Low-Low-power standby
LH5268A
Device TypeXPackage
LL
Power
5268A-7
CMOS 64K (8K x 8) Static RAM
Blank 28 pin, 600-mil DIP (DIP028-P-0600)
D 28-pin, 300-mil DIP (DIP028-P-0300)
N 28-pin, 450-mil SOP (SOP028-P-0450)
Example: LH5268AD-10LL (CMOS 64K (8K x 8) Static RAM, Low-Low-power standby,
100 ns, 28-pin, 300-mil DIP))
- ##
Speed
10 100 Access Time (ns)
ORDERING INFORMATION
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOP (SOP028-P-0450)
12.40 [0.488]
11.60 [0.457]
8.80 [0.346]
8.40 [0.331]
10.60 [0.417]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
28 15
141
1.70 [0.067]
1.70 [0.067]
28SOP
28-pin, 450-mil SOP
LH5268A CMOS 64K (8 K × 8) Static RAM
10
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