LH52258A
CMOS 32K × 8 Static RAM
FEATURES
•• Fast A ccess T imes: 20/25 ns
•• Low-Power Standby when Deselected
•• TTL Compatible I/O
•• 5 V ± 10% Supply
•• Fully-Static Operation
•• JEDEC Standard Pinout
•• Packages:
28-Pin, 300-mil DIP
28-Pin, 300-mil SOJ
FUNCTIONAL DESCRIPTION
The LH52258A is a high-speed 2 62,144 bit static RAM
organized as 32K × 8. A fast , ef ficien t des ign is obt ained
with a CMOS periphery and a matrix constructed with
polysilicon load memory cel ls.
This RAM is fully static in opera tion. The Chip Enable
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HI GH). Standby power (I
SB1
) drops
to its lowest level if E is raised to within 0.2 V of VCC.
Write cycles occur when bo th Chip Enable (E) and
Write Enable (W) are LOW. Data is transferred from the
DQ pins to the memory location specified by the 15
address lines. The proper use of the Output Enable
control (G) can prevent bus contention.
When E is LOW and W is HIGH, a sta tic Read will
occur at the memory location specified by the address
lines. G must be brought LOW to enable the outputs.
Since the device is fully static in operation, new Read
cycles can be performed by simply changing the address .
High-frequency design techniques should be employed to obtain the best performance from this device.
Solid, low-impedance power and ground planes, with
high-frequency decoupling capacitors, are recommended. Serie s terminat ion of the inputs should be considered when tra nsmis sion l ine effect s occur .
PIN CONNECTIONS
52258A-1D
1
2
3
4
5
6
7
8
9
10
11
12
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
V
SS
28
27
26
25
24
23
22
21
20
19
V
CC
W
A
8
A
9
A
11
G
A
10
DQ
7
DQ
6
DQ
5
18
17
DQ
3
13
14
16
15
DQ
0
DQ
4
A
13
DQ
1
DQ
2
E
28-PIN DIP
28-PIN SOJ
TOP VIEW
Figur e 1. Pin Connect ions for DIP and
SOJ Packages
1
TRUTH T ABL E
E G WMODE DQ I
CC
HXX
Not Selected High-Z Standby
LHH
Selected High-Z Active
LLH
Read Data Out Active
LXL
Write Data In Active
PIN DESCRIP TIONS
PIN DESCRIPT ION
A0 – A
14
Address Inputs
DQ0 – DQ
7
Data Input s/ Outp uts
E Chip Enable
G Output Enable
W Write Enable
V
CC
Positive Po wer Supply
V
SS
Ground
52258A-2
MEMORY ARRAY
(32,768 x 8)
I/O CIRCUIT
BLOCK
DECODE
COLUMN
DECODE
A0A
3
A
10
A11A9A8A
13
E
W
A
4
A
5
A
1
A
2
A
6
A
7
A
12
A
14
G
DQ0 - DQ
7
8
8
8
ROW DECODER
Figure 2. LH52258A Block Diagram
LH52258A CMOS 32 K × 8 Static RAM
2
ABSOLUT E MAXIMUM R ATI NGS
1
PARAMETER RATING
VCC to VSS Potential –0.5 V to 7 V
Inpu t Volt age R ange –0.5 V to VCC + 0.5 V
DC Outp ut C ur r en t
2
± 40 mA
Stor age Temper atu re Ran g e –65o to 150oC
Power Dissipat ion (Pac kage Lim it) 1.0 W
NOTES :
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for
transient conditions only. Functional operation o f the devic e at these or any other conditions above those indicated in the ‘Operating Range’
section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliab ility.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGES
SYMBOL PARAMETER MIN TYP MAX UNIT
T
A
T em per at ur e, Ambie nt
070
o
C
V
CC
Supply Volt age
4.5 5.0 5.5 V
V
SS
Supply Volt age
00 0 V
VILLogic ‘0’ Input V olt age
1
–0.5 0.8 V
V
IH
Logic ‘1’ Input Volt age
2.2 VCC + 0.5 V
NOTE:
1. Negative undershoot of up to 3.0 V is permitted once per cycle.
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1MAX UNIT
I
CC1
Opera ting Cur re nt
2
tRC = 20 ns
G ≥ VIH, E ≤ VIL, I
OUT
= 0 mA,
t
CYCLE
= 20 ns
95 150 mA
I
CC1
Opera ting Cur re nt
2
tRC = 25 ns
G ≥ VIH, E ≤ VIL, I
OUT
= 0 mA,
t
CYCLE
= 25 ns
90 140 mA
I
SB1
Standby Cur ren t
E ≥ VCC – 0.2 V 0.005 1 mA
I
SB2
Standby Cur ren t E ≥ V
IH
615mA
ILIInput Leakage Current VCC = 5 .5 V, VIN = 0 V to V
CC
–2 2
µA
I
LO
I/O Leakage Cu rrent VCC = 5 .5 V, VIN = 0 V to V
CC
–2 2
µA
V
OH
Output High Volta ge IOH = –4.0 mA
2.4 V
V
OL
Output Low Volt age IOL = 8 .0 m A
0.4 V
V
DR
Data Retention Voltage E ≥ VCC – 0.2 V
25.5V
IDRData Retention Current
VCC = 3 V, E ≥ VCC – 0.2 V 250
µA
NOTES:
1. Typical values at VCC = 5 V, TA = 25°C.
2. ICC is dependent upon output loading and cycle rates. Specified values are with outputs open, operating at specified cycle times.
CMOS 32K × 8 Static RAM LH52258A
3
AC TEST CONDITIONS
PARAMETER RATING
Input Pulse Levels
V
SS
to 3 V
Input Rise and Fall T imes
3 ns
Input and Output T iming Ref. Le vels
1.5 V
Output Load , Timin g T es ts
Figure 3
CAP ACITANCE
1,2
PAR AMETER RATING
C
IN
(Input Capacit ance)
7 pF
C
DQ
(I/O Capacit ance)
8 pF
NOTES:
1. Capaci tances are maximum values at 25
o
C measured at 1.0 MHz
with V
Bias
= 0 V and VCC = 5.0 V .
2. Guaranteed but not tested.
DATA RETENTION T IMI NG
E must be he ld above the less er of VIH or VCC – 0.2 V
to pre vent impr oper ope ration when VCC < 4 .5 V. E must
be VCC – 0.2 V or greater to meet IDR specification. All
other inputs are ‘Don’t Car e.’
480 Ω
DQ PINS
52258A-3
* INCLUDES JIG AND SCOPE CAPACITANCES
255 Ω
30 pF *
+5 V
Figure 3. Output Load Cir cui t
tRC MIN
0 ns
4.5 V
V
IH
V
IL
V
CC
52258A-4
E
V
DR
E ≥ VDR - 0.2 V
Figure 4. Data Retenti on Timi ng
LH52258A CMOS 32 K × 8 Static RAM
4
AC ELECTRICAL CHARACTERIS TIC S
1
(Over Operatin g Range)
SYMBOL DESCRIPTION
–20 –25
UNITS
MIN MAX MIN MAX
READ CYCLE
t
RC
Read Cycle Time
20 25 ns
t
AA
Address Acc ess T ime 20
25 ns
t
OH
Output Hold from Address Cha n ge
44ns
t
EA
E Low to Valid Data
20 25 ns
t
ELZ
E Low to Output Active
2,3
44ns
t
EHZ
E High to Out put High- Z
2,3
010012ns
tGAG Low to Valid Data
10 12 ns
t
GLZ
G Low to Output Active
2,3
00ns
t
GHZ
G High to Output High-Z
2,3
09010ns
tPUE Low to Power Up Tim e
3
00ns
t
PD
E High to Power Down Tim e
3
25 30 ns
WRITE CYCLE
t
WC
Write Cycle T im e
20 25 ns
t
EW
E Low to End of Write
15 20 ns
t
AW
Address V alid to End of Write
15 20 ns
t
AS
Address Setup
00ns
t
AH
Address Hold from End of Write
00ns
t
WP
W Pulse Width
12 15 ns
t
DW
Input Data Setu p Tim e
10 12 ns
t
DH
Input Data Hold T ime
00ns
t
WHZ
W Low to Output High-Z
2,3
810ns
t
WLZ
W High to Output Active
2,3
00ns
NOTES:
1. AC Electrical Characteristics specified at ‘AC Test Conditions’ levels.
2. Active output to High-Z and High-Z to output active tests specified for a ±500 mV transition from steady state levels into the test load. The test
load has 5 pF capacitances.
3. Guaranteed by design but not tested.
CMOS 32K × 8 Static RAM LH52258A
5
TIMING DIAGRAMS – READ CYCLE
Read Cycle No. 1
Chip is in Read Mode: W is HIGH, E is LOW and G is
LOW. Read cycle timing is referenced from when all
addresses are stable until the first address transition.
Crosshat che d portion of Data Out implies that data lines
are in the Low-Z state but the data is not guaranteed to
be valid until tAA.
Read Cycle No. 2
Chip i s in Read Mode: W is HIGH. Timing illustrated
for the case when addresses are valid before E goes
LOW . Data Out is not specified t o be valid until tEA or tGA,
but may become valid as soon as t
ELZ
or t
GLZ
. Outp uts
will transition from High- Z to Valid Dat a Out. Va lid dat a will
be pre sent following tGA only if tEA timing is met.
t
RC
VALID ADDRESS
t
AA
t
OH
VALID DATA
ADDRESS
DQ
52258A-5
PREVIOUS DATA
Figure 5. Read Cycle No. 1
VALID DATA
E
DQ
t
RC
t
ELZ
t
GHZ
52258A-6
G
t
EHZ
t
EA
t
PU
SUPPLY
CURRENT
t
PD
t
GLZ
t
GA
Figure 6. Read Cyc le No. 2
LH52258A CMOS 32 K × 8 Static RAM
6
TIMING DI AGRAMS – WRITE CYCLE
Addresses must be stable during Write cycles. The
outputs w ill rem ain in the H igh-Z state if W is LOW when
E goes LOW. If G is HIGH, the outputs will remain in the
High-Z state. Although these examples illustrate timing
with G active, it is recommended that G be h eld HIGH for
all Write cycles. This will prevent the LH52258A ’s outputs
from becoming active, preventing bus contention, thereby
reducing syste m noise.
Write Cycle No. 1 (W Controlled)
Chip is selected: E is LOW, G is LOW. Using only W
to co ntrol W rite cyc les m ay not offer the best perfor mance
since both t
WHZ
and tDW timing specifications must be
met.
Write Cycle No. 2 (E Controll ed)
G is LOW. DQ lines may transition to Low-Z if the falling
edge of W occurs after the falling edge of E.
t
WC
VALID ADDRESS
ADDRESS
52258A-7
t
AW
t
AH
t
WP
t
AS
t
WHZ
t
WLZ
t
DH
HIGH-Z
W
DQ
DATA ON
DQ LINES
PREVIOUS OUTPUT
INPUT
t
DW
LOW-Z
Figure 7. Write Cycle No. 1
t
WC
VALID ADDRESS
ADDRESS
52258A-8
W
E
DQ
t
WP
t
EW
t
AH
t
DW
t
DH
t
ELZ
t
AS
DATA ON
DQ LINES
HIGH-Z LOW-Z HIGH-Z INPUT
t
WHZ
Figure 8. Write Cycl e No. 2
CMOS 32K × 8 Static RAM LH52258A
7
28SK-DIP (DIP028-P-0300)
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
114
1528
28DIP-1
7.05 [0.278]
6.65 [0.262]
0.51 [0.020] MIN.
4.40 [0.173]
4.00 [0.157]
3.40 [0.134]
3.00 [0.118]
2.54 [0.100]
TYP.
0.56 [0.022]
0.36 [0.014]
0.35 [0.014]
0.15 [0.006]
DETAIL
35.00 [1.378]
34.40 [1.354]
0° TO 15°
3.65 [0.144]
3.25 [0.128]
7.62 [0.300]
TYP.
28- pin, 300-m il D IP
PACKAGE DIAGRAMS
28SOJ300
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOJ (SOJ28-P-300)
1.27 [0.050]
TYP.
0.53 [0.021]
0.33 [0.013]
DETAIL
7.9 [0.311]
7.5 [0.295]
8.63 [0.340]
8.23 [0.324]
18.7 [0.736]
18.3 [0.720]
1.15 [0.045]
0.85 [0.033]
0.64 [0.025] MIN
7.0 [0.276]
6.6 [0.260]
2.6 [0.102]
2.2 [0.087]
3.7 [0.146]
3.3 [0.130]
0.20 [0.008]
0.8 [0.031]
0.6 [0.024]
0.102 [0.004]
114
28 15
28-pin, 300-mil SOJ
LH52258A CMOS 32 K × 8 Static RAM
8
20
25
Access Time (ns)
D 28-pin, 300-mil DIP (DIP28-P-300)
K 28-pin, 300-mil SOJ (SOJ28-P-300)
LH52258A
Device Type
X
Package
- ##
Speed
52258AMD
CMOS 32K x 8 Static RAM
Example: LH52258AK-25 (CMOS 32K x 8 Static RAM, 25 ns, 28-pin, 300-mil SOJ)
ORDERING INFO RMATION
CMOS 32K × 8 Static RAM LH52258A
9
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