Datasheet LH5164AVHT, LH5164AVHN Datasheet (Sharp)

LH5164AVH

CMOS 6 4K (8 K × 8) S tatic RA M

FEATURES

•• 8,192 × 8 bit orga niza ti on

•• Access time: 200 ns (MAX.)

•• Supply curre nt (MAX.):

Operating : 90 mW
29 mW (t

RC

, tWC = 1 µs)

Standb y: 3.6 µW (MAX.) @ 70°C

10.8 µW (MAX.) @ 85°C
Data reten tion:

0.6 µW (V

CC

= 3 V, tA = 25°C)

•• Low voltag e ope ration : 3.3 V ±0.3 V

•• Fully-static operatio n

•• TTL compatible I/O

•• Three-state outputs

•• Packages:

28-pi n , 450 -mil S OP
28-pi n , 8 × 13 mm

2

TSOP (Type I)

DESCRIPTION

The LH5164AVH is a static RAM organized as
8,192 × 8 bits. It is fabricated using silicon-gate CMOS
process technology.

PIN CONNECTIONS

1
2
3
4

7
8

A

2

A

5

26
25
24
23
22
21

18

15

A

7

A

6

5
6

A

3

A

4

20
19

A

12

GND

A

8

A

11

A

10

CE

1

9

10

11

28
27

WE

A

1

V

CC

12

17
16

A

0

I/O

1

A

9

13
14

NC

OE

I/O

2

I/O

3

I/O

7

I/O

6

I/O

5

I/O

4

I/O

8

CE

2

5164AVH-1

TOP VIEW

28-PIN SOP

Figure 1. Pin Connections for SOP Package

2
3

4
5
6

9

10

7
8

A

11

11

1

28
27
26

25

22

21

24
23

20
19

A

10

28-PIN TSOP (Type I)

12
13
14

17
16

18

15

OE

A

8

A

9

CE

2

WE

A

12

NC

I/O

3

I/O

2

A

1

I/O

8

CE

1

I/O

6

I/O

7

GND

I/O

5

I/O

4

I/O

1

A

0

5164AVH-2

V

CC

A

7

A

6

A

5

A

4

A

3

A

2

TOP VIEW

Figure 2. Pin Connect ions for TSOP Package

1

I/O

8

A

5

A

4

A

3

11

15

18

5164AVH-3

MEMORY

ARRAY

(256 x 256)

13

17

12

16

A

6

WE

A

7

A

12

27

A

8

COLUMN I/O

CIRCUITS

COLUMN SELECT

V

CC

GND

OE

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

22

19

8

A

2A1A0A11

23

9

10

28
14

A

9

CE

1

20

26

CE

2

INPUT

DATA

CONTROL

A

10

21

ROW

SELECT

5
6
7

4

3

2

25

24

NOTE: Pin numbers apply to the 28-pin SOP.

Figure 3. LH5164AVH Block Diagram

PIN DESCRIPTI ON

SIGNA L PIN N AME

A0 - A

12

Addre ss inputs

CE1/CE

2

Chip Ena ble in put

WE Write E na ble inp ut

OE Outpu t E nab le inp ut

SIGNAL PIN NAM E

I/O1 - I/O

8

Data i npu ts and ou tpu ts

V

CC

Power sup ply

GND Ground

NC No connec tion

LH5164AVH CMOS 64K (8 K × 8) Static RAM

2

TRUTH TABLE

CE

1

CE

2

WE OE MODE I/O1 - I/O

8

SUPPLY CU RRENT NOTE

HXXX

Standby High-Z Standby (I

SB

)1

XLXX
L H L X Write Data input Operating (ICC)1
L H H L Read Data output Operating (I

CC

)

L H H H Output disable High-Z Operating (I

CC

)

NOTE:

1. X = H or L

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT NOTE

Suppl y v olt age

V

CC

–0.3 to +7.0 V 1

Input vol tage V

IN

–0.3 to VCC +0.3 V 1, 2
Operating temperature Topr –40 to +85 °C
Storag e t emp era ture

Tstg –65 to +150 °C

NOTES:

1. The maximum applicable voltage on any pin with respect to GND.

2.

V

IN

(MIN.) = –3. 0 V for pu lse widt h ≤ 50 ns.

RECOMMENDED OPERATING CON DITIONS (TA = –40°C to +85°C)

PARAMETE R SYMB OL MIN. TYP. MAX. UNIT N OTE

Suppl y v olt age V

CC

3.0 3.3 3.6 V

Input vol tage

V

IH

VCC – 0.5 VCC + 0.3 V

V

IL

–0.3 0.2 V 1

NOTE:

1.

V

IL

(MIN.) = –3. 0 V for p ulse w idt h ≤50 ns.

DC CHARACTERISTICS 1 (TA = –40°C to +85°C, VCC = 3.3 V ±0.3 V)

PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE

Input lea kage
curren t

I

LI

VIN = 0 V to V

CC

–1.0 1.0

µA

Output le aka ge
curren t

I

LO

CE1 = VIH or CE2 = VIL or

OE = VIH or WE = V

IL

V

I/O

= 0 to V

CC

–1.0 1.0 µA

Operat ing su ppl y
curren t

I

CC

CE1 = 0.2 V, VIN = 0.2 V, or

V

CC

– 0.2 V

CE

2

= VCC – 0.2 V,

Outputs open

t

CYCLE

=

200 ns

25

mA

t

CYCLE

=

1.0 µs

8

Standb y c urr ent

I

SB

CE2 ≤ 0.2 V or

CE1 ≥ VCC – 0.2 V

T

A

≤ +70° C

1.0
µA

1

T

A

≤ +85°C

3.0

I

SB1

CE1 = V

IH or CE2

= V

IL

5mA

Output vo lta ge

V

OL

IOL = 500 µA

0.4 V

V

OH

IOH = –500 µ A

V

CC

–

0.5

V

NOTE:

1.

CE

2

should be ≥ VCC – 0.2 V or ≤ 0. 2 V when CE1 ≥ V

CC

– 0.2 V.

CMOS 64K (8K × 8) Static RAM LH5164AVH

3

READ CYCLE (TA = –40°C to +85°C, VCC = 3.3 V ±0.3 V)

PARAMETER SYMBOL MIN. MAX. UNIT

Read c yc le t ime

t

RC

200 ns

Addres s a cc ess ti me

t

AA

200 ns

CE1 acces s t ime

t

ACE 1

200 ns

CE

2

acces s t ime t

ACE 2

200 ns

Output en abl e a cce ss tim e t

OE

150 ns

Output ho ld time t

OH

10 ns

CE1 Low to ou tpu t i n Lo w-Z t

LZ1

20 ns

CE

2

High t o o utp ut in L ow -Z t

LZ2

20 ns

OE Low to ou tpu t in Lo w-Z t

OLZ

10 ns

CE1 High t o o utp ut in H ig h-Z t

HZ1

060ns

CE

2

Low to ou tpu t i n H igh -Z t

HZ2

060ns

OE Hig h t o o utp ut i n H igh -Z t

OHZ

040ns

WRITE CYCLE (TA = –40°C to +85°C, VCC = 3.3 V ±0.3 V)

PARAMETER SYMBOL MIN. MAX. UNIT

Write c ycl e t ime t

WC

200 ns

CE Low to en d o f wr ite t

CW

180 ns

Addres s v al id t o e nd of writ e t

AW

180 ns

Addres s s etu p t ime

t

AS

0ns

Write p uls e w idt h

t

WP

150 ns

Write re co ver y ti me t

WR

0ns

Input dat a s etu p ti me t

DW

100 ns

Input dat a h old tim e t

DH

0ns

WE Hig h t o o utp ut i n L ow- Z t

OW

20 ns

WE Low to ou tpu t in Hi gh- Z t

WZ

060ns

OE Hig h t o o utp ut i n H igh -Z t

OHZ

040ns

TEST CONDI TIONS

PARAMETER MODE N OTE

Input pulse level 0.2 V to VCC – 0.2 V
Input rise/fall time 10 ns
Input/ out put ti ming le vel 1.5 V
Output lo ad C

L

(100 pF) 1

NOTE:

1. In cludes scope and jig capacitance.

CAPAC ITANC E 1 (TA = 25°C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT

Input cap acitan ce C

IN

VIN = 0 V 7 pF

I/O ca pac ita nce C

I/O

V

I/O

= 0 V 10 pF

NOTE:

1. Th is parameter is sampled and not production tested.

LH5164AVH CMOS 64K (8 K × 8) Static RAM

4

DATA RETENTION CHARACTERISTICS (TA = –40°C to +85°C)

PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE

Data r ete nti on s up ply vo lta ge

V

CCDR

CE2 ≤ 0.2 V or

CE1 ≥ V

CCDR

– 0.2 V

2.0 V 1

Data r ete nti on s up ply cu rren t I

CCDR

V

CCDR

= 3 V,

CE

2

≤ 0.2 V or

CE1 ≥ V

CCDR

– 0.2 V

T

A

=

25°C

0.2

µA

1

T

A

=

70°C

0.6 µA

1.5 µA

Chip d isa ble to da ta rete nti on t

CDR

0ns

Recov ery tim e t

R

t

RC

ns 2

NOTES:

1.

CE

2

should be ≥ V

CCDR

– 0.2 V or ≤ 0.2 V.

2. t

RC

= Read cycle time.

DATA RETENTION MODE

V

CC

0 V

t

CDR

5164AVH-7

t

R

V

CCDR

CE

1

CE1 ≥ V

CCDR

- 0.2 V

CE2 CONTROL

CE

1

CONTROL (NOTE)

NOTE: To control the data retention mode at CE

1

, fix the input level of CE2 between

V

CCDR

to V

CCDR

- 0.2 V or 0 V and 0.2 V during the data retention mode.

- 0.5 V

3.0 V

V

CC

DATA RETENTION MODE

V

CC

0 V

t

CDR

t

R

V

CCDR

CE2

CE

2

≤ 0.2 V

3.0 V

0.2 V

Figure 4. Data Retention Characteristics

CMOS 64K (8K × 8) Static RAM LH5164AVH

5

t

LZ1

t

ACE1

A0 - A

12

t

OHZ

D

OUT

DATA VALID

OE

t

RC

5164AVH-4

t

OLZ

NOTE: WE = 'HIGH.'

t

ACE2

t

AA

t

LZ2

CE

1

CE

2

t

HZ1

t

OE

t

OH

t

HZ2

Figure 5. Read Cycle

LH5164AVH CMOS 64K (8 K × 8) Static RAM

6

DATA VALID

t

DH

t

DW

WE

D

IN

t

CW

OE

t

WC

5164AVH-5

t

WR

t

CW

t

AW

CE

1

CE

2

t

AS

t

OHZ

t

WP

t

WR

D

OUT

t

WR

(NOTE 2)

(NOTE 1)

(NOTE 3)

(NOTE 4)

(NOTE 5)

NOTES:

1. t

CW

is defined as the time from the last occuring transition, either CE1 LOW transition or CE2

HIGH transition, to the time when the writing is finished.

2. t

WR

is defined as the time from writing finish to address change.

3. t

AS

is defined as the time from address change to writing start.

4. The writing occurs during an overlapping period of CE

1

= 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

5. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.

A0 - A

12

Figure 6. Write Cyc l e (OE Controll ed)

CMOS 64K (8K × 8) Static RAM LH5164AVH

7

DATA VALID

t

DH

t

DW

WE

D

IN

t

CW

t

WC

t

CW

t

AW

CE

1

CE

2

t

AS

t

WP

D

OUT

t

WZ

t

WR

t

OW

t

WR

t

WR

5164AVH-6

(NOTE 4)

(NOTE 1)

(NOTE 3)

(NOTE 2)

(NOTE 7)

(NOTE 5)

(NOTE 6)

NOTES:

1. t

CW

is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,

to the time when the writing is finished.

2. tWR is defined as the time from writing finish to address change.

3. t

AS

is defined as the time from address change to writing start.

4. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.

6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition,
the outputs will remain high-impedance.

7. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.

A0 - A

12

Figure 7. Write Cycle (OE Low Fixed)

LH5164AVH CMOS 64K (8 K × 8) Static RAM

8

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

28SOP (SOP028-P-0450)

12.40 [0.488]

11.60 [0.457]

8.80 [0.346]

8.40 [0.331]

10.60 [0.417]

18.20 [0.717]

17.80 [0.701]

0.15 [0.006]

1.025 [0.040]

0.20 [0.008]

0.00 [0.000]

1.025 [0.040]

2.40 [0.094]

2.00 [0.079]

0.20 [0.008]

0.10 [0.004]

0.50 [0.020]

0.30 [0.012]

1.27 [0.050]
TYP.

28 15

141

1.70 [0.067]

1.70 [0.067]

28SOP

28-pin, 450-mil SOP

PACKAGE DIAGRAMS

CMOS 64K (8K × 8) Static RAM LH5164AVH

9

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

28TSOP (TSOP028-P-0813)

28

1

28TSOP

14

15

0.28 [0.011]

0.12 [0.005]

0.55 [0.022]
TYP.

12.00 [0.472]

11.60 [0.457]

13.70 [0.539]

13.10 [0.516]

8.20 [0.323]

7.80 [0.307]

0.15 [0.006]

1.10 [0.043]

0.90 [0.035]

1.20 [0.047]
MAX.

12.60 [0.496]

12.20 [0.480]

0.20 [0.008]

0.10 [0.004]

0.20 [0.008]

0.00 [0.000]

1.10 [0.043]

0.90 [0.035]

0.425 [0.017]

0.20 [0.008]

0.00 [0.000]

0 - 10°

DETAIL

0.425 [0.017]

28-pin, 8 × 13 mm2 TSOP (Type I)

LH5164AVH
Device TypeXPackage

5164AVH-8

CMOS 64K (8K x 8) Static RAM

N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13 mm

2

TSOP (Type I) (TSOP028-P-0813)

Example: LH5164AVHN (CMOS 64K (8K x 8) Static RAM, 28-pin, 450-mil SOP)

ORDERING INFORMATION

LH5164AVH CMOS 64K (8 K × 8) Static RAM

10