Datasheet LH5164A, LH5164AH Datasheet (Sharp)

LH5164A/AH

CMOS 6 4K (8 K × 8) S tatic RA M

FEATURES

•• 8,192 × 8 bit orga niza ti on

•• Access times: 80/10 0 ns (MAX.)

•• Low-pow er consumption :

Operating :

303 mW (MAX.) LH5164A/D/N @ 80 ns 248 mW (MAX.) LH5164A/D/N/T @ 100 ns 275 mW (MAX.) LH5164AH/HD/H N/HT @ 100 ns

Standby:

LH5164A/D/N/T: 5.5 µW (MAX.) LH5164AH/HD/HN/HT:

T

≤ 85°C: 16.5 µW (MAX.)

A

≤ 70°C: 5.5 µW (MAX.)

T

A

•• Fully-static operatio n

PIN CONNECTIONS

28-PIN DIP 28-PIN SK-DIP 28-PIN SOP

1

NC

2

A

12

3

A

7

A

4

6

A

5

A

6

4

A

7

3

8

A

2

A

9

1

A

10

0

I/O

11

1

12

I/O

2

13

I/O

3

14

GND

Figure 1. Pin Connections for DIP, SK-DIP,

and SOP Packages

28 27 26 25 24 23 22 21 20 19 18 17 16 15

V

WE CE A A A OE A CE I/O I/O I/O I/O I/O

CC

2 8 9 11

10

1

8 7 6 5 4

TOP VIEW

5164A-1

•• Three-state outputs

•• Singl e +5 V p owe r su ppl y

•• TTL compatible I/O

•• Wide temp erature ra nge avail abl e

LH5 164A: -10 to +70°C LH5164AH: -40 to +85°C

•• Packages: 28-pi n , 600 -mil DIP 28-pi n , 300 -mil SK-DIP 28-pi n , 450 -mil S OP 28-pi n , 8 × 13 mm

2

TSOP (Type I)

DESCRIPTION

The LH5164A/ AH are static RAMs organized as 8,192 × 8 bits. It is f abricated using silicon-gate CMOS pr ocess technology.

The LH5164AH is designed for wide temperature range from -40 to +85°C.

28-PIN TSOP (Type I)

OE A

CE

WE V

NC A

1

2

11

A

3

9

4

A

8

5

2

6 7

CC

8 9

12

A

10

7

A

11

6

12

A

5

13

A

4

14

A

3

TOP VIEW

28 27

I/O

26

I/O

25

I/O

24

I/O

23 22

21

GND

20

I/O

19

I/O 18 17

16 15

A CE

I/O

I/O A

A A

Figure 2. Pin Connect ions for TSOP Package

10

1 8 7 6 5

4

3 2

1

0 1 2

5164A-8

1

LH5164A /AH CMOS 64K (8 K × 8) Static RAM

A

7

3

A

6

4

A

5

I/O I/O I/O I/O I/O I/O I/O I/O

5

A

4

6

A

3

7

A

25

8

A

24

9

A

2

12

11

1

12

2

13

3

15

4

16

5

17

6

18

7

19

8

BUFFERS

ROW ADDRESS

DATA CONTROL

ROW DECODERS

MEMORY

ARRAY

(256 x 256)

I/O

CIRCUITS

COLUMN DECODERS

COLUMN ADDRESS

BUFFER

V

28

CC

14

GND

27

WE

22

OE

26

CE

2

20

CE

1

9

NOTE: Pin numbers apply to 28-pin DIP, SK-DIP, or SOP.

10 A

0A1A2A10

21

8

23

A

11

Figure 3. LH5164A/AH Bl ock Diagram

PIN DESCRIPTION

SIGNA L PIN N AME

A0 - A

12

CE1 - CE

Addre ss inputs Chip Ena ble in put

2

WE Write E na ble inp ut

OE Outpu t E nab le inp ut

SIGNAL PIN NAME

I/O1 - I/O

V

CC

Data i npu ts and ou tpu ts

8

Power sup ply

GND Ground

NC No connec tion

TRUTH TABLE

CE

1

H X X X Deselect High-Z Standby (ISB)1 X L X X Deselect High-Z Standby (I

L H L X Write D L H H L Read D L H H H Output disable High-Z Operating (I

NOTE:

1. X = H or L

CE

2

WE OE MODE I/O1 - I/O

IN

OUT

SUPPLY CURRENT NOTE

8

Operating (ICC)1 Operating (ICC)

)1

SB

)

CC

5164A-2

2

CMOS 64K (8K × 8) Static RAM LH5164A/AH

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL

Suppl y v olt age V Input vol tage V

CC

IN

Operat ing te mpe ratu re Topr

80 ns 100 ns

RATING RATING

-0.3 to +7.0 -0.3 to +7.0 V 1

-0.3 to VCC + 0.3 -0.3 to VCC + 0.3 V 1, 2

-10 to +70 -10 to +70

-40 to +85 °C4

Storage t emperature Tstg -55 to +150 -55 to +150

NOTES:

1. The maximum applicable voltage on any pin with respect to GND.

2.

(MIN.) = -3.0 V f or pulse width ≤50 ns.

V

IN

3. LH5164A/AD/AN/ AT

4. LH5164AH/AHD/AHN/AHT

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL

Suppl y v olt age V Input vol tage

NOTES:

1.

T

= -10 to +70°C (LH5164A/AD/AN/ AT), TA = -40 to +85°C (LH5164AH/ AHD/AHN/AHT).

A

2.

(MIN.) = -3.0 V f or pulse width ≤50 ns.

V

IN

CC

V

IH

V

IL

MIN. TY P. MAX. MIN. TYP. MAX.

4.5 5.0 5.5 4.5 5.0 5.5 V

2.2 VCC + 0.3 2.2 VCC + 0.3 V

-0.3 0.8 -0.3 0.8 V 2

80 ns 100 ns

1

UNIT NOTE

°C

3

°C

UNIT NOTE

DC CHARACTERISTICS 1 (VCC = 5 V ±10%)

PARAMETER SYMBOL CONDITI ONS MIN. MAX. UNIT NOTE

Input lea kag e c urr ent Output le aka ge

curren t

I

LI

I

LO

CE1 = VIL, VIN = VIL or V

CE2 = VIH, Outputs open

CE1 = VIL, VIN = VIL or V

Operat ing cu rre nt I

CC

CE2 = VIH, Outputs open CE1 = VIL, VIN = 0.2 V or

CE

= VIH, Outputs open

2

Standb y c urr ent I

SB1

CE1 ≥ VCC - 0.2 V

V

Output vo lta ge

NOTES:

1.

T

= -10 to 70°C (LH5164A/AD/ AN/AT), TA = -40 to +85° C (LH5164AH/AHD/AHN/AHT)

A

2. LH5164A/AD/AN/ AT

3. LH5164AH/AHD/AHN/AHT

4.

should be ≥ VCC – 0.2 V or ≤ 0.2 V wh en CE1 ≥ VCC – 0. 2 V

CE

2

OL

V

OH

VIN = 0 to V

CE1 = VIH or CE2 = V

or OE = VIH or WE = V

V

= 0 to V

I/O

V

- 0.2 V

CC

CE1 = V

IH or CE2

CE2 ≤ 0.2 V or

IOL = 2.1 mA 0.4 V

IOH = -1 mA 2.4 V

CC

IH

-1.0 1.0 µA

IL

t

CYCLE

80 ns

t

CYCLE

100 ns

-1.0 1.0 µA

=

55 mA 45

50 3

mA

=

t

CYCLE

1.0 µs

= V

IL

T

≤ 70°C 1.0 µA 2, 3, 4

A

T

≤ 85°C 3.0 µA 3, 4

A

10

5mA

2

3

LH5164A /AH CMOS 64K (8 K × 8) Static RAM

AC CHARACTERISTICS

1

(1) READ CYCLE (VCC = 5 V ±10%)

PARAMETER SYMBOL

Read c yc le t ime t Addres s a cc ess ti me t

(

Chip e nab le acces s t ime

CE1)t

)t

(CE

2

Output en abl e a cce ss tim e t Output ho ld time t

(

Chip e nab le to output in Lo w-Z

CE1)t

(CE

)t

2

Output en abl e t o ou tpu t i n Low-Z

CE1)t

Chip e nab le to output in Hi gh- Z

( (CE

)t

2

Output disable to outp ut in High-Z

RC

AA AC E 1 AC E 2

OE

OH

LZ1 LZ2

t

OLZ

HZ1 HZ2

t

OHZ

80 ns 100 ns

MIN. MAX. M IN. MAX.

80 100 ns

80 100 ns 80 100 ns 80 100 ns

40 40 ns 10 10 ns 10 10 ns 1 10 10 ns 1

5 5 ns 1 0 30 0 30 ns 1

0 30 0 30 ns 1 0 20 0 20 ns 1

(2) WRITE CYCLE (VCC = 5 V ±10%)

PARAMETER SYMBOL

Write c ycl e t ime t Chip e nab le to end of wri te t Addres s v al id t o e nd of writ e t Addres s s etu p t ime t Write p uls e w idt h t Write re co ver y ti me t Data v ali d t o e nd of w rit e t Data h old ti me t Output ac tiv e f rom end of wri te t WE to out put in Hig h-Z t OE to out put in Hig h-Z t

NOTES:

1.

= -10 to +70°C (LH5164A/AD/AN/ AT), TA = -40 to +85°C (LH5164AH/ AHD/AHN/AHT)

T

A

2.

Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load.

WC CW AW

AS WP WR DW DH OW WZ

OHZ

80 ns 100 ns

MIN. MAX. MIN. M AX.

80 100 ns 70 80 ns 70 80 ns

00ns

60 60 ns

00ns

40 40 ns

00ns

10 10 ns 2

030030ns2 020020ns2

UNIT NOTE

AC TEST CONDITIONS

PARAMETER MODE NOTE

Input voltage amplitude 0.6 to 2.4 V Input rise/fall time 10 ns Timing re fer enc e l eve l 1.5 V Output load conditions 1TTL + CL (100 pF) 1

NOTE:

1. In cludes scope and jig capacitance.

4

CMOS 64K (8K × 8) Static RAM LH5164A/AH

CAPACITANCE 1 (TA = 25°C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT

Input cap acitan ce C Input/ out put ca pac ita nce C

NOTE:

1. T his parameter is sampled and not production tested.

IN

I/O

VIN = 0 V 7 pF

V

= 0 V 10 pF

I/O

DATA RETENTION CHARACTERISTICS

PARA METER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE

Data r ete nti on v ol tag e V

Data r ete nti on c urr ent I

Chip d isa ble to da ta rete nti on t Recov ery tim e t

NOTES:

1.

= -10 to +70°C (LH5164A/AD/AN/ AT), TA = -40 to +85°C (LH5164AH/ AHD/AHN/AHT)

T

A

2.

should be ≥ V

CE

2

3. LH5164A/AD/AN/ AT

4. LH5164AH/AHD/AHN/AHT = Read cycle time

5. t

RC

- 0.2 V or ≤ 0.2 V when CE1 ≥ V

CCDR

CDR

R

1

CE2 ≤ 0.2 V or

CE1 ≥ V

V

CCDR

CE

≤ 0.2 V or

2

V

CCDR

≤ 0.2 V or

CE

2

CCDR

– 0. 2 V

- 0.2 V

= 3 V,

- 0.2 V

= 3 V,

- 0.2 V

T

=

A

25°C

=

T

A

40°C

T

=

A

25°C

=

T

A

70°C

2.0 5.5 V 2

0.2 µA 2, 3

0.4 µA 2, 3

0.6

0.2

0.6

µA µA

µA

2, 3 2, 4

2, 4

1.5 µA 2, 4

0ns

t

RC

ns 5

5

LH5164A /AH CMOS 64K (8 K × 8) Static RAM

CONTROL (NOTE)

CE

1

CE2 CONTROL

V

CC

CE2

V

CE

CC

V

4.5 V

2.2 V

CCDR

1

4.5 V

CCDR

0.8 V

0 V

DATA RETENTION MODE

t

CDR

t

R

CE1 ≥ V

CCDR

- 0.2 V

DATA RETENTION MODE

t

CDR

t

R

CE

0.2 V

≥

2

NOTE: To control data hold at CE during the data retention mode.

A0 - A

12

CE

1

CE

2

, fix the input level of CE2 between V

1

OE

CCDR

to V

- 0.2 V or 0 V to 0.2 V

CCDR

Figure 4. Low V oltage Data Ret e ntion

t

RC

t

AA

t

ACE1

t

LZ1

t

ACE2

t

LZ2

t

OE

t

OLZ

t

5164A-6

HZ1

HZ2

OHZ

I/O1 - I/O

8

WE = 'HIGH.'NOTE:

DATA VALID

t

OH

5164A-3

Figure 5. Read Cycle

6

CMOS 64K (8K × 8) Static RAM LH5164A/AH

t

WC

A0 - A

12

OE

t

AW

t

CW

(NOTE 4)

t

WR

(NOTE 2)

CE

1

t

WR

t

WR

CE

t

CW

2

t

AS

(NOTE 3)

t

WP

(NOTE 1)

WE

t

OHZ

(NOTE 5)

D

OUT

D

IN

(NOTE 6)

HIGH-Z

t

DW

DATA VALID

NOTES:

1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

2. t

is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,

CW

to the time when the writing is finished.

3. t

is defined as the time from address change to writing start.

AS

4. t

is defined as the time from writing finish to address change.

WR

5. If CE outputs will remain high-impedance.

LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the

1

6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.

t

DH

5164A-4

Figure 6. Write Cy cl e 1

7

LH5164A /AH CMOS 64K (8 K × 8) Static RAM

t

WC

A0 - A

12

t

AW

t

WR

(NOTE 4)

CE

t

CW

(NOTE 2)

1

t

CW

2

t

AS

(NOTE 3)

t

WP

(NOTE 1)

t

WR

WE

t

(NOTE 5)

D

OUT

(NOTE 7)

D

IN

WZ

HIGH-Z

t

(NOTE 6)

DW

DATA VALID

OE = 'LOW'

NOTES:

1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

2. t

is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,

CW

to the time when the writing is finished.

3. t

is defined as the time from address change to writing start.

AS

4. t

is defined as the time from writing finish to address change.

WR

5. If CE outputs will remain high-impedance.

6. If CE outputs will remain high-impedance.

LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the

1

HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the

1

7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.

Figure 7. Write Cy cl e 2

t

OW

t

DH

5164A-5

8

CMOS 64K (8K × 8) Static RAM LH5164A/AH

PACKAGE DIAGRAMS

28DIP (DIP028-P-0600)

1528

DETAIL

13.45 [0.530]

12.95 [0.510]

114

36.30 [1.429]

35.70 [1.406]

4.50 [0.177]

4.00 [0.157]

5.20 [0.205]

5.00 [0.197]

3.50 [0.138]

3.00 [0.118]

2.54 [0.100] TYP.

DIMENSIONS IN MM [INCHES]

0.60 [0.024]

0.40 [0.016]

MAXIMUM LIMIT

MINIMUM LIMIT

0.51 [0.020] MIN.

28-pin, 600-mil DIP

28DIP (DIP028-P-0300)

1528

0.30 [0.012]

0° TO 15°

0.20 [0.008]

15.24 [0.600] TYP.

28DIP-2

DETAIL

114

35.00 [1.378]

34.40 [1.354]

2.54 [0.100] TYP.

DIMENSIONS IN MM [INCHES]

0.56 [0.022]

0.36 [0.014]

MAXIMUM LIMIT

MINIMUM LIMIT

7.05 [0.278]

6.65 [0.262]

3.65 [0.144]

3.25 [0.128]

4.40 [0.173]

4.00 [0.157]

3.40 [0.134]

3.00 [0.118]

0.51 [0.02] MIN.

28-pin, 300-mi l SK-DIP

0.35 [0.014]

0° TO 15°

0.15 [0.006]

7.62 [0.300] TYP.

28DIP-6

9

LH5164A /AH CMOS 64K (8 K × 8) Static RAM

28SOP (SOP028-P-0450)

1.27 [0.050]

0.50 [0.020]

0.30 [0.012]

28 15

TYP.

1.70 [0.067]

18.20 [0.717]

17.80 [0.701]

DIMENSIONS IN MM [INCHES]

141

0.15 [0.006]

MAXIMUM LIMIT

MINIMUM LIMIT

8.80 [0.346]

8.40 [0.331]

1.70 [0.067]

1.025 [0.040]

12.40 [0.488]

11.60 [0.457]

2.40 [0.094]

2.00 [0.079]

0.20 [0.008]

0.00 [0.000]

28-pin, 450-mil SOP

10.60 [0.417]

0.20 [0.008]

0.10 [0.004]

28SOP

10

CMOS 64K (8K × 8) Static RAM LH5164A/AH

28TSOP (TSOP028-P-0813)

0.28 [0.011]

0.12 [0.005]

28

1

DIMENSIONS IN MM [INCHES]

0.55 [0.022] TYP.

8.20 [0.323]

7.80 [0.307]

MAXIMUM LIMIT

MINIMUM LIMIT

15

12.00 [0.472]

11.60 [0.457]

14

0.15 [0.006]

0.425 [0.017]

1.10 [0.043]

0.90 [0.035]

0.20 [0.008]

0.00 [0.000]

13.70 [0.539]

13.10 [0.516]

1.20 [0.047] MAX.

0.425 [0.017]

1.10 [0.043]

0.90 [0.035]

0.20 [0.008]

0.00 [0.000]

12.60 [0.496]

12.20 [0.480]

0.20 [0.008]

0.10 [0.004]

DETAIL

0 - 10°

28TSOP

28-pin, 8 × 13 mm2 TSOP (Type I)

ORDERING INFORMATION

LH5164A

Device Type

X

Operating

X

Package

- ##

Speed

Temperature

Example: LH5164AD-10L (CMOS 64K (8K x 8) Static RAM, 100 ns, Low-power standby, 28-pin, 300-mil SK-DIP)

L

Power

Low-power standby 10 100

80 80

Access Time (ns)

Blank 28 pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SK-DIP (SK-DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm

2

TSOP (Type I) (TSOP028-P-0813)

Blank -10 to 70°C H -40 to +85°C

CMOS 64K (8K x 8) Static RAM

5164A-7

11

Datasheet LH5164A, LH5164AH Datasheet (Sharp)

Specifications and Main Features

Frequently Asked Questions

User Manual