Datasheet LH28F800SGN-L70, LH28F800SGN-L10 Datasheet (Sharp)

LH28F800SG-L
(FOR SOP)

DESCRIPTION

The LH28F800SG-L flash memory with Smart
Voltage technology is a high-density, low­cost, nonvolatile, read/write storage solution for a
wide range of applications. The LH28F800SG-L
can operate at V
low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Its symmetrically-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for resident flash
arrays, SIMMs and memory cards. Its enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F800SG-L offers
three levels of protection : absolute protection with

PP at GND, selective hardware block locking, or

V
flexible software block locking.These alternatives
give designers ultimate control of their code security
needs.

CC = 2.7 V and VPP = 2.7 V. Its

LH28F800SG-L (FOR SOP)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memory

• Enhanced data protection features
– Absolute protection with V
– Flexible block locking
– Block erase/word write lockout during power

transitions

• SRAM-compatible write interface

• High-density symmetrically-blocked architecture
– Sixteen 32 k-word erasable blocks

• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/chip

• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I

in static mode

• Automated word write and block erase
– Command user interface
– Status register

TM

∗

• ETOX

• Package

V nonvolatile flash technology

–44-pin SOP (SOP044-P-0600)

PP = GND

CC

∗

FEATURES

• SmartVoltage technology
– 2.7 V, 3.3 V or 5 V V
– 2.7 V, 3.3 V, 5 V or 12 V VPP

• High performance read access time
LH28F800SG-L70
– 70 ns (5.0±0.25 V)/80 ns (5.0±0.5 V)/

85 ns (3.3±0.3 V)/100 ns (2.7 to 3.0 V)
LH28F800SG-L10
– 100 ns (5.0 ±0.5 V)/100 ns (3.3±0.3 V)/

120 ns (2.7 to 3.0 V)

• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

CC

ETOX is a trademark of Intel Corporation.

- 1 -

COMPARISON TABLE

44-PIN SOP

(SOP044-P-0600)

VPP

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

GND

OE#
DQ

0

DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RP#
WE#
A

8

A9
A10
A11
A12
A13
A14
A15
A16
NC
GND
DQ

15

DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC

VERSIONS

LH28F800SG-L
(FOR SOP)

LH28F800SG-L
(FOR TSOP, CSP)

LH28F800SGH-L
(FOR TSOP, CSP)

∗1 Refer to the datasheet of LH28F800SG-L/SGH-L (FOR TSOP, CSP).

OPERATING TEMPERATURE

0 to +70˚C 44-pin SOP Controlled by RP# pin

1

∗

0 to +70˚C

1

∗

–40 to +85˚C

PACKAGE

48-pin TSOP (I)

48-ball CSP WP# and RP# pins

48-pin TSOP (I)

48-ball CSP WP# and RP# pins

PIN CONNECTIONS

LH28F800SG-L (FOR SOP)

WRITE PROTECT FUNCTION

Controlled by

Controlled by

TOP VIEW

- 2 -

BLOCK DIAGRAMS

Y GATING

Y DECODER

INPUT

BUFFER

OUTPUT
BUFFER

DQ0-DQ15

VCC

CE#
WE#
OE#
RP#

ADDRESS

LATCH

DATA

COMPARATOR

PROGRAM/ERASE
VOLTAGE SWITCH

STATUS

REGISTER

COMMAND

USER

INTERFACE

WRITE
STATE

MACHINE

DATA

REGISTER

OUTPUT

MULTIPLEXER

IDENTIFIER
REGISTER

ADDRESS
COUNTER

A0-A18

X DECODER

16

32 k-WORD

BLOCKS

RY/BY#

VCC
GND

V

PP

INPUT

BUFFER

I/O

LOGIC

LH28F800SG-L (FOR SOP)

- 3 -

LH28F800SG-L (FOR SOP)

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A

0-A18 INPUT

DQ0-DQ15

INPUT/

OUTPUT

CE# INPUT

RP#

INPUT

OE# INPUT OUTPUT ENABLE : Controls the device's outputs during a read cycle.

WE# INPUT

RY/BY# OUTPUT

V

PP SUPPLY

CC SUPPLY

V

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not internal connected; recommend to be floated.

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at V

HH allows to set permanent

lock-bit. Block erase, word write, or lock-bit configuration with VIH < RP# < VHH produce
spurious results and should not be attempted.

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, word write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and word write is inactive, word write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.

BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :

For erasing array blocks, writing word, or configuring lock-bits. With V
memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid V

PP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious

results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp V

CC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write

ramp V

CC down to GND and then

attempts to the flash memory are inhibited. Device operations at invalid V
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.

PP ≤ VPPLK,

CC voltage

- 4 -

1 INTRODUCTION

This datasheet contains LH28F800SG-L specifi­cations. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800SG-L flash
memory documentation also includes ordering
information which is referenced in Section 7.

LH28F800SG-L (FOR SOP)

the power of 5 V V
highest read performance. V
5 V eliminates the need for a separate 12 V
converter, while V
and word write performance. In addition to flexible
erase and program voltages, the dedicated V
gives complete data protection when V

CC. But, 5 V VCC provides the

PP at 2.7 V, 3.3 V and

PP = 12 V maximizes block erase

PP pin

PP ≤ VPPLK.

1.1 New Features

Key enhancements of LH28F800SG-L SmartVoltage
flash memory are :

• SmartVoltage Technology

• Enhanced Suspend Capabilities

• In-System Block Locking

• Permanent Lock Capability

Note following important differences :

PPLK has been lowered to 1.5 V to support

•V

3.3 V and 5 V block erase, word write, and lock­bit configuration operations. Designs that switch

PP off during read operations should make sure

V
that the V

PP voltage transitions to GND.

• To take advantage of SmartVoltage technology,
allow V

CC connection to 2.7 V, 3.3 V or 5 V.

• Once set the permanent lock bit, the blocks which
have been set block lock-bit can not be erased,
written forever.

1.2 Product Overview

The LH28F800SG-L is a high-performance 8 M-bit
SmartVoltage flash memory organized as 512 k­word of 16 bits. The 512 k-word of data is arranged
in sixteen 32 k-word blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of V
and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.

2.7 to 3.6 V V

CC consumes approximately one-fifth

CC

Table 1 VCC and VPP Voltage Combinations

Offered by SmartVoltage Technology

VCC VOLTAGE VPP VOLTAGE

2.7 V 2.7 V, 3.3 V, 5 V, 12 V

3.3 V 3.3 V, 5 V, 12 V
5 V 5 V, 12 V

Internal VCC and VPP detection circuitry auto­matically configures the device for optimized read
and write operations.

A command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timing
necessary for block erase, word write, and lock-bit
configuration operations.

A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (5 V
V

CC, 12 V VPP) independent of other blocks. Each

block can be independently erased 100 000 times
(1.6 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.

Writing memory data is performed in word
increments typically within 7.5 µs (5 V V

PP). Word write suspend mode enables the

V

CC, 12 V

system to read data from, or write data to any other
flash memory array location.

- 5 -

LH28F800SG-L (FOR SOP)

32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block

7FFFF
78000

77FFF
70000

6FFFF
67FFF

68000
60000

5FFFF
58000

57FFF
50000

4FFFF
48000

47FFF
40000

3FFFF
38000

37FFF
30000

2FFFF
28000

27FFF
20000

1FFFF
18000

17FFF
10000

0FFFF
08000

07FFF
00000

15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

The selected block can be locked or unlocked
individually by the combination of sixteen block lock
bits and the RP#. Block erase or word write must
not be carried out by setting block lock bits and
RP# to V

IH. Even if RP# is set to VHH, block erase

and word write to locked blocks is prohibited by
setting permanent lock bit.

The status register or RY/BY# indicates when the
WSM’s block erase, word write, or lock-bit
configuration operation is finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, word write, or
lock-bit configuration.

RY/BY#-high indicates that the WSM is ready for a
new command, block erase is suspended (and
word write is inactive), word write is suspended, or
the device is in deep power-down mode.

The access time is 70 ns (t
voltage range of 4.75 to 5.25 V over the
temperature range (0 to +70˚C). At 4.5 to 5.5 V

CC, the access time is 80 ns or 100 ns. At lower

V

CC voltage, the access time is 85 ns or 100 ns

V
(3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V).

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
5 V V

CC and 3 mA at 2.7 to 3.6 V VCC.

AVQV) at the VCC supply

CCR current is 1 mA at

When CE# and RP# pins are at V
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.

Fig. 1 Memory Map

- 6 -

CC, the ICC

PHQV) is

PHEL)

2 PRINCIPLES OF OPERATION

The LH28F800SG-L SmartVoltage flash memory
includes an on-chip WSM to manage block erase,
word write, and lock-bit configuration functions. It
allows for : 100% TTL-level control inputs, fixed
power supplies during block erasure, word write,
and lock-bit configuration, and minimal processor
overhead with RAM-like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.

Status register and identifier codes can be
accessed through the CUI independent of the V
voltage. High voltage on VPP enables successful
block erasure, word writing, and lock-bit
configuration. All functions associated with altering
memory contents — block erase, word write, lock­bit configuration, status, and identifier codes — are
accessed via the CUI and verified through the
status register.

Commands are written using standard micro­processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
word write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during write cycles. Writing the appropriate
command outputs array data, accesses the
identifier codes, or outputs status register data.

Interface software that initiates and polls progress
of block erase, word write, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system

PP

LH28F800SG-L (FOR SOP)

software to suspend a block erase to read/write
data from/to blocks other than that which is
suspended. Word write suspend allows system
software to suspend a word write to read data from
any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V

PP power supply

switchable (available only when memory block
erases, word writes, or lock-bit configurations are
required) or hardwired to V

PPH1/2/3. The device

accommodates either design practice and
encourages optimization of the processor-memory
interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase, word
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V
functions are disabled when V
lockout voltage V

LKO or when RP# is at VIL. The

CC is below the write

PP. All write

device’s block locking capability provides additional
protection from inadvertent code or data alteration
by gating erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in­system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes, or status register independent of the V
voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power­down mode, the device automatically resets to read

PP

- 7 -

LH28F800SG-L (FOR SOP)

array mode. Four control pins dictate the data flow
in and out of the component : CE#, OE#, WE# and
RP#. CE# and OE# must be driven active to obtain
data at the outputs. CE# is the device selection
control, and when active enables the selected
memory device. OE# is the data output (DQ

0-DQ15)

control and when active drives the selected
memory data onto the I/O bus. WE# must be at V
and RP# must be at VIH or VHH. Fig. 13 illustrates
read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ

0-DQ15 are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ
in a high-impedance state independent of OE#. If
deselected during block erase, word write, or lock­bit configuration, the device continues functioning,
and consuming active power until the operation
completes.

0-DQ15 outputs are placed

During block erase, word write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time t
after RP# goes to logic-high (V

IH

command can be written.

PHWL is required

IH) before another

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
word write, or lock-bit configuration modes. If a
CPU reset occurs with no flash memory reset,
proper CPU initialization may not occur because
the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In
this application, RP# is controlled by the same
RESET# signal that resets the system CPU.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

PHQV is required

- 8 -

LH28F800SG-L (FOR SOP)

7FFFF

78004
78003
78002
78001
78000

0FFFF

08004
08003
08002
08001
08000
07FFF

00004
00003
00002
00001
00000

Reserved for

Future Implementation

Block 15 Lock Configuration Code

Block 15

Block 1

Block 0

(Blocks 2 through 14)

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

Reserved for

Future Implementation

Permanent Lock Configuration Code

Block 0 Lock Configuration Code

Device Code

Manufacture Code

3.5 Read Identifier Codes

The read identifier codes operation outputs the
manufacture code, device code, block lock
configuration codes for each block, and the
permanent lock configuration code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms. The block lock and
permanent lock configuration codes identify locked
and unlocked blocks and permanent lock-bit setting.

Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.
Set Permanent and Block Lock-Bit commands
require the command and address within the device
(Permanent Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 14 and
Fig. 15 illustrate WE# and CE# controlled write
operations.

4 COMMAND DEFINITIONS

When the VPP ≤ VPPLK, read operations from the
status register, identifier codes, or blocks are
enabled. Placing V

PPH1/2/3 on VPP enables

successful block erase, word write and lock-bit
configuration operations.

Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.

- 9 -

LH28F800SG-L (FOR SOP)

Table 2 Bus Operations

MODE NOTE RP# CE# OE# WE#

Read 1, 2, 3, 8
Output Disable 3
Standby 3

VIHor V
VIHor V
VIHor V

HH
HH
HH

V

IL

V

IL

V

IH

V

IL

V

IH

XXXXHigh Z X
Deep Power-Down 4 VIL XXXXXHigh Z V
Read Identifier Codes 8
Write 3, 6, 7, 8

VIHor V
VIHor V

HH
HH

V

IL

V

IL

V

IL

V

IH

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

PPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

V
CHARACTERISTICS" for V

3. RY/BY# is V

IL or VIH for control pins and addresses, and

PPLK and VPPH1/2/3 voltages.

OL when the WSM is executing internal

block erase, word write, or lock-bit configuration
algorithms. It is V

OH during when the WSM is not busy,

in block erase suspend mode (with word write inactive),
word write suspend mode, or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

IH < RP# < VHH produce spurious results and should

6. V
not be attempted.

7. Refer to Table 3 for valid D

8. Don’t use the timing both OE# and WE# are V

V

IH

V

IH

V

IH

V

IL

ADDRESS

XXD

V

PP

DQ

0-15

OUT

X X High Z X

See Fig. 2

X(

NOTE 5)

XXDINX

IN during a write operation.

RY/BY#

X

OH

V

OH

IL.

- 10 -

LH28F800SG-L (FOR SOP)

COMMAND

Table 3 Command Definitions

BUS CYCLES

REQ’D.

NOTE

FIRST BUS CYCLE SECOND BUS CYCLE

(NOTE 1)

Oper

Addr

(NOTE 9)

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Word Write 2 5, 6 Write WA
Block Erase and
Word Write Suspend
Block Erase and
Word Write Resume

1 5 Write X B0H

1 5 Write X D0H

40H or 10H

Write WA WD

Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H
Set Permanent Lock-Bit 2 7 Write X 60H Write X F1H
Clear Block Lock-Bits 2 8 Write X 60H Write X D0H

NOTES :

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever
goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
permanent lock codes. See Section 4.2 for read
identifier code data.

5. If the block is locked and the permanent lock-bit is not
set, RP# must be at V
write operations. Attempts to issue a block erase or word
write to a locked block while RP# is V

HH to enable block erase or word

HH.

6. Either 40H or 10H is recognized by the WSM as the
word write setup.

7. If the permanent lock-bit is set, RP# must be at V
set a block lock-bit. RP# must be at V
permanent lock-bit. If the permanent lock-bit is set, a
block lock-bit cannot be set. Once the permanent lock-bit
is set, permanent lock-bit reset is unable.

8. If the permanent lock-bit is set, clear block lock-bits
operation is unable. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the permanent
lock-bit is not set, the Clear Block Lock-Bits command
can be done while RP# is V

9. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.

HH.

HH to set the

(NOTE 3)

HH to

- 11 -

LH28F800SG-L (FOR SOP)

4.1 Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, word write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Word
Write Suspend command. The Read Array
command functions independently of the V

PP

voltage and RP# can be VIH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and permanent lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V
V

IH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

CODE ADDRESS DATA

Manufacture Code 00000H 00B0H
Device Code 00001H 0050H
Block Lock Configuration

•Unlocked DQ0 = 0

•Locked DQ0 = 1

•

Reserved for future enhancement

Permanent Lock Configuration

•Unlocked DQ0 = 0

•Locked DQ0 = 1

•

Reserved for future enhancement

NOTES :

1. X selects the specific block lock configuration code to be
read. See Fig. 2 for the device identifier code memory map.

2. Block lock status and permanent lock status are output

0. DQ1-DQ15 are reserved for future enhancement.

by DQ

PP voltage and RP# can be

(NOTE 2)

(NOTE 2)

XX002H

00003H

(NOTE 1)

DQ1-15

DQ1-15

4.3 Read Status Register Command

The status register may be read to determine when
a block erase, word write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to

IH before further reads to update the status

V
register latch. The Read Status Register command
functions independently of the V
can be V

IH or VHH.

PP voltage. RP#

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
be V

IH or VHH. This command is not functional

PP voltage. RP# can

during block erase or word write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,

- 12 -

LH28F800SG-L (FOR SOP)

the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.

This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V

CC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

V

CC =

this high voltage, block contents are protected
against erasure. If block erase is attempted while

PP ≤ VPPLK, SR.3 and SR.5 will be set to "1".

V
Successful block erase requires that the
corresponding block lock-bit be cleared or, if set,
that RP# = V

HH. If block erase is attempted when

the corresponding block lock-bit is set and RP# =
V

IH, SR.1 and SR.5 will be set to "1". Once

permanent lock-bit is set, the blocks which have
been set block lock-bit are unable to erase forever.
Block erase operations with V

IH < RP# < VHH

produce spurious results and should not be
attempted.

4.6 Word Write Command

Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the

completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.

Reliable word writes can only occur when V

CC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

V

CC =

this high voltage, memory contents are protected
against word writes. If word write is attempted while

PP ≤ VPPLK, status register bits SR.3 and SR.4 will

V
be set to "1". Successful word write requires that
the corresponding block lock-bit be cleared or, if
set, that RP# = V

HH. If word write is attempted

when the corresponding block lock-bit is set and
RP# = V

IH, SR.1 and SR.4 will be set to "1". Once

permanent lock-bit is set, the blocks which have
been set block lock-bit are unable to write forever.
Word write operations with V

IH < RP# < VHH

produce spurious results and should not be
attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V
Specification t

WHRH2 defines the block erase

suspend latency.

OH.

- 13 -

LH28F800SG-L (FOR SOP)

At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to V

OL.

However, SR.6 will remain "1" to indicate block
erase suspend status.

The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V

OL. After the Erase

Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). V

PP must remain at VPPH1/2/3

(the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at
V

IH or VHH (the same RP# level used for block

erase). Block erase cannot resume until word write
operations initiated during block erase suspend
have completed.

4.8 Word Write Suspend Command

The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to V
the word write suspend latency.

OH. Specification tWHRH1 defines

At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while word write is suspended are Read
Status Register and Word Write Resume. After
Word Write Resume command is written to the
flash memory, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and RY/BY# will return to

OL. After the Word Write Resume command is

V
written, the device automatically outputs status
register data when read (see Fig. 6). V
remain at V

PPH1/2/3 (the same VPP level used for

PP must

word write) while in word write suspend mode. RP#
must also remain at V

IH or VHH (the same RP#

level used for word write).

4.9 Set Block and Permanent Lock­Bit Commands

The combination of the software command
sequence and hardware RP# pin provides most
flexible block lock (write protection) capability. The
word write/block erase operation is restricted by the
status of block lock-bit, RP# pin and permanent
lock-bit. The status of RP# pin and permanent lock­bit restricts the set block bit. When the permanent
lock-bit has not been set, and when RP# = V
the block lock bit can be set with the status of the
RP# pin. When RP# = V

HH, the permanent lock-bit

can be set with the permanent lock-bit set
command. After the permanent lock-bit has been
set, the write/erase operation to the block lock-bit
can never be accepted. Refer to Table 5 for the
hardware and the software write protection.

Set block lock-bit and permanent lock-bit are
executed by a two-cycle command sequence. The
set block or permanent lock-bit setup along with
appropriate block or device address is written
followed by either the set block lock-bit confirm (and
an address within the block to be locked) or the set
permanent lock-bit confirm (and any device
address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device

HH,

- 14 -

LH28F800SG-L (FOR SOP)

automatically outputs status register data when
read (see Fig. 7). The CPU can detect the
completion of the set lock-bit event by analyzing the
RY/BY# pin output or status register bit SR.7.

When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.

This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Permanent Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when V

PPH1/2/3. In the absence of this high voltage, lock-

V

CC = VCC1/2/3/4 and VPP =

bit contents are protected against alteration.

A successful set block lock-bit operation requires
that the permanent lock-bit be cleared and RP# =

HH. If it is attempted with the permanent lock-bit

V
set, SR.1 and SR.4 will be set to "1" and the
operation will fail. Set block lock-bit operations while

IH < RP# < VHH produce spurious results and

V
should not be attempted. A successful set
permanent lock-bit operation requires that RP# =
V

HH. If it is attempted with RP# = VIH, SR.1 and

SR.4 will be set to "1" and the operation will fail.
Set permanent lock-bit operations with V

HH produce spurious results and should not be

V

IH < RP# <

attempted.

Clear block lock-bits option is executed by a two­cycle command sequence. A clear block lock-bits
setup is first written. After the command is written,
the device automatically outputs status register data
when read (see Fig. 8). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.

When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.

This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock­Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable
clear block lock-bits operation can only occur when

CC = VCC1/2/3/4 and VPP = VPPH1/2/3. In a clear

V
block lock-bits operation is attempted while V

PPLK, SR.3 and SR.5 will be set to "1". In the

V

PP ≤

absence of this high voltage, the block lock-bit
contents are protected against alteration. A
successful clear block lock-bits operation requires
that the permanent lock-bit is not set and RP# =
V

HH. If it is attempted with the permanent lock-bit

set or RP# = V

IH, SR.1 and SR.5 will be set to "1"

and the operation will fail. A clear block lock-bits
operation with V

IH < RP# < VHH produce spurious

results and should not be attempted.

4.10 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the
permanent lock-bit not set and RP# = V
lock-bits can be cleared using the Clear Block Lock­Bits command. If the permanent lock-bit is set, clear
block lock-bits operation is unable. See Table 5
for a summary of hardware and software write
protection options.

HH, block

If a clear block lock-bits operation is aborted due to
V

PP or VCC transition out of valid range or RP#

active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values. Once the permanent lock-bit is set, it
cannot be cleared.

- 15 -

LH28F800SG-L (FOR SOP)

Table 5 Write Protection Alternatives

OPERATION

Block Erase

PERMANENT

LOCK-BIT

X0

or 0

Word Write

1 X Permanent Lock-Bit is set. Block Erase and Word Write Disabled

Set Block 0

Lock-Bit

Set Permanent

Lock-Bit

1

XX

Clear Block 0

Lock-Bits

1

WSMS ESS ECLBS WWSLBS VPPS WWSS DPS R

76543210

BLOCK

LOCK-BIT

VIHor VHHBlock Erase and Word Write Enabled

1V

X

X

Table 6 Status Register Definition

RP# EFFECT

HH Block Lock-Bit Override. Block Erase and Word Write Enabled

V

IH Block is Locked. Block Erase and Word Write Disabled

HH Set Block Lock-Bit Enabled

V

V

IH

Set Block Lock-Bit Disabled

X

Permanent Lock-Bit is set. Set Block Lock-Bit Disabled

HH Set Permanent Lock-Bit Enabled

V

VIH Set Permanent Lock-Bit Disabled

V

HH

Clear Block Lock-Bits Enabled

V

IH

Clear Block Lock-Bits Disabled

X

Permanent Lock-Bit is set. Clear Block Lock-Bits Disabled

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready
0 = Busy

SR.6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended
0 = Block Erase in Progress/Completed

SR.5 =

ERASE AND CLEAR LOCK-BITS STATUS (ECLBS)
1 = Error in Block Erase or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits

SR.4 =

WORD WRITE AND SET LOCK-BIT STATUS (WWSLBS)
1=

Error in Word Write or Set Permanent/Block Lock-Bit
0=

Successful Word Write or Set

Permanent

/Block Lock-Bit

SR.3 = VPP STATUS (VPPS)

PP Low Detect, Operation Abort

1= V
0= VPP OK

SR.2 = WORD WRITE SUSPEND STATUS (WWSS)

1 = Word Write Suspended
0 = Word Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Permanent Lock-Bit, Block Lock-Bit and/or RP#

Lock Detected, Operation Abort

0 = Unlock

SR.0 =

RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES :

Check RY/BY# or SR.7 to determine block erase, word
write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 =

If both SR.5 and SR.4 are
configuration attempt, an improper command sequence was
entered.

SR.3 does not provide a continuous indication of V
The WSM interrogates and indicates the V
Block Erase, Word Write, Set Block/
Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to reports accurate feedback only when V
V

PPH1/2/3.

SR.1 does not provide a continuous indication of permanent
and block lock-bit values. The WSM interrogates the
permanent lock-bit, block lock-bit, and RP# only after Block
Erase, Word Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the attempted
operation, if the block lock-bit is set, permanent lock-bit is set,
and/or RP# is not V
lock configuration codes after writing the Read Identifier Codes
command indicates permanent and block lock-bit status.

SR.0 is reserved for future use and should be masked out
when polling the status register.

HH. Reading the block lock and permanent

"0".

"1"s after a block erase or lock-bit

PP level.

PP level only after

Permanent

Lock-Bit, or

PP ≠

- 16 -

LH28F800SG-L (FOR SOP)

Block Erase

Complete

Start

Write 20H,

Block Address

Write D0H,

Block Address

Read

Status Register

0

SR.7 =

1

Full Status

Check if Desired

Repeat for subsequent block erasures.
Full status check can be done after each block erase or after

a sequence of block erasures.
Write FFH after the last block erase operation to place device

in read array mode.

BUS

OPERATION

Write

Write

Read

Standby

COMMAND

Erase Setup

COMMENTS

Data = 20H
Addr = Within Block to be Erased

Data = D0H
Addr = Within Block to be Erased

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

V

PP Range Error

1

0

SR.1 =

Device Protect Error

1

0

BUS

OPERATION

COMMAND

COMMENTS

Standby

Standby

Check SR.1
1 = Device Protect Detect
RP# = V

IH, Block Lock-Bit is Set

Only required for systems
implementing lock-bit configuration

Check SR.5
1 = Block Erase Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.

If error is detected, clear the status register before attempting
retry or other error recovery.

No

Suspend

Block Erase

Yes

Suspend Block

Erase Loop

Erase

Confirm

Block Erase

Successful

SR.4, 5 =

Command Sequence

Error

1

0

SR.5 =

Block Erase

Error

1

0

Standby

Check SR.3
1 = V

PP Error Detect

Standby

Check SR.4, 5
Both 1 = Command Sequence Error

Fig. 3 Automated Block Erase Flowchart

- 17 -

LH28F800SG-L (FOR SOP)

Word Write

Complete

Start

Write 40H,

Address

Write Word

Data and Address

Read

Status Register

0

SR.7 =

1

Full Status

Check if Desired

Repeat for subsequent word writes.
SR full status check can be done after each word write or after

a sequence of word writes.
Write FFH after the last word write operation to place device

in read array mode.

BUS

OPERATION

Write

Write

Read

Standby

COMMAND

Setup

Word Write

COMMENTS

Data = 40H
Addr = Location to be Written

Data = Data to be Written
Addr = Location to be Written

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

V

PP Range Error

1

0

SR.1 =

Device Protect Error

1

0

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1
1 = Device Protect Detect
RP# = V

IH, Block Lock-Bit is Set

Only required for systems
implementing lock-bit configuration

SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.

If error is detected, clear the status register before attempting
retry or other error recovery.

No

Suspend

Word Write

Yes

Suspend Word

Write Loop

Word Write

Word Write

Successful

SR.4 =

Word Write Error

1

0

Standby

Check SR.3
1 = V

PP Error Detect

Standby

Check SR.4
1 = Data Write Error

Fig. 4 Automated Word Write Flowchart

- 18 -

LH28F800SG-L (FOR SOP)

Block Erase

Resumed

Start

Write B0H

Read

Status Register

0

SR.7 =

1

Word Write

BUS

OPERATION

Write

Read

Standby

Standby

COMMAND

Erase

Suspend

COMMENTS

Data = B0H
Addr = X

Status Register Data
Addr = X

Check SR.7
1 = WSM Ready
0 = WSM Busy

Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed

Erase

Resume

SR.6 =

Write D0H

Done?

Block Erase

Completed

Write FFH

Read

Array Data

1

0

No

Yes

Write

Data = D0H
Addr = X

Read

or Word

Write?

Read

Read Array Data Word Write Loop

Fig. 5 Block Erase Suspend/Resume Flowchart

- 19 -

LH28F800SG-L (FOR SOP)

Word Write Resumed

Start

Write B0H

Read

Status Register

0

SR.7 =

1

Write FFH

BUS

OPERATION

Write

Read

Standby

Standby

COMMAND

Word Write

Suspend

COMMENTS

Data = B0H
Addr = X

Status Register Data
Addr = X

Check SR.7
1 = WSM Ready
0 = WSM Busy

Check SR.2
1 = Word Write Suspended
0 = Word Write Completed

Read Array

SR.2 =

Read

Array Data

Done

Reading

Write D0H

Word Write
Completed

Write FFH

Read

Array Data

1

0

No

Yes

Write

Read

Write

Word Write

Resume

Data = FFH
Addr = X

Read array locations other
than that being written.

Data = D0H
Addr = X

Fig. 6 Word Write Suspend/Resume Flowchart

- 20 -

LH28F800SG-L (FOR SOP)

Set Lock-Bit

Complete

Start

Write 60H,

Block/Device Address

Write 01H/F1H,

Block/Device Address

Read

Status Register

0

SR.7 =

1

Full Status

Check if Desired

Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set

operation or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device

in read array mode.

BUS

OPERATION

Write

Write

Read

Standby

COMMAND

Set

Block/Permanent

Lock-Bit

Setup

COMMENTS

Data = 60H
Addr = Block Address (Block),

Device Address (Permanent)

Data = 01H (Block),

F1H (Permanent)

Addr = Block Address (Block),

Device Address (Permanent)

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

V

PP Range Error

1

0

SR.1 =

Device Protect Error

1

0

BUS

OPERATION

COMMAND

COMMENTS

Standby

Standby

Check SR.1
1 = Device Protect Detect
RP# = V

IH

(Set Permanent Lock-Bit Operation)

RP# = V

IH or

Permanent Lock-Bit is Set

(Set Block Lock-Bit Operation)

Check SR.4
1 = Set Lock-Bit Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple lock-bits are
set before full status is checked.

If error is detected, clear the status register before attempting
retry or other error recovery.

Set

Block or Permanent

Lock-Bit

Confirm

Set Lock-Bit

Successful

SR.4, 5 =

Command Sequence

Error

1

0

SR.4 =

Set Lock-Bit

Error

1

0

Standby

Check SR.3
1 = V

PP Error Detect

Standby

Check SR.4, 5
Both 1 = Command Sequence Error

Fig. 7 Set Block and Permanent Lock-Bit Flowchart

- 21 -

LH28F800SG-L (FOR SOP)

Clear Block Lock-Bits

Complete

Start

Write 60H

Write D0H

Read

Status Register

0

SR.7 =

1

Full Status

Check if Desired

Write FFH after the last clear block lock-bits operation to place
device in read array mode.

BUS

OPERATION

Write

Write

Read

Standby

COMMAND

Clear Block

Lock-Bits

Setup

COMMENTS

Data = 60H
Addr = X

Data = D0H
Addr = X

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

V

PP Range Error

1

0

SR.1 =

Device Protect Error

1

0

BUS

OPERATION

COMMAND

COMMENTS

Standby

Standby

Check SR.1
1 = Device Protect Detect
RP# = V

IH or

Permanent Lock-Bit is Set

Check SR.5
1 = Clear Block Lock-Bits Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command.

If error is detected, clear the status register before attempting
retry or other error recovery.

Clear Block

Lock-Bits

Confirm

Clear Block Lock-Bits

Successful

SR.4, 5 =

Command Sequence

Error

1

0

SR.5 =

Clear Block Lock-Bits

Error

1

0

Standby

Check SR.3
1 = V

PP Error Detect

Standby

Check SR.4, 5
Both 1 = Command Sequence Error

Fig. 8 Clear Block Lock-Bits Flowchart

- 22 -

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three­line control provides for :

a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention

will not occur.

To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.

5.2 RY/BY# and Block Erase, Word Write,
and Lock-Bit Configuration Polling

RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, word
write and lock-bit configuration completion. It
transitions low after block erase, word write, or lock­bit configuration commands and returns to V

OH

when the WSM has finished executing the internal
algorithm.

RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also V

OH when the device is in

block erase suspend (with word write inactive),
word write suspend or deep power-down modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current

LH28F800SG-L (FOR SOP)

issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its V

CC and GND and between its VPP

and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between V

CC

and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.

5.4 VPP Trace on Printed Circuit Boards

Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the V
trace. The V

PP pin supplies the memory cell current

PP power supply

for word writing and block erasing. Use similar trace
widths and layout considerations given to the V

CC

power bus. Adequate VPP supply traces and
decoupling will decrease V

PP voltage spikes and

overshoots.

5.5 VCC, VPP, RP# Transitions

Block erase, word write and lock-bit configuration
are not guaranteed if V
V

PPH1/2/3 range, VCC falls outside of a valid
CC1/2/3/4 range, or RP# ≠ VIH or VHH. If VPP error

V
is detected, status register bit SR.3 is set to "1"
along with SR.4 or SR.5, depending on the
attempted operation. If RP# transitions to V
block erase, word write, or lock-bit configuration,
RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the
device will enter deep power-down. The aborted
operation may leave data partially altered.
Therefore, the command sequence must be

PP falls outside of a valid

IL during

- 23 -

LH28F800SG-L (FOR SOP)

repeated after normal operation is restored. Device
power-off or RP# transitions to V

IL clear the status

register.

The CUI latches commands issued by system
software and is not altered by V

PP or CE#

transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep power­down or after V

CC transitions below VLKO.

After block erase, word write, or lock-bit
configuration, even after V

PPLK, the CUI must be placed in read array mode

V

PP transitions down to

via the Read Array command if subsequent access
to the memory array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against
accidental block erasure, word writing, or lock-bit
configuration during power transitions. Upon power­up, the device is indifferent as to which power
supply (V
circuitry resets the CUI to read array mode at
power-up.

PP or VCC) powers-up first. Internal

5.7 Power Consumption

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.

In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solid­state storage can consume negligible power by
lowering RP# to V
access is again needed, the devices can be read
following the t
required after RP# is first raised to V

6.2.4 through 6.2.6 "AC CHARACTERISTICS

- READ-ONLY and WRITE OPERATIONS" and
Fig. 13, Fig. 14 and Fig. 15 for more information.

IL standby or sleep modes. If

PHQV and tPHWL wake-up cycles

IH. See Section

A system designer must guard against spurious
writes for V

CC voltages above VLKO when VPP is

active. Since both WE# and CE# must be low for a
command write, driving either to V

IH will inhibit

writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.

In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = V

IL regardless of its control inputs

state.

- 24 -

LH28F800SG-L (FOR SOP)

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

Operating Temperature

During Read, Block Erase, Word Write

......

and Lock-Bit Configuration
Temperature under Bias

Storage Temperature

.......................

Voltage On Any Pin

(except VCC, VPP, and RP#)

VCC Supply Voltage

.................

VPP Update Voltage during

Block Erase, Word Write and
Lock-Bit Configuration

..

RP# Voltage with Respect to

GND during Lock-Bit
Configuration Operations

..

Output Short Circuit Current

0 to +70°C

.............

–10 to +80°C

– 65 to +125°C

....

– 2.0 to +7.0 V

– 2.0 to +7.0 V

– 2.0 to +14.0 V

– 2.0 to +14.0 V

..............

100 mA

∗

(NOTE 1)

(NOTE 2)

(NOTE 2)

(NOTE 2, 3)

(NOTE 2, 3)

(NOTE 4)

NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.

∗

WARNING : Stressing the device beyond the

"

Absolute Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.

NOTES :

1. Operating temperature is for commercial product defined

by this specification.

2. All specified voltages are with respect to GND. Minimum

DC voltage is – 0.5 V on input/output pins and – 0.2 V on
V

CC and VPP pins. During transitions, this level may

undershoot to – 2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins and V
which, during transitions, may overshoot to V
for periods < 20 ns.

3. Maximum DC voltage on V

to +14.0 V for periods < 20 ns.

4. Output shorted for no more than one second. No more

than one output shorted at a time.

PP and RP# may overshoot

CC is VCC+0.5 V

CC+2.0 V

6.2 Operating Conditions

SYMBOL

TA Operating Temperature 1
VCC1 VCC Supply Voltage (2.7 to 3.0 V) 2.7 3.0 V
VCC2 VCC Supply Voltage (3.3±0.3 V) 3.0 3.6 V
VCC3 VCC Supply Voltage (5.0±0.25 V) 4.75 5.25 V
V

CC4 VCC Supply Voltage (5.0±0.5 V) 4.50 5.50 V

NOTE :

1. Test condition : Ambient temperature

6.2.1 CAPACITANCE

SYMBOL PARAMETER TYP. MAX. UNIT CONDITION

CIN Input Capacitance 7 10 pF VIN = 0.0 V
COUT Output Capacitance 9 12 pF VOUT = 0.0 V

NOTE :

1. Sampled, not 100% tested.

PARAMETER NOTE MIN. MAX. UNIT VERSION

0

(NOTE 1)

TA = +25˚C, f = 1 MHz

+70 ˚C

LH28F800SG-L70

- 25 -

LH28F800SG-L (FOR SOP)

TEST POINTSINPUT OUTPUT

1.35

1.35

2.7

0.0

1.5

1.5

3.0

0.0

TEST POINTSINPUT OUTPUT

2.0

0.8

2.0

0.8

2.4

0.45

TEST POINTSINPUT OUTPUT

DEVICE

UNDER

TEST

C

L Includes Jig

Capacitance

RL = 3.3 kΩ

C

L

OUT

1.3 V

1N914

6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

AC test inputs are driven at 2.7 V for a logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing
ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.

Fig. 9 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.0 V

AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.

Fig. 10 Transient Input/Output Reference Waveform for VCC = 3.3±0.3 V and

CC = 5.0±0.25 V (High Speed Testing Configuration)

V

AC test inputs are driven at V
begins at V

IH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and V IL. Input rise and fall times (10% to

OH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing

90%) < 10 ns.

Fig. 11 Transient Input/Output Reference Waveform for

VCC = 5.0±0.5 V (Standard Testing Configuration)

Fig. 12 Transient Equivalent Testing Load Circuit

Test Configuration Capacitance Loading Value

TEST CONFIGURATION CL (pF)

VCC = 3.3±0.3 V, 2.7 to 3.0 V 50
VCC = 5.0±0.25 V

(NOTE 1)

VCC = 5.0±0.5 V 100

NOTE :

1. Applied to high-speed product, LH28F800SG-L70.

- 26 -

30

LH28F800SG-L (FOR SOP)

6.2.3 DC CHARACTERISTICS

SYMBOL

I

LI Input Load Current 1 ±0.5 ±1 µA

LO Output Leakage Current 1 ±0.5 ±10 µA

I

PARAMETER NOTE

VCC= 2.7 to 3.6 V VCC= 5.0±0.5 V

TYP. MAX. TYP. MAX.

UNIT

V

CC = VCC Max.

VIN = VCC or GND
V

CC = VCC Max.

VOUT = VCC or GND
CMOS inputs

100 100 µA V

ICCS VCC Standby Current 1, 3, 6

22mAV

CC = VCC Max.

CE# = RP# = V
TTL inputs

CC = VCC Max.

CE# = RP# = VIH

VCC Deep Power-Down

ICCD

Current IOUT (RY/BY#) = 0 mA

11216µA

RP# = GND±0.2 V

CMOS inputs

CC = VCC Max.

V

25 50 mA

ICCR VCC Read Current 1, 5, 6

30 65 mA

CE# = GND
f = 5 MHz (3.3 V, 2.7 V),

I

OUT = 0 mA

TTL inputs

CC = VCC Max.

V
CE# = GND
f = 5 MHz (3.3 V, 2.7 V),

IOUT = 0 mA

VCC Word Write or

ICCW

Set Lock-Bit Current

17 — — mA V

1, 7 17 35 mA V

12 30 mA VPP = 12.0±0.6 V

PP = 2.7 to 3.6 V
PP = 5.0±0.5 V

VCC Block Erase or 17 — — mA VPP = 2.7 to 3.6 V

ICCE Clear Block Lock-Bits 1, 7 17 30 mA VPP = 5.0±0.5 V

Current 12 25 mA VPP = 12.0±0.6 V

CCWS VCC Word Write or Block

I
ICCES Erase Suspend Current
IPPS

VPPStandby or Read Current

IPPR 200 200 µA VPP > VCC

VPP Deep Power-Down

IPPD

Current
VPP Word Write or

IPPW

Set Lock-Bit Current
VPP Block Erase or

IPPE

Clear Block Lock-Bits
Current

PPWS VPP Word Write or Block

I
IPPES Erase Suspend Current

1, 2 6 10 mA CE# = V

1

±15 ±15 µA V

PP ≤ VCC

1 5 5 µA RP# = GND±0.2 V

80 — — mA V

1, 7 80 80 mA V

PP = 2.7 to 3.6 V
PP = 5.0±0.5 V

30 30 mA VPP = 12.0±0.6 V
40 — — mA V

1, 7 40 40 mA V

30 30 mA V

1 200 200 µA V

PP = 2.7 to 3.6 V
PP = 5.0±0.5 V
PP = 12.0±0.6 V

PP = VPPH1/2/3

TEST

CONDITIONS

8 MHz (5 V)

8 MHz (5 V)

IH

CC±0.2 V

- 27 -

LH28F800SG-L (FOR SOP)

6.2.3 DC CHARACTERISTICS (contd.)

SYMBOL

PARAMETER NOTE

VCC= 2.7 to 3.6 V VCC= 5.0±0.5 V

MIN. MAX. MIN. MAX.

UNIT

VIL Input Low Voltage 7 –0.5 0.8 –0.5 0.8 V

CC

V

IH Input High Voltage 7 2.0

V

OL Output Low Voltage 3, 7 0.4 0.45 V IOL = 5.8 mA (VCC = 5 V),

V

+0.5 +0.5

2.0

CC

V

V

V

CC = VCC Min.

IOL= 2.0 mA (VCC= 3.3 V, 2.7 V)

CC = VCC Min.

Output High Voltage

V

OH1

(TTL)

3, 7

2.4 2.4 V

0.85 0.85
V

Output High Voltage

VOH2

(CMOS)

3, 7

CC VCC IOH = –2.5 µA

V

CC VCC

– 0.4 – 0.4 IOH = –100 µA

VPP Lockout Voltage during

VPPLK

Normal Operations
V

PP Voltage during

V

PPH1 Word Write, Block Erase 2.7 3.6 — — V

4, 7 1.5 1.5 V

V
IOH= –2.5 mA (VCC= 5 V),
IOH= –2.0 mA (VCC= 3.3 V, 2.7 V)
VCC = VCC Min.

V

CC = VCC Min.

V

V

or Lock-Bit Operations
V

PP Voltage during

V

PPH2 Word Write, Block Erase 4.5 5.5 4.5 5.5 V

or Lock-Bit Operations
V

PP Voltage during

V

PPH3 Word Write, Block Erase 11.4 12.6 11.4 12.6 V

or Lock-Bit Operations

VLKO VCC Lockout Voltage 2.0 2.0 V
VHH RP# Unlock Voltage 8 11.4 12.6 11.4 12.6 V

Set permanent lock-bit
Override block lock-bit

NOTES :

1. All currents are in RMS unless otherwise noted. Typical
values at nominal V

CC voltage and TA = +25°C. These

currents are valid for all product versions (packages and
speeds).

CCWS and ICCES are specified with the device de-

2. I
selected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of I
I

CCES and ICCR or ICCW, respectively.

CCWS or

3. Includes RY/BY#.

4. Block erases, word writes, and lock-bit configurations are
inhibited when V
range between V

PPH1 (max.) and VPPH2 (min.), between VPPH2 (max.)

V
and V

PPH3 (min.), and above VPPH3 (max.).

PP ≤ VPPLK, and not guaranteed in the
PPLK (max.) and VPPH1 (min.), between

5. Automatic Power Saving (APS) reduces typical I
1 mA at 5 V V

CC and 3 mA at 2.7 to 3.6 V VCC in static

operation.

6. CMOS inputs are either V
inputs are either V

CC±0.2 V or GND±0.2 V. TTL

IL or VIH.

7. Sampled, not 100% tested.

8. Permanent lock-bit set operations are inhibited when
RP# = V

IH. Block lock-bit configuration operations are

inhibited when the permanent lock-bit is set or RP# =
V

IH. Block erases and word writes are inhibited when the

corresponding block lock-bit is set and RP# = V
permanent lock-bits is set. Block erase, word write, and
lock-bit configuration operations are not guaranteed with

IH < RP# < VHH and should not be attempted.

V

TEST

CONDITIONS

IH or the

CCR to

- 28 -

LH28F800SG-L (FOR SOP)

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS

• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C

(NOTE 1)

VERSIONS LH28F800SG-L70 LH28F800SG-L10

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 100 120 ns
tAVQV Address to Output Delay 100 120 ns
tELQV CE# to Output Delay 2 100 120 ns
tPHQV RP# High to Output Delay 600 600 ns
tGLQV OE# to Output Delay 2 45 55 ns
tELQX CE# to Output in Low Z 3 0 0 ns
tEHQZ CE# High to Output in High Z 3 45 55 ns
tGLQX OE# to Output in Low Z 3 0 0 ns
tGHQZ OE# High to Output in High Z 3 20 25 ns

OH

t

Output Hold from Address, CE# or
OE# Change, Whichever Occurs First

30 0 ns

•VCC = 3.3±0.3 V, TA = 0 to +70˚C
VERSIONS LH28F800SG-L70 LH28F800SG-L10

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 85 100 ns
tAVQV Address to Output Delay 85 100 ns
tELQV CE# to Output Delay 2 85 100 ns
tPHQV RP# High to Output Delay 600 600 ns
tGLQV OE# to Output Delay 2 40 45 ns
tELQX CE# to Output in Low Z 3 0 0 ns
tEHQZ CE# High to Output in High Z 3 40 45 ns
tGLQX OE# to Output in Low Z 3 0 0 ns
tGHQZ OE# High to Output in High Z 3 15 20 ns

OH

t

Output Hold from Address, CE# or
OE# Change, Whichever Occurs First

30 0 ns

NOTES :

1. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate.

2. OE# may be delayed up to t

3. Sampled, not 100% tested.

ELQV-tGLQV after the falling edge of CE# without impact on tELQV.

UNIT

UNIT

- 29 -

LH28F800SG-L (FOR SOP)

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.)

(NOTE 1)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C

(NOTE 4)

LH28F800SG-L70

(NOTE 5)

LH28F800SG-L70

(NOTE 5)

LH28F800SG-L10

SYMBOL

VCC±0.25 V

VERSIONS

VCC±0.5 V

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 70 80 100 ns
tAVQV Address to Output Delay 70 80 100 ns
tELQV CE# to Output Delay 2 70 80 100 ns
tPHQV RP# High to Output Delay 400 400 400 ns
tGLQV OE# to Output Delay 2 40 45 50 ns
tELQX CE# to Output in Low Z 3 0 0 0 ns
tEHQZ CE# High to Output in High Z 3 55 55 55 ns
tGLQX OE# to Output in Low Z 3 0 0 0 ns
tGHQZ OE# High to Output in High Z 3 10 10 15 ns

Output Hold from Address,

OH CE# or OE# Change, 3 0 0 0 ns

t

Whichever Occurs First

NOTES :

1. See AC Input/Output Reference Waveform (Fig. 9
through Fig. 11) for maximum allowable input slew rate.

2. OE# may be delayed up to t
edge of CE# without impact on t

3. Sampled, not 100% tested.

4. See Fig. 10 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing

characteristics.

ELQV-tGLQV after the falling

ELQV.

5. See Fig. 11 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing

characteristics.

UNIT

- 30 -

LH28F800SG-L (FOR SOP)

V

OL

V

OH

Standby

Device

Address Selection

Data Valid

ADDRESSES (A)

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

V

IL

V

IL

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

(DQ

0

- DQ15)

RP# (P)

V

CC

High Z High Z

t

AVAV

t

EHQZ

t

GHQZ

t

OH

t

GLQV

t

ELQV

t

GLQX

t

ELQX

t

AVQV

t

PHQV

Valid Output

V

IH

Address Stable

Fig. 13 AC Waveform for Read Operations

- 31 -

LH28F800SG-L (FOR SOP)

6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS

• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C

(NOTE 1)

VERSIONS LH28F800SG-L70 LH28F800SG-L10

SYMBOL

t

AVAV

t

PHWL

t

ELWL

t

WLWH

Write Cycle Time 100 120 ns
RP# High Recovery to WE# Going Low 2 1 1 µs
CE# Setup to WE# Going Low 10 10 ns
WE# Pulse Width 50 50 ns

PARAMETER NOTE MIN. MAX. MIN. MAX.

tPHHWH RP# VHH Setup to WE# Going High 2 100 100 ns
tVPWH VPP Setup to WE# Going High 2 100 100 ns
t

AVWH

t

DVWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

Address Setup to WE# Going High 3 50 50 ns
Data Setup to WE# Going High 3 50 50 ns
Data Hold from WE# High 5 5 ns
Address Hold from WE# High 5 5 ns
CE# Hold from WE# High 10 10 ns

WE# Pulse Width High 30 30 ns
tWHRL WE# High to RY/BY# Going Low 100 100
tWHGL Write Recovery before Read 0 0 ns
tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

QVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

t

•VCC = 3.3±0.3 V, TA = 0 to +70˚C

VERSIONS LH28F800SG-L70 LH28F800SG-L10

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 85 100 ns
tPHWL RP# High Recovery to WE# Going Low 2 1 1 µs
tELWL CE# Setup to WE# Going Low 10 10 ns
tWLWH WE# Pulse Width 50 50 ns
tPHHWH RP# VHH Setup to WE# Going High 2 100 100 ns
tVPWH VPP Setup to WE# Going High 2 100 100 ns
tAVWH Address Setup to WE# Going High 3 50 50 ns
tDVWH Data Setup to WE# Going High 3 50 50 ns
tWHDX Data Hold from WE# High 5 5 ns
tWHAX Address Hold from WE# High 5 5 ns
tWHEH CE# Hold from WE# High 10 10 ns
tWHWL WE# Pulse Width High 30 30 ns
tWHRL WE# High to RY/BY# Going Low 100 100 ns
tWHGL Write Recovery before Read 0 0 ns
tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

QVPH

t

RP# VHHHold from Valid SRD, RY/BY# High

2, 4 0 0 ns

NOTES :

1. Read timing characteristics during block erase, word
write and lock-bit configuration operations are the same
as during read-only operations. Refer to Section 6.2.4
"AC CHARACTERISTICS" for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A
word write, or lock-bit configuration.

4. V

PP should be held at VPPH1/2/3 (and if necessary RP#

should be held at V
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

HH) until determination of block erase,

IN and DIN for block erase,

UNIT

ns

UNIT

- 32 -

LH28F800SG-L (FOR SOP)

6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (contd.)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C
VCC±0.25 V

VERSIONS

VCC±0.5 V

SYMBOL

t

AVAV

PHWL

t
t

ELWL

t

WLWH

t

PHHWH

t

VPWHVPP

t

AVWH

t

DVWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

t

WHRL

t

WHGL

QVVL

t

QVPH

t

Write Cycle Time 70 80 100 ns
RP# High Recovery to WE#
Going Low
CE# Setup to WE# Going Low 10 10 10 ns
WE# Pulse Width 40 40 40 ns
RP# VHHSetup to WE# Going High

Address Setup to WE# Going High
Data Setup to WE# Going High 3 40 40 40 ns
Data Hold from WE# High 5 5 5 ns
Address Hold from WE# High 5 5 5 ns
CE# Hold from WE# High 10 10 10 ns
WE# Pulse Width High 30 30 30 ns
WE# High to RY/BY# Going Low
Write Recovery before Read 0 0 0 ns
VPPHold from Valid SRD,
RY/BY# High
RP# VHHHold from Valid SRD,
RY/BY# High

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

Setup to WE# Going High 2 100 100 100 ns

NOTES :

1. Read timing characteristics during block erase, word
write and lock-bit configuration operations are the same
as during read-only operations. Refer to Section 6.2.4
"AC CHARACTERISTICS" for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A
word write, or lock-bit configuration.

4. V

PP should be held at V PPH1/2/3 (and if necessary RP#

should be held at V
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

HH) until determination of block erase,

IN and DIN for block erase,

(NOTE 5)

LH28F800SG-L70

(NOTE 6)

LH28F800SG-L70

(NOTE 6)

LH28F800SG-L10

2111µs

2 100 100 100 ns

3404040ns

90 90 90 ns

2, 4 0 0 0 ns

2, 4 0 0 0 ns

5. See Fig. 10 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing

characteristics.

6. See Fig. 11 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing

characteristics.

(NOTE 1)

UNIT

- 33 -

VPP (V)

VIH

VIH

VIH

VIH

VIH

VOH

VOL

VIH

VIL

VIL

VIL

VIL

VIL

VIL

VPPH1/2/3

VPPLK

RP# (P)

RY/BY# (R)

DATA (D/Q)

WE# (W)

OE# (G)

CE# (E)

ADDRESSES (A)

t

AVAV tAVWH

tELWL

tWHGL

tWHQV1/2/3/4

tWHWL

tWHDX

DIN

AIN AIN

DIN

High Z

t

PHWL

tWHRL

Valid

SRD

D

IN

tVPWH

tWHEH

VIL

VHH

tQVPHtPHHWH

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

tDVWH

tWLWH

tWHAX

tQVVL

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Fig. 14 AC Waveform for WE#-Controlled Write Operations

LH28F800SG-L (FOR SOP)

- 34 -

LH28F800SG-L (FOR SOP)

6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITES OPERATIONS

(NOTE 1)

•VCC = 2.7 to 3.0 V, TA = 0 to +70˚C
VERSIONS LH28F800SG-L70 LH28F800SG-L10

SYMBOL

t

AVAV

t

PHEL

t

WLEL

t

ELEH

t

PHHEH

t

VPEH

t

AVEH

t

DVEH

t

EHDX

t

EHAX

t

EHWH

t

EHEL

t

EHRL

t

EHGL

t

QVVL
QVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

t

•V

Write Cycle Time 100 120 ns
RP# High Recovery to CE# Going Low 2 1 1 µs
WE# Setup to CE# Going Low 0 0 ns
CE# Pulse Width 70 70 ns
RP# VHHSetup to CE# Going High 2 100 100 ns
VPPSetup to CE# Going High 2 100 100 ns
Address Setup to CE# Going High 3 50 50 ns
Data Setup to CE# Going High 3 50 50 ns
Data Hold from CE# High 5 5 ns
Address Hold from CE# High 5 5 ns
WE# Hold from CE# High 0 0 ns
CE# Pulse Width High 25 25 ns
CE# High to RY/BY# Going Low 100 100 ns
Write Recovery before Read 0 0 ns
VPPHold from Valid SRD, RY/BY# High 2, 4 0 0 ns

CC = 3.3±0.3 V, TA = 0 to +70˚C

PARAMETER NOTE MIN. MAX. MIN. MAX.

VERSIONS LH28F800SG-L70 LH28F800SG-L10

SYMBOL

t

AVAV

t

PHEL

t

WLEL

t

ELEH

t

PHHEH

t

VPEH

t

AVEH

t

DVEH

t

EHDX

t

EHAX

t

EHWH

t

EHEL

t

EHRL

t

EHGL

t

QVVL
QVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

t

Write Cycle Time 85 100 ns
RP# High Recovery to CE# Going Low 2 1 1 µs
WE# Setup to CE# Going Low 0 0 ns
CE# Pulse Width 70 70 ns
RP# VHHSetup to CE# Going High 2 100 100 ns
VPPSetup to CE# Going High 2 100 100 ns
Address Setup to CE# Going High 3 50 50 ns
Data Setup to CE# Going High 3 50 50 ns
Data Hold from CE# High 5 5 ns
Address Hold from CE# High 5 5 ns
WE# Hold from CE# High 0 0 ns
CE# Pulse Width High 25 25 ns
CE# High to RY/BY# Going Low 100 100 ns
Write Recovery before Read 0 0 ns
VPPHold from Valid SRD, RY/BY# High 2, 4 0 0 ns

PARAMETER NOTE MIN. MAX. MIN. MAX.

NOTES :

1. In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A
word write, or lock-bit configuration.

PP should be held at VPPH1/2/3 (and if necessary RP#

4. V
should be held at V
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

HH) until determination of block erase,

IN and DIN for block erase,

UNIT

UNIT

- 35 -

LH28F800SG-L (FOR SOP)

6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITES OPERATIONS (contd.)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C
VCC±0.25 V

VERSIONS

VCC±0.5 V

SYMBOL

t

AVAV

PHEL

t
t

WLEL

t

ELEH

t

PHHEH

t

VPEH

t

AVEH

t

DVEH

t

EHDX

t

EHAX

t

EHWH

t

EHEL

t

EHRL

t

EHGL

QVVL

t

QVPH

t

Write Cycle Time 70 80 100 ns
RP# High Recovery to CE#
Going Low
WE# Setup to CE# Going Low 0 0 0 ns
CE# Pulse Width 50 50 50 ns
RP# VHHSetup to CE# Going High
VPP Setup to CE# Going High 2 100 100 100 ns
Address Setup to CE# Going High
Data Setup to CE# Going High 3 40 40 40 ns
Data Hold from CE# High 5 5 5 ns
Address Hold from CE# High 5 5 5 ns
WE# Hold from CE# High 0 0 0 ns
CE# Pulse Width High 25 25 25 ns
CE# High to RY/BY# Going Low 90 90 90 ns
Write Recovery before Read 0 0 0 ns
VPP Hold from Valid SRD,
RY/BY# High
RP# VHH Hold from Valid SRD,
RY/BY# High

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

NOTES :

1. In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A
word write, or lock-bit configuration.

4. V

PP should be held at VPPH1/2/3 (and if necessary RP#

should be held at V
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

HH) until determination of block erase,

IN and DIN for block erase,

(NOTE 5)

LH28F800SG-L70

(NOTE 6)

LH28F800SG-L70

(NOTE 6)

LH28F800SG-L10

2111µs

2 100 100 100 ns

3404040ns

2, 4 0 0 0 ns

2, 4 0 0 0 ns

5. See Fig. 10 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing

characteristics.

6. See Fig. 11 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing

characteristics.

(NOTE 1)

UNIT

- 36 -

VPP (V)

A

IN

A

IN

VIH

VIH

VIH

VIH

VIH

VOH

VOL

VIH

VIL

VIL

VIL

VIL

VIL

VIL

VPPH1/2/3

VPPLK

RP# (P)

RY/BY# (R)

DATA (D/Q)

CE# (E)

OE# (G)

WE# (W)

ADDRESSES (A)

t

AVAV tAVEH

tWLEL

tEHGL

tEHQV1/2/3/4

tEHEL

tEHDX

DINDIN

High Z

t

PHEL

tEHRL

Valid
SRD

D

IN

tVPEH

tEHWH

VIL

VHH

tQVPHtPHHEH

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

tDVEH

tELEH

tEHAX

tQVVL

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

LH28F800SG-L (FOR SOP)

Fig. 15 AC Waveform for CE#-Controlled Write Operations

- 37 -

6.2.7 RESET OPERATIONS

VIH

VOH

VOL

VIL

RY/BY# (R)

(A) Reset During Read Array Mode

(B) Reset During Block Erase, Word Write, or Lock-Bit Configuration

(C) V

CC Rising Timing

t

PLPH

RP# (P)

VIH

VOH

VOL

VIL

RY/BY# (R)

t

PLRH

tPLPH

RP# (P)

VIH

2.7 V/3.3 V/5 V

VIL

VIL

VCC

t235VPH

RP# (P)

LH28F800SG-L (FOR SOP)

Fig. 16 AC Waveform for Reset Operation

Reset AC Specifications

(NOTE 1)

VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V

MIN. MAX. MIN. MAX.

100 100 ns

2, 3

3. A reset time, t
or RP# going high until outputs are valid.

4. When the device power-up, holding RP#-low minimum
100 ns is required after V
range and also has been in stable there.

- 38 -

20

28 (2.7 V VCC)

PHQV, is required from the latter of RY/BY#

12 µs

CC has been in predefined

PLPH

PLRH

RP# Pulse Low Time (If RP# is tied to VCC,

PARAMETER NOTE

this specification is not applicable)
RP# Low to Reset during Block Erase,
Word Write, or Lock-Bit Configuration
VCC 2.7 V to RP# High

CC 4.5 V to RP# High

V

SYMBOL

t

t

t235VPH VCC 3.0 V to RP# High 4 100 100 ns

NOTES :

1. These specifications are valid for all product versions
(packages and speeds).

2. If RP# is asserted while a block erase, word write, or
lock-bit configuration operation is not executing, the reset
will complete within 100 ns.

UNIT

LH28F800SG-L (FOR SOP)

6.2.8

BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE

•VCC = 2.7 to 3.0 V, TA = 0 to +70˚C

SYMBOL

WHQV1

t
tEHQV1

PARAMETER NOTE

Word Write Time 2 49 63 20 28 15.4 µs

VPP = 2.7 to 3.0 V VPP = 5.0±0.5 V VPP = 12.0±0.6 V

MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. MIN.

Block Write Time 2 1.7 2.1 0.7 1.0 0.56 s
tWHQV2
tEHQV2
tWHQV3
tEHQV3
tWHQV4 Clear Block Lock-Bits
tEHQV4 Time

WHRH1 Word Write Suspend

t
tEHRH1 Latency Time to Read

WHRH2

t

EHRH2 Time to Read

t

•V

SYMBOL

tWHQV1
tEHQV1

Block Erase Time 2 3.0 2.0 1.9 s

Set Lock-Bit Time 2 44 28 24.4 µs

2 3.8 2.6 2.3 s

12.6 10.5 10.5 µs

Erase Suspend Latency

CC = 3.3±0.3 V, TA = 0 to +70˚C

PARAMETER NOTE

34.1 20.2 20.2 µs

VPP = 3.3±0.3 V VPP = 5.0±0.5 V VPP = 12.0±0.6 V

MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. MIN.

Word Write Time 2 35 45 14 20 11 µs

Block Write Time 2 1.2 1.5 0.5 0.7 0.4 s

WHQV2

t
tEHQV2
tWHQV3
tEHQV3
tWHQV4 Clear Block Lock-Bits
tEHQV4 Time
tWHRH1 Word Write Suspend
tEHRH1 Latency Time to Read

WHRH2

t

EHRH2

t

Block Erase Time 2 2.1 1.4 1.3 s

Set Lock-Bit Time 2 31 20 17.4 µs

2 2.7 1.8 1.6 s

9 7.5 7.5 µs

Erase Suspend Latency

Time to Read

24.3 14.4 14.4 µs

NOTES :

1. Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed
versions.

4. Sampled, not 100% tested.

TYP.

TYP.

(NOTE 1)

(NOTE 1)

(NOTE 3, 4)

UNIT

MAX.

UNIT

MAX.

- 39 -

LH28F800SG-L (FOR SOP)

6.2.8

BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (contd.)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C

SYMBOL

t

WHQV1

t

EHQV1

PARAMETER NOTE

Word Write Time 2 10 14 7.5 µs

VPP = 5.0±0.5 V VPP = 12.0±0.6 V

MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

Block Write Time 2 0.4 0.5 0.25 s

t

WHQV2

t

EHQV2

t

WHQV3

t

EHQV3

t

WHQV4

t

EHQV4

t

WHRH1

t

EHRH1

t

WHRH2

t

EHRH2

Block Erase Time 2 1.3 1.2 s

Set Lock-Bit Time 2 18 15 µs

Clear Block Lock-Bits Time 2 1.6 1.5 s

Word Write Suspend Latency Time to Read 7.5 6 µs

Erase Suspend Latency Time to Read 14.4 14.4 µs

NOTES :

1. Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed
versions.

4. Sampled, not 100% tested.

(NOTE 3, 4)

UNIT

MAX.

- 40 -

LH28F800SG-L (FOR SOP)

LH28F800SGN-L70

Device Density
800 = 8 M-bit

Access Speed (ns)
70 : 70 ns (5.0±0.25 V), 80 ns (5.0±0.5 V),

85 ns (3.3±0.3 V), 100 ns (2.7 to 3.0 V)

10 : 100 ns (5.0±0.5 V), 100 ns (3.3±0.3 V),

120 ns (2.7 to 3.0 V)

Package
N = 44-pin SOP (SOP044-P-0600)

Architecture
S = Symmetrical Block

Power Supply Type
G = SmartVoltage Technology

Product line designator for all SHARP Flash products

Operating Temperature = 0 to 70°C

7 ORDERING INFORMATION

VALID OPERATIONAL COMBINATIONS

OPTION ORDER CODE

1 LH28F800SGN-L70 100 ns 85 ns 80 ns 70 ns
2 LH28F800SGN-L10 120 ns 100 ns 100 ns

VCC= 2.7 to 3.0 V VCC= 3.3±0.3 V VCC= 5.0±0.5 V VCC= 5.0±0.25 V

50 pF load, 50 pF load, 100 pF load, 30 pF load,

1.35 V I/O Levels 1.5 V I/O Levels TTL I/O Levels 1.5 V I/O Levels

- 41 -

13.2

16.0

1.27

44_0.4

44

1

23

22

0.15

(14.4)

±0.1

TYP.

±0.4

±0.2

±0.05

0.15 M

0.15

28.2

2.7

1.275

±0.2

±0.1

±0.2

0.15

0.1

Package base plane

44 SOP (SOP044-P-0600)

PACKAGING