Datasheet LH28F800SGB-L10, LH28F800SGR-L70, LH28F800SGR-L10, LH28F800SGHR-L70, LH28F800SGHR-L10 Datasheet (Sharp)

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In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

DESCRIPTION

The LH28F800SG-L/SGH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. The LH28F800SG-L/SGH-L can operate at V

CC = 2.7 V and VPP = 2.7 V. Their

low voltage operation capability realizes longer battery life and suits for cellular phone application. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800SG-L/SGH-L offer three levels of protection : absolute protection with V

PP at GND, selective hardware block locking,

or flexible software block locking.These alternatives give designers ultimate control of their code security needs.

FEATURES

• SmartVoltage technology – 2.7 V, 3.3 V or 5 V V

– 2.7 V, 3.3 V, 5 V or 12 V VPP

• High performance read access time LH28F800SG-L70/SGH-L70 – 70 ns (5.0±0.25 V)/80 ns (5.0±0.5 V)/

85 ns (3.3±0.3 V)/100 ns (2.7 to 3.0 V) LH28F800SG-L10/SGH-L10 – 100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/

120 ns (2.7 to 3.0 V)

• Enhanced automated suspend options – Word write suspend to read – Block erase suspend to word write – Block erase suspend to read

• Enhanced data protection features – Absolute protection with V

PP = GND

– Flexible block locking – Block erase/word write lockout during power

transitions

• SRAM-compatible write interface

• High-density symmetrically-blocked architecture – Sixteen 32 k-word erasable blocks

• Enhanced cycling capability – 100 000 block erase cycles – 1.6 million block erase cycles/chip

• Low power management – Deep power-down mode – Automatic power saving mode decreases I

in static mode

• Automated word write and block erase – Command user interface – Status register

• ETOX

∗

V nonvolatile flash technology

• Packages – 48-pin TSOP TypeI (TSOP048-P-1220)

Normal bend/Reverse bend

–48-ball CSP(FBGA048-P-0808)

∗

ETOX is a trademark of Intel Corporation.

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memories

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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PIN CONNECTIONS

48-PIN TSOP (Type I)

(TSOP048-P-1220)

A15 A14 A13 A12 A11 A10

A8 NC NC

WE#

RP#

WP#

RY/BY#

A17

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 NC GND DQ

DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A

A3B

GND

CE#

OE#

DQ0

A17

WP# WE#

DQ1

DQ2

DQ9

VPP

DQ10

DQ11

DQ3

RP#

DQ12

VCC

DQ4

DQ6

DQ5

DQ13

A11

A10

A12

DQ15

DQ14

DQ7

A14

A13

A15

A16

GND

RY/BY#

A18

(FBGA048-P-0808)

48-BALL CSP

TOP VIEW

COMPARISON TABLE

VERSIONS

OPERATING TEMPERATURE

PACKAGE

WRITE PROTECT FUNCTION

LH28F800SG-L

0 to +70˚C

48-pin TSOP (I)

Controlled by

(FOR TSOP, CSP)

48-ball CSP WP# and RP# pins

LH28F800SGH-L

–40 to +85˚C

48-

TSOP (I)

Controlled by

(FOR TSOP, CSP)

48-

ball

CSP

WP# and RP# pins

LH28F800SG-L

∗

0 to +70˚C 44-pin SOP Controlled by RP# pin

(FOR SOP)

∗1 Refer to the datasheet of LH28F800SG-L (FOR SOP).

NOTE :

Reverse bend available on request.

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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BLOCK DIAGRAM

Y GATING

Y DECODER

INPUT

BUFFER

OUTPUT BUFFER

DQ0-DQ15

VCC

CE# WE# OE# WP# RP#

ADDRESS

LATCH

DATA

COMPARATOR

PROGRAM/ERASE VOLTAGE SWITCH

STATUS

COMMAND

USER

INTERFACE

WRITE STATE

MACHINE

DATA

OUTPUT

MULTIPLEXER

IDENTIFIER

ADDRESS COUNTER

A0-A18

X DECODER

32 k-WORD

BLOCKS

RY/BY#

VCC GND

INPUT

BUFFER

I/O

LOGIC

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

0-A18 INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle.

CE# INPUT

CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provide data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at V

HH allows to set permanent lock-bit. Block erase, word write, or lock-bit

configuration with V

IH < RP# < VHH produce spurious results and should not be

attempted.

OE# INPUT OUTPUT ENABLE : Controls the device's outputs during a read cycle.

WE# INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse.

WP# INPUT

WRITE PROTECT : Master control for block locking. When V

IL, locked blocks cannot be

erased and programmed, and block lock-bits can not be set and reset. READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, word write, or lock-bit configuration). RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and word write is inactive, word write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled.

BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :

For erasing array blocks, writing words, or configuring lock-bits. With V

PP ≤ VPPLK,

memory contents cannot be altered. Block erase, word write, and lock-bit configuration with an invalid V

PP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious

results and should not be attempted. DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or 5 V operation. To switch from one voltage to another, ramp V

CC down to GND and then

ramp V

CC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write

attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted.

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not internal connected; recommend to be floated.

DQ0-DQ15

INPUT/

OUTPUT

RP#

INPUT

RY/BY# OUTPUT

PP SUPPLY

CC SUPPLY

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

1 INTRODUCTION

This datasheet contains LH28F800SG-L/SGH-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F800SG-L/ SGH-L flash memories documentation also includes ordering information which is referenced in Section 7.

1.1 New Features

Key enhancements of LH28F800SG-L/SGH-L SmartVoltage flash memories are :

• SmartVoltage Technology

• Enhanced Suspend Capabilities

• In-System Block Locking

• Permanent Lock Capability,

Note following important differences :

•V

PPLK has been lowered to 1.5 V to support

3.3 V and 5 V block erase, word write, and lockbit configuration operations. Designs that switch V

PP off during read operations should make sure

that the V

PP voltage transitions to GND.

• To take advantage of SmartVoltage technology, allow V

CC connection to 2.7 V, 3.3 V or 5 V.

• Once set the permanent lock bit, the blocks which have been set block lock-bit can not be erased, written forever.

1.2 Product Overview

The LH28F800SG-L/SGH-L are high-performance 8 M-bit SmartVoltage flash memories organized as 512 k-word of 16 bits. The 512 k-word of data is arranged in sixteen 32 k-word blocks which are individually erasable, lockable, and unlockable insystem. The memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of V

and VPP combinations, as shown in Table 1, to meet system performance and power expectations.

2.7 to 3.6 V V

CC consumes approximately one-fifth

the power of 5 V V

CC. But, 5 V VCC provides the

highest read performance. V

PP at 2.7 V, 3.3 V and

5 V eliminates the need for a separate 12 V converter, while V

PP = 12 V maximizes block erase

and word write performance. In addition to flexible erase and program voltages, the dedicated V

PP pin

gives complete data protection when V

PP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations

Offered by SmartVoltage Technology

Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations.

A command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timing necessary for block erase, word write, and lock-bit configuration operations.

A block erase operation erases one of the device’s 32 k-word blocks typically within 1.2 second (5 V V

CC, 12 V VPP) independent of other blocks. Each

block can be independently erased 100 000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block.

Writing memory data is performed in word increments typically within 7.5 µs (5 V V

CC, 12 V

PP). Word write suspend mode enables the

system to read data from, or write data to any other flash memory array location.

VCC VOLTAGE VPP VOLTAGE

2.7 V

2.7 V, 3.3 V, 5 V, 12 V

3.3 V 3.3 V, 5 V, 12 V 5 V 5 V, 12 V

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

The selected block can be locked or unlocked individually by the combination of sixteen block lock bits and the RP# or WP#. Block erase or word write must not be carried out by setting block lock bits and setting WP# to low and RP# to V

IH. Even

if WP# is high state or RP# is set to V

HH, block

erase and word write to locked blocks is prohibited by setting permanent lock bit.

The status register or RY/BY# indicates when the WSM’s block erase, word write, or lock-bit configuration operation is finished.

The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, word write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the device is in deep powerdown mode.

The access time is 70 ns (t

AVQV) at the VCC supply

voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70°C (LH28F800SG-L)/ – 40 to +85°C (LH28F800SGH-L). At 4.5 to 5.5 V V

CC, the access time is 80 ns or 100 ns. At lower

CC voltage, the access time is 85 ns or 100 ns

(3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V).

The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I

CCR current is 1 mA at

5 V V

CC and 3 mA at 2.7 to 3.6 V VCC.

When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (t

PHQV) is

required from RP# switching high until outputs are valid. Likewise, the device has a wake time (t

PHEL)

from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared.

Fig. 1 Memory Map

32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block

7FFFF 78000

77FFF 70000

6FFFF 67FFF

68000 60000

5FFFF 58000

57FFF 50000

4FFFF 48000

47FFF 40000

3FFFF 38000

37FFF 30000

2FFFF 28000

27FFF 20000

1FFFF 18000

17FFF 10000

0FFFF 08000

07FFF 00000

15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

2 PRINCIPLES OF OPERATION

The LH28F800SG-L/SGH-L SmartVoltage flash memories include an on-chip WSM to manage block erase, word write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, word write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations.

Status register and identifier codes can be accessed through the CUI independent of the V

voltage. High voltage on VPP enables successful block erasure, word writing, and lock-bit configuration. All functions associated with altering memory contents — block erase, word write, lockbit configuration, status, and identifier codes — are accessed via the CUI and verified through the status register.

Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, word write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data.

Interface software that initiates and polls progress of block erase, word write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write

data from/to blocks other than that which is suspended. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer may choose to make the V

PP power supply

switchable (available only when memory block erases, word writes, or lock-bit configurations are required) or hardwired to V

PPH1/2/3. The device

accommodates either design practice and encourages optimization of the processor-memory interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase, word write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to V

PP. All write

functions are disabled when V

CC is below the write

lockout voltage V

LKO or when RP# is at VIL. The

device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier codes, or status register independent of the V

voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component : CE#, OE#, WE#,

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

RP# and WP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ

0-DQ15) control and when active drives

the selected memory data onto the I/O bus. WE# must be at V

IH and RP# must be at VIH or VHH.

Fig. 13 illustrates read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ

0-DQ15 are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ

0-DQ15 outputs are placed

in a high-impedance state independent of OE#. If deselected during block erase, word write, or lockbit configuration, the device continues functioning, and consuming active power until the operation completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time t

PHQV is required

after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.

During block erase, word write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time t

PHWL is required

after RP# goes to logic-high (V

IH) before another

command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, word write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

3.5 Read Identifier Codes

The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the permanent lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and permanent lock configuration codes identify locked and unlocked blocks and permanent lock-bit setting.

Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Word Write command requires the command and address of the location to be written. Set Permanent and Block Lock-Bit commands require the command and address within the device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 14 and Fig. 15 illustrate WE# and CE# controlled write operations.

4 COMMAND DEFINITIONS

When the VPP ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing V

PPH1/2/3 on VPP enables

successful block erase, word write and lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.

7FFFF

78004 78003 78002 78001 78000

0FFFF

08004 08003 08002 08001 08000 07FFF

00004 00003 00002 00001 00000

Reserved for

Future Implementation

Block 15 Lock Configuration Code

Block 15

Block 1

Block 0

(Blocks 2 through 14)

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

Reserved for

Future Implementation

Permanent Lock Configuration Code

Block 0 Lock Configuration Code

Device Code

Manufacture Code

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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Table 2 Bus Operations

MODE NOTE RP# CE# OE# WE#

ADDRESS

0-15

RY/BY#

VIHor V

XXD

OUT

Output Disable 3

VIHor V

X X High Z X

Standby 3

VIHor V

XXXXHigh Z X

Deep Power-Down 4 VIL XXXXXHigh Z V

Read Identifier Codes 8

VIHor V

See Fig. 2

NOTE 5)

Write 3, 6, 7, 8

VIHor V

XXDINX

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS". When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

IL or VIH for control pins and addresses, and

PPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for V

PPLK and VPPH1/2/3 voltages.

3. RY/BY# is V

OL when the WSM is executing internal

block erase, word write, or lock-bit configuration algorithms. It is V

OH during when the WSM is not busy,

in block erase suspend mode (with word write inactive), word write suspend mode, or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep powerdown current.

5. See Section 4.2 for read identifier code data.

6. V

IH < RP# < VHH produce spurious results and should

not be attempted.

7. Refer to Table 3 for valid D

IN during a write operation.

8. Don’t use the timing both OE# and WE# are V

IL.

Page 11

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE SECOND BUS CYCLE

REQ’D.

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset 1 Write X FFH Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID Read Status Register 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Block Erase 2 5 Write BA 20H Write BA D0H Word Write 2 5, 6 Write WA

40H or 10H

Write WA WD

Block Erase and

1 5 Write X B0H

Word Write Suspend Block Erase and

1 5 Write X D0H

Word Write Resume Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H Set Permanent Lock-Bit 2 7 Write X 60H Write X F1H Clear Block Lock-Bits 2 8 Write X 60H Write X D0H

Table 3 Command Definitions

(NOTE 9)

NOTES :

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device. IA = Identifier code address : see Fig. 2. BA = Address within the block being erased or locked. WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and permanent lock codes. See Section 4.2 for read identifier code data.

5. If the block is locked and the permanent lock-bit is not set, WP# must be at V

IH or RP# must be at VHH to

enable block erase or word write operations. Attempts to issue a block erase or word write to a locked block while WP# is V

IH or RP# is VHH.

6. Either 40H or 10H is recognized by the WSM as the word write setup.

7. If the permanent lock-bit is set, WP# must be at V

IH or

RP# must be at V

HH to set a block lock-bit. RP# must

be at V

HH to set the permanent lock-bit. If the permanent

lock-bit is set, a block lock-bit cannot be set. Once the permanent lock-bit is set, permanent lock-bit reset is unable.

8. If the permanent lock-bit is set, clear block lock-bits operation is unable. The clear block lock-bits operation simultaneously clears all block lock-bits. If the permanent lock-bit is not set, the Clear Block Lock-Bits command can be done while WP# is V

IH or RP# is VHH.

9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

4.1 Read Array Command

Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, word write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write Suspend command. The Read Array command functions independently of the V

voltage and RP# can be VIH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and permanent lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the V

PP voltage and RP# can be

IH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

NOTES :

1. X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map.

2. Block lock status and permanent lock status are output by DQ

0. DQ1-DQ15 are reserved for future enhancement.

4.3 Read Status Register Command

The status register may be read to determine when a block erase, word write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to V

IH before further reads to update the status

PP voltage. RP#

can be V

IH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V

PP voltage. RP# can

be V

IH or VHH. This command is not functional

during block erase or word write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written,

CODE ADDRESS DATA

Manufacture Code 00000H 00B0H Device Code 00001H 0050H Block Lock Configuration

(NOTE 2)

XX002H

(NOTE 1)

•Unlocked DQ0 = 0

•Locked DQ0 = 1

•

Reserved for future enhancement

DQ1-15

Permanent Lock Configuration

(NOTE 2)

00003H

•Unlocked DQ0 = 0

•Locked DQ0 = 1

•

Reserved for future enhancement

DQ1-15

Page 13

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued.

This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when V

CC =

CC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

this high voltage, block contents are protected against erasure. If block erase is attempted while V

PP ≤ VPPLK, SR.3 and SR.5 will be set to "1".

Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that WP# = V

IH or RP# = VHH. If block erase is

attempted when the corresponding block lock-bit is set and WP# = V

IL and RP# = VIH, SR.1 and SR.5

will be set to "1". Once permanent lock-bit is set, the blocks which have been set block lock-bit are unable to erase forever. Block erase operations with V

IH < RP# < V HH produce spurious results and

should not be attempted.

4.6 Word Write Command

Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the

completion of the word write event by analyzing the RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command.

Reliable word writes can only occur when V

CC =

CC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

this high voltage, memory contents are protected against word writes. If word write is attempted while V

PP ≤ VPPLK, status register bits SR.3 and SR.4 will

be set to "1". Successful word write requires that the corresponding block lock-bit be cleared or, if set, that WP# = V

IH or RP# = VHH. If word write is

attempted when the corresponding block lock-bit is set and WP# = V

IL and RP# = VIH, SR.1 and SR.4

will be set to "1". Once permanent lock-bit is set, the blocks which have been set block lock-bit are unable to write forever. Word write operations with V

IH < RP# < VHH produce spurious results and

should not be attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows block erase interruption to read or word write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to V

OH.

Specification t

WHRH2 defines the block erase

suspend latency.

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word Write Suspend command (see Section 4.8), a word write operation can also be suspended. During a word write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to V

OL.

However, SR.6 will remain "1" to indicate block erase suspend status.

The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V

OL. After the Erase

Resume command is written, the device automatically outputs status register data when read (see Fig. 5). V

PP must remain at VPPH1/2/3

(the same VPP level used for block erase) while block erase is suspended. RP# must also remain at V

IH or VHH (the same RP# level used for block

erase). WP# must also remain at V

IL or VIH (the

same WP# level used for block erase). Block erase cannot resume until word write operations initiated during block erase suspend have completed.

4.8 Word Write Suspend Command

The Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM suspend the word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). RY/BY# will

also transition to V

OH. Specification tWHRH1 defines

the word write suspend latency.

At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word write is suspended are Read Status Register and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the word write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V

OL. After the Word Write Resume command is

written, the device automatically outputs status register data when read (see Fig. 6). V

PP must

remain at V

PPH1/2/3 (the same VPP level used for

word write) while in word write suspend mode. RP# must also remain at V

IH or VHH (the same RP#

level used for word write). WP# must also remain at V

IL or VIH (the same WP# level used for word

write).

4.9 Set Block and Permanent LockBit Commands

The combination of the software command sequence and hardware WP#, RP# pin provides most flexible block lock (write protection) capability. The word write/block erase operation is restricted by the status of block lock-bit, WP# pin, RP# pin and permanent lock-bit. The status of WP# pin, RP# pin and permanent lock-bit restricts the set block bit. When the permanent lock-bit has not been set, and when WP# = V

IH or RP# = V HH, the

block lock bit can be set with the status of the RP# pin. When RP# = V

HH, the permanent lock-bit can

be set with the permanent lock-bit set command. After the permanent lock-bit has been set, the write/erase operation to the block lock-bit can never be accepted. Refer to Table 5 for the hardware and the software write protection.

Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The

Page 15

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Fig. 7). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7.

When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued.

This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when V

CC = VCC1/2/3/4 and VPP =

PPH1/2/3. In the absence of this high voltage, lock-

bit contents are protected against alteration.

A successful set block lock-bit operation requires that the permanent lock-bit be cleared and WP# = V

IH or RP# = VHH. If it is attempted with the

permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations while V

IH < RP# < VHH produce

spurious results and should not be attempted. A successful set permanent lock-bit operation requires that RP# = V

HH. If it is attempted with RP# = VIH,

SR.1 and SR.4 will be set to "1" and the operation will fail. Set permanent lock-bit operations with V

< RP# < VHH produce spurious results and should not be attempted.

4.10 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the permanent lock-bit not set and WP# = V

IH or RP#

= V

HH, block lock-bits can be cleared using the

Clear Block Lock-Bits command. If the permanent lock-bit is set, clear block lock-bits operation is unable. See Table 5 for a summary of hardware and software write protection options.

Clear block lock-bits option is executed by a twocycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Fig. 8). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# pin output or status register bit SR.7.

When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bits error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued.

This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when V

CC =

CC1/2/3/4 and VPP = VPPH1/2/3. In a clear block lock-

bits operation is attempted while V

PP ≤ VPPLK, SR.3

and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bit contents are protected against alteration. A successful clear block lock-bits operation requires that the permanent lockbit is not set and WP# = V

IH or RP# = VHH. If it is

attempted with the permanent lock-bit set or WP# = V

IL and RP# = VIH, SR.1 and SR.5 will be set to "1"

and the operation will fail. A clear block lock-bits operation with V

IH < RP# < VHH produce spurious

results and should not be attempted.

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

If a clear block lock-bits operation is aborted due to V

PP or V CC transition out of valid range or WP# or

RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block

lock-bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit is set, it cannot be cleared.

Table 5 Write Protection Alternatives

OPERATION

PERMANENT

BLOCK

WP# RP# EFFECT

LOCK-BIT

X0X

VIHor VHHBlock Erase and Word Write Enabled

VIHor V

Block Lock-Bit Override. Block Erase and Word Write Enabled

VIH

Block is Locked. Block Erase and Word Write Disabled

1XX

Permanent Lock-Bit is set. Block Erase and Word Write Disabled

VIH

VIHor VHHSet Block Lock-Bit Enabled

Set Block

Set Block Lock-Bit Enabled

Lock-Bit

Set Block Lock-Bit Disabled

Permanent Lock-Bit is set. Set Block Lock-Bit Disabled

Set Permanent

XXX

HH Set Permanent Lock-Bit Enabled

Lock-Bit

VIH Set Permanent Lock-Bit Disabled

VIH

VIHor VHHClear Block Lock-Bits Enabled

Clear Block

Clear Block Lock-Bits Enabled

Lock-Bits

Clear Block Lock-Bits Disabled

Permanent Lock-Bit is set. Clear Block Lock-Bits Disabled

Block Erase

Word Write

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 17 -

Table 6 Status Register Definition

WSMS ESS ECLBS WWSLBS VPPS WWSS DPS R

76543210

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready 0 = Busy

SR.6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended 0 = Block Erase in Progress/Completed

SR.5 =

ERASE AND CLEAR LOCK-BITS STATUS (ECLBS) 1 = Error in Block Erase or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits

SR.4 =

WORD WRITE AND SET LOCK-BIT STATUS (WWSLBS) 1=

Error in Word Write or Set Permanent/Block Lock-Bit 0=

Successful Word Write or Set Permanent/Block Lock-Bit

SR.3 = VPP STATUS (VPPS)

1= V

PP Low Detect, Operation Abort

0= V

PP OK

SR.2 = WORD WRITE SUSPEND STATUS (WWSS)

1 = Word Write Suspended 0 = Word Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Permanent Lock-Bit, Block Lock-Bit and/or

WP#/RP# Lock Detected, Operation Abort

0 = Unlock

SR.0 =

RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES :

Check RY/BY# or SR.7 to determine block erase, word write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7 =

"0".

If both SR.5 and SR.4 are

"1"s after a block erase or lock-bit

configuration attempt, an improper command sequence was entered.

SR.3 does not provide a continuous indication of V

PP level.

The WSM interrogates and indicates the V

PP level only after

Block Erase, Word Write, Set Block/Permanent Lock-Bit, or Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when V

PP ≠

PPH1/2/3.

SR.1 does not provide a continuous indication of Permanent and block lock-bit values. The WSM interrogates the Permanent lock-bit, block lock-bit, WP# and RP# only after Block Erase, Word Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set, and/or WP# is not V

IH, RP# is not VHH. Reading the block

lock and permanent lock configuration codes after writing the Read Identifier Codes command indicates permanent and block lock-bit status.

SR.0 is reserved for future use and should be masked out when polling the status register.

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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Block Erase

Complete

Start

Write 20H,

Block Address

Write D0H,

Block Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent block erasures. Full status check can be done after each block erase or after

a sequence of block erasures. Write FFH after the last block erase operation to place device

in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Erase Setup

COMMENTS

Data = 20H Addr = Within Block to be Erased

Data = D0H Addr = Within Block to be Erased

Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

PP Range Error

SR.1 =

Device Protect Error

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1 1 = Device Protect Detect RP# = V

IH, Block Lock-Bit is Set

Only required for systems implementing lock-bit configuration

Check SR.5 1 = Block Erase Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked.

If error is detected, clear the status register before attempting retry or other error recovery.

Suspend

Block Erase

Yes

Suspend Block

Erase Loop

Erase

Confirm

Block Erase

Successful

SR.4, 5 =

Command Sequence

Error

SR.5 =

Block Erase

Error

Standby

Check SR.3 1 = V

PP Error Detect

Standby

Check SR.4, 5 Both 1 = Command Sequence Error

Fig. 3 Automated Block Erase Flowchart

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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Word Write

Complete

Start

Write 40H,

Address

Write Word

Data and Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent word writes. SR full status check can be done after each word write or after

a sequence of word writes. Write FFH after the last word write operation to place device

in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Setup

Word Write

COMMENTS

Data = 40H Addr = Location to be Written

Data = Data to be Written Addr = Location to be Written

Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

PP Range Error

SR.1 =

Device Protect Error

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1 1 = Device Protect Detect RP# = V

IH, Block Lock-Bit is Set

Only required for systems implementing lock-bit configuration

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked.

If error is detected, clear the status register before attempting retry or other error recovery.

Suspend

Word Write

Yes

Suspend Word

Write Loop

Word Write

Word Write Successful

SR.4 =

Word Write Error

Standby

Check SR.3 1 = V

PP Error Detect

Standby

Check SR.4 1 = Data Write Error

Fig. 4 Automated Word Write Flowchart

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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Block Erase

Resumed

Start

Write B0H

Read

Status Register

SR.7 =

Word Write

BUS

OPERATION

Write

Read

Standby

COMMAND

Erase

Suspend

COMMENTS

Data = B0H Addr = X

Status Register Data Addr = X

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed

Erase

Resume

SR.6 =

Write D0H

Done?

Block Erase

Completed

Write FFH

Read

Array Data

Yes

Write

Data = D0H Addr = X

Read

or Word

Write?

Read

Read Array Data Word Write Loop

Fig. 5 Block Erase Suspend/Resume Flowchart

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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Word Write Resumed

Start

Write B0H

Read

Status Register

SR.7 =

Write FFH

BUS

OPERATION

Write

Read

Standby

COMMAND

Word Write

Suspend

COMMENTS

Data = B0H Addr = X

Status Register Data Addr = X

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.2 1 = Word Write Suspended 0 = Word Write Completed

Read Array

SR.2 =

Read

Array Data

Done

Reading

Write D0H

Word Write

Completed

Write FFH

Read

Array Data

Yes

Write

Read

Write

Word Write

Resume

Data = FFH Addr = X

Read array locations other than that being written.

Data = D0H Addr = X

Fig. 6 Word Write Suspend/Resume Flowchart

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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Set Lock-Bit

Complete

Start

Write 60H,

Block/Device Address

Write 01H/F1H,

Block/Device Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set

operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device

in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Set

Block/Permanent

Lock-Bit

Setup

COMMENTS

Data = 60H Addr = Block Address (Block),

Device Address

(Parmanent)

Data = 01H (Block),

F1H (Parmanent)

Addr = Block Address (Block),

Device Address (

Parmanent

)

Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

PP Range Error

SR.1 =

Device Protect Error

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1 1 = Device Protect Detect RP# = V

(Set Permanent Lock-Bit Operation)

WP# = V

IL and RP# = VIH or

Permanent Lock-Bit is Set

(Set Block Lock-Bit Operation)

Check SR.4 1 = Set Lock-Bit Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked.

If error is detected, clear the status register before attempting retry or other error recovery.

Set

Block or Permanent

Lock-Bit Confirm

Set Lock-Bit

Successful

SR.4, 5 =

Command Sequence

Error

SR.4 =

Set Lock-Bit

Error

Standby

Check SR.3 1 = V

PP Error Detect

Standby

Check SR.4, 5 Both 1 = Command Sequence Error

Fig. 7 Set Block and Permanent Lock-Bit Flowchart

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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Clear Block Lock-Bits

Complete

Start

Write 60H

Write D0H

Read

Status Register

SR.7 =

Full Status

Check if Desired

Write FFH after the last clear block lock-bits operation to place device in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Clear Block

Lock-Bits

Setup

COMMENTS

Data = 60H Addr = X

Data = D0H Addr = X

Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

PP Range Error

SR.1 =

Device Protect Error

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1 1 = Device Protect Detect WP# = V

IL and RP# = VIH or

Permanent Lock-Bit is Set

Check SR.5 1 = Clear Block Lock-Bits Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command.

If error is detected, clear the status register before attempting retry or other error recovery.

Clear Block

Lock-Bits

Confirm

Clear Block Lock-Bits

Successful

SR.4, 5 =

Command Sequence

Error

SR.5 =

Clear Block Lock-Bits

Error

Standby

Check SR.3 1 = V

PP Error Detect

Standby

Check SR.4, 5 Both 1 = Command Sequence Error

Fig. 8 Clear Block Lock-Bits Flowchart

Page 24

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Threeline control provides for :

a. Lowest possible memory power consumption. b. Complete assurance that data bus contention

will not occur.

To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.

5.2 RY/BY# and Block Erase, Word Write, and Lock-Bit Configuration Polling

RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, word write and lock-bit configuration completion. It transitions low after block erase, word write, or lockbit configuration commands and returns to V

when the WSM has finished executing the internal algorithm.

RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also V

OH when the device is in

block erase suspend (with word write inactive), word write suspend or deep power-down modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current

issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its V

CC and GND and between its VPP

and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply connection between V

and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.

5.4 VPP Trace on Printed Circuit Boards

Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the V

PP power supply

trace. The V

PP pin supplies the memory cell current

for word writing and block erasing. Use similar trace widths and layout considerations given to the V

power bus. Adequate VPP supply traces and decoupling will decrease V

PP voltage spikes and

overshoots.

5.5 VCC, VPP, RP# Transitions

Block erase, word write and lock-bit configuration are not guaranteed if V

PP falls outside of a valid

PPH1/2/3 range, VCC falls outside of a valid

CC1/2/3/4 range, or RP# ≠ VIH or VHH. If VPP error

is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V

IL during

block erase, word write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be

- 24 -

Page 25

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

repeated after normal operation is restored. Device power-off or RP# transitions to V

IL clear the status

The CUI latches commands issued by system software and is not altered by V

PP or CE#

transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep powerdown or after V

CC transitions below VLKO.

After block erase, word write, or lock-bit configuration, even after V

PP transitions down to

PPLK, the CUI must be placed in read array mode

via the Read Array command if subsequent access to the memory array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against accidental block erasure, word writing, or lock-bit configuration during power transitions. Upon powerup, the device is indifferent as to which power supply (V

PP or VCC) powers-up first. Internal

circuitry resets the CUI to read array mode at power-up.

A system designer must guard against spurious writes for V

CC voltages above VLKO when VPP is

active. Since both WE# and CE# must be low for a command write, driving either to V

IH will inhibit

writes. The CUI’s two-step command sequence architecture provides added level of protection against data alteration.

In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = V

IL regardless of its control inputs

state.

5.7 Power Consumption

When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed.

In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solidstate storage can consume negligible power by lowering RP# to V

IL standby or sleep modes. If

access is again needed, the devices can be read following the t

PHQV and tPHWL wake-up cycles

required after RP# is first raised to V

IH. See Section

6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and Fig. 13, Fig. 14 and Fig. 15 for more information.

Page 26

- 26 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

∗

Operating Temperature

• LH28F800SG-L During Read, Block Erase, Word Write, and Lock-Bit Configuration

........

0 to +70°C

(NOTE 1)

Temperature under Bias

............

– 10 to +80°C

• LH28F800SGH-L During Read, Block Erase, Word Write, and Lock-Bit Configuration

...

– 40 to +85°C

(NOTE 2)

Temperature under Bias

.............

– 40 to +85°C

Storage Temperature

........................

– 65 to +125°C

Voltage On Any Pin

(except VCC, VPP, and RP#)

....

– 2.0 to +7.0 V

(NOTE 3)

VCC Supply Voltage

.................

– 2.0 to +7.0 V

(NOTE 3)

VPP Update Voltage during

Block Erase, Word Write, and Lock-Bit Configuration

....

– 2.0 to +14.0 V

(NOTE 3, 4)

RP# Voltage with Respect to

GND during Lock-Bit Configuration Operations

– 2.0 to +14.0 V

(NOTE 3, 4)

Output Short Circuit Current

..............

100 mA

(NOTE 5)

∗

WARNING : Stressing the device beyond the

Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.

NOTES :

1. Operating temperature is for commercial product defined

by this specification.

2. Operating temperature is for extended temperature

product defined by this specification.

3. All specified voltages are with respect to GND. Minimum

DC voltage is – 0.5 V on input/output pins and – 0.2 V on V

CC and VPP pins. During transitions, this level may

undershoot to – 2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins and V

CC is VCC+0.5 V

which, during transitions, may overshoot to V

CC+2.0 V

for periods < 20 ns.

4. Maximum DC voltage on V

PP and RP# may overshoot

to +14.0 V for periods < 20 ns.

5. Output shorted for no more than one second. No more

than one output shorted at a time.

NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design.

SYMBOL

PARAMETER NOTE MIN. MAX. UNIT VERSIONS

TA Operating Temperature 1

+70

C LH28F800SG-L

–40

+85

˚C LH28F800SGH-L VCC1 VCC Supply Voltage (2.7 to 3.0 V) 2.7 3.0 V VCC2 VCC Supply Voltage (3.3±0.3 V) 3.0 3.6 V VCC3 VCC Supply Voltage (5.0±0.25 V) 4.75 5.25 V

LH28F800SG-L70/SGH-L70

VCC4 VCC Supply Voltage (5.0±0.5 V) 4.50 5.50 V

6.2 Operating Conditions

NOTE :

1. Test condition : Ambient temperature

Page 27

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 27 -

NOTE :

1. Sampled, not 100% tested.

SYMBOL PARAMETER TYP. MAX. UNIT CONDITION

CIN Input Capacitance 7 10 pF VIN = 0.0 V COUT Output Capacitance 9 12 pF VOUT = 0.0 V

6.2.1 CAPACITANCE

(NOTE 1)

TA = +25˚C, f = 1 MHz

6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

TEST POINTSINPUT OUTPUT

1.35

2.7

0.0

Fig. 9 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.0 V

1.5

3.0

0.0

TEST POINTSINPUT OUTPUT

Fig. 10 Transient Input/Output Reference Waveform for VCC = 3.3±0.3 V and

VCC = 5.0±0.25 V (High Speed Testing Configuration)

2.0

0.8

2.0

0.8

2.4

0.45

TEST POINTSINPUT OUTPUT

Fig. 11 Transient Input/Output Reference Waveform for

CC = 5.0±0.5 V (Standard Testing Configuration)

AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.

AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.

AC test inputs are driven at V

OH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing

begins at V

IH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to

90%) < 10 ns.

Page 28

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 28 -

Fig. 12 Transient Equivalent Testing

Load Circuit

DEVICE

UNDER

TEST

L Includes Jig

Capacitance

RL = 3.3 kΩ

OUT

1.3 V

1N914

TEST CONFIGURATION CL (pF)

VCC = 3.3±0.3 V, 2.7 to 3.0 V 50 VCC = 5.0±0.25 V

(NOTE 1)

CC = 5.0±0.5 V 100

Test Configuration Capacitance Loading Value

NOTE :

1. Applied to high-speed products, LH28F800SG-L70 and LH28F800SGH-L70.

Page 29

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 29 -

6.2.3 DC CHARACTERISTICS

SYMBOL

PARAMETER NOTE

VCC= 2.7 to 3.6 V VCC= 5.0±0.5 V

UNIT

TEST

TYP. MAX. TYP. MAX.

CONDITIONS

LI Input Load Current 1 ±0.5 ±1 µA

CC = VCC Max.

VIN = VCC or GND

LO Output Leakage Current 1 ±0.5 ±10 µA

CC = VCC Max.

VOUT = VCC or GND CMOS Inputs

100 100 µA V

CC = VCC Max.

ICCS VCC Standby Current 1, 3, 6

CE# = RP# = V

CC±0.2 V

TTL Inputs

22mAV

CC = VCC Max.

CE# = RP# = VIH

ICCD

VCC Deep Power-Down

11216µA

RP# = GND±0.2 V

Current IOUT (RY/BY#) = 0 mA

CMOS Inputs V

CC = VCC Max.

25 50 mA

CE# = GND f = 5 MHz (3.3 V, 2.7 V),

8 MHz (5 V)

ICCR VCC Read Current 1, 5, 6

OUT = 0 mA

TTL Inputs V

CC = VCC Max.

30 65 mA

CE# = GND f = 5 MHz (3.3 V, 2.7 V),

8 MHz (5 V)

IOUT = 0 mA

VCC Word Write or

17 — — mA V

PP = 2.7 to 3.6 V

ICCW

Set Lock-Bit Current

1, 7 17 35 mA V

PP = 5.0±0.5 V

12 30 mA VPP = 12.0±0.6 V

VCC Block Erase or 17 — — mA VPP = 2.7 to 3.6 V

ICCE Clear Block Lock-Bits 1, 7 17 30 mA VPP = 5.0±0.5 V

Current 12 25 mA VPP = 12.0±0.6 V

CCWS VCC Word Write or Block

1, 2 6 10 mA CE# = V

ICCES Erase Suspend Current IPPS

VPPStandby or Read Current

±15 ±15 µA V

PP ≤ VCC

IPPR 200 200 µA VPP > VCC IPPD

VPP Deep Power-Down

1 5 5 µA RP# = GND±0.2 V

Current VPP Word Write or

80 — — mA V

PP = 2.7 to 3.6 V

IPPW

Set Lock-Bit Current

1, 7 80 80 mA V

PP = 5.0±0.5 V

30 30 mA VPP = 12.0±0.6 V

VPP Block Erase or

40 — — mA V

PP = 2.7 to 3.6 V

IPPE

Clear Block Lock-Bits

1, 7 40 40 mA V

PP = 5.0±0.5 V

Current 30 30 mA VPP = 12.0±0.6 V

PPWS VPP Word Write or Block

1 200 200 µA V

PP = VPPH1/2/3

IPPES Erase Suspend Current

Page 30

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 30 -

6.2.3 DC CHARACTERISTICS (contd.)

SYMBOL

PARAMETER NOTE

VCC= 2.7 to 3.6 V

VCC = 5.0±0.5 V

UNIT

TEST

MIN. MAX. MIN. MAX.

CONDITIONS

VIL Input Low Voltage 7 – 0.5 0.8 – 0.5 0.8 V VIH Input High Voltage 7 2.0

2.0

+0.5 +0.5

CC = VCC Min.

OL Output Low Voltage 3, 7 0.4 0.45 V IOL = 5.8 mA (VCC = 5 V),

IOL= 2.0 mA (VCC= 3.3 V, 2.7 V)

Output High Voltage

CC = VCC Min.

OH1

(TTL)

3, 7 2.4 2.4 V

IOH= –2.5 mA (VCC= 5 V), IOH= –2.0 mA (VCC= 3.3 V, 2.7 V)

0.85 0.85

VCC = VCC Min.

VOH2

Output High Voltage

3, 7

CC VCC IOH = –2.5 µA

(CMOS)

CC VCC

CC = VCC Min.

– 0.4 – 0.4 IOH = –100 µA

VPPLK

VPP Lockout Voltage during

4, 7 1.5 1.5 V

Normal Operations V

PP Voltage during

PPH1 Word Write, Block Erase 2.7 3.6 — — V

or Lock-Bit Operations V

PP Voltage during

PPH2 Word Write, Block Erase 4.5 5.5 4.5 5.5 V

or Lock-Bit Operations V

PP Voltage during

PPH3 Word Write, Block Erase 11.4 12.6 11.4 12.6 V

or Lock-Bit Operations

VLKO VCC Lockout Voltage 2.0 2.0 V VHH RP# Unlock Voltage 8 11.4 12.6 11.4 12.6 V

Set permanent lock-bit Override block lock-bit

NOTES :

1. All currents are in RMS unless otherwise noted. Typical values at nominal V

CC voltage and TA = +25°C. These

currents are valid for all product versions (packages and speeds).

2. I

CCWS and ICCES are specified with the device de-

selected. If reading or word writing in erase suspend mode, the device’s current draw is the sum of I

CCWS or

CCES and ICCR or ICCW, respectively.

3. Includes RY/BY#.

4. Block erases, word writes, and lock-bit configurations are inhibited when V

PP ≤ VPPLK, and not guaranteed in the

range between V

PPLK (max.) and VPPH1 (min.), between

PPH1 (max.) and VPPH2 (min.), between VPPH2 (max.)

and V

PPH3 (min.), and above VPPH3 (max.).

5. Automatic Power Saving (APS) reduces typical I

CCR to

1 mA at 5 V V

CC and 3 mA at 2.7 to 3.6 V VCC in static

operation.

6. CMOS inputs are either V

CC±0.2 V or GND±0.2 V. TTL

inputs are either V

IL or VIH.

7. Sampled, not 100% tested.

8. Permanent lock-bit set operations are inhibited when RP# = V

IH. Block lock-bit configuration operations are

inhibited when the permanent lock-bit is set or RP# = V

IH and WP# = VIL. Block erases and word writes are

inhibited when the corresponding block lock-bit is set and RP# = V

IH and WP# = VIL or the permanent lock-bit

is set. Block erase, word write, and lock-bit configuration operations are not guaranteed with V

IH < RP# < VHH

and should not be attempted.

Page 31

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 31 -

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS

(NOTE 1)

• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C

VERSIONS

LH28F800SG-L70 LH28F800SG-L10

LH28F800SGH-L70 LH28F800SGH-L10

UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 100 120 ns tAVQV Address to Output Delay 100 120 ns tELQV CE# to Output Delay 2 100 120 ns tPHQV RP# High to Output Delay 600 600 ns tGLQV OE# to Output Delay 2 45 50 ns tELQX CE# to Output in Low Z 3 0 0 ns tEHQZ CE# High to Output in High Z 3 45 55 ns tGLQX OE# to Output in Low Z 3 0 0 ns tGHQZ OE# High to Output in High Z 3 20 25 ns

Output Hold from Address, CE# or

30 0 ns

OE# Change, Whichever Occurs First

VERSIONS

LH28F800SG-L70 LH28F800SG-L10

LH28F800SGH-L70 LH28F800SGH-L10

UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 85 100 ns tAVQV Address to Output Delay 85 100 ns tELQV CE# to Output Delay 2 85 100 ns tPHQV RP# High to Output Delay 600 600 ns tGLQV OE# to Output Delay 2 40 45 ns tELQX CE# to Output in Low Z 3 0 0 ns tEHQZ CE# High to Output in High Z 3 40 45 ns tGLQX OE# to Output in Low Z 3 0 0 ns tGHQZ OE# High to Output in High Z 3 15 20 ns

Output Hold from Address, CE# or

30 0 ns

OE# Change, Whichever Occurs First

NOTES :

1. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate.

2. OE# may be delayed up to t

ELQV-tGLQV after the falling edge of CE# without impact on tELQV.

3. Sampled, not 100% tested.

•VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C

Page 32

- 32 -

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 70 80 100 ns tAVQV Address to Output Delay 70 80 100 ns tELQV CE# to Output Delay 2 70 80 100 ns tPHQV RP# High to Output Delay 400 400 400 ns tGLQV OE# to Output Delay 2 40 45 50 ns tELQX CE# to Output in Low Z 3 0 0 0 ns tEHQZ CE# High to Output in High Z 3 55 55 55 ns tGLQX OE# to Output in Low Z 3 0 0 0 ns tGHQZ OE# High to Output in High Z 3 10 10 15 ns

Output Hold from Address,

OH CE# or OE# Change, 3 0 0 0 ns

Whichever Occurs First

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

VERSIONS

VCC±0.25 V

VCC±0.5 V

(NOTE 4)

LH28F800SG-L70

LH28F800SGH-L70

(NOTE 5)

LH28F800SG-L10

LH28F800SGH-L10

(NOTE 5)

LH28F800SG-L70

LH28F800SGH-L70

UNIT

NOTES :

1. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate.

2. OE# may be delayed up to t

ELQV-tGLQV after the falling

edge of CE# without impact on t

ELQV.

3. Sampled, not 100% tested.

4. See Fig. 10 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing

characteristics.

5. See Fig. 11 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing

characteristics.

6.2.4 AC CHARACTERISTICS - READ ONLY OPERATIONS (contd.)

(NOTE 1)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C

Page 33

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 33 -

Standby

Device

Address Selection

Data Valid

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

(DQ

- DQ15)

RP# (P)

High Z High Z

AVAV

EHQZ

GHQZ

GLQV

ELQV

GLQX

ELQX

AVQV

PHQV

Valid Output

Address Stable

Fig. 13 AC Waveform for Read Operations

Page 34

- 34 -

VERSIONS

LH28F800SG-L70 LH28F800SG-L10

LH28F800SGH-L70 LH28F800SGH-L10

UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 85 100 ns tPHWL RP# High Recovery to WE# Going Low 2 1 1 µs tELWL CE# Setup to WE# Going Low 10 10 ns tWLWH WE# Pulse Width 50 50 ns tPHHWH RP# VHH Setup to WE# Going High 2 100 100 ns tVPWH VPP Setup to WE# Going High 2 100 100 ns tAVWH Address Setup to WE# Going High 3 50 50 ns tDVWH Data Setup to WE# Going High 3 50 50 ns tWHDX Data Hold from WE# High 5 5 ns tWHAX Address Hold from WE# High 5 5 ns tWHEH CE# Hold from WE# High 10 10 ns tWHWL WE# Pulse Width High 30 30 ns tWHRL WE# High to RY/BY# Going Low 100 100 ns tWHGL Write Recovery before Read 0 0 ns tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns t

QVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS

(NOTE 1)

• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C

VERSIONS

LH28F800SG-L70 LH28F800SG-L10

LH28F800SGH-L70 LH28F800SGH-L10

UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 100 120 ns tPHWL RP# High Recovery to WE# Going Low 2 1 1 µs tELWL CE# Setup to WE# Going Low 10 10 ns tWLWH WE# Pulse Width 50 50 ns tPHHWH RP# VHH Setup to WE# Going High 2 100 100 ns tVPWH VPP Setup to WE# Going High 2 100 100 ns tAVWH Address Setup to WE# Going High 3 50 50 ns tDVWH Data Setup to WE# Going High 3 50 50 ns tWHDX Data Hold from WE# High 5 5 ns tWHAX Address Hold from WE# High 5 5 ns tWHEH CE# Hold from WE# High 10 10 ns tWHWL WE# Pulse Width High 30 30 ns tWHRL WE# High to RY/BY# Going Low 100 100 ns tWHGL Write Recovery before Read 0 0 ns tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns t

QVPH RP# VHH Hold from Valid SRD, RY/BY#

High 2, 4 0 0 ns

•VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C

NOTES :

1. Read timing characteristics during block erase, word write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

IN and DIN for block erase,

word write, or lock-bit configuration.

4. V

PP should be held at VPPH1/2/3 (and if necessary RP#

should be held at V

HH) until determination of block erase,

word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

Page 35

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 35 -

NOTES :

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

IN and DIN for block erase,

word write, or lock-bit configuration.

4. V

PP should be held at VPPH1/2/3 (and if necessary RP#

should be held at V

HH) until determination of block erase,

word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

5. See Fig. 10 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing

characteristics.

6. See Fig. 11 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing

characteristics.

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

AVAV

Write Cycle Time 70 80 100 ns

PHWL

RP# High Recovery to WE#

2111µs

Going Low

ELWL

CE# Setup to WE# Going Low 10 10 10 ns

WLWH

WE# Pulse Width 40 40 40 ns

PHHWH

RP# VHHSetup to WE# Going High

2 100 100 100 ns

VPWH

VPPSetup to WE# Going High 2 100 100 100 ns

AVWH

Address Setup to WE# Going High

3404040ns

DVWH

Data Setup to WE# Going High 3 40 40 40 ns

WHDX

Data Hold from WE# High 5 5 5 ns

WHAX

Address Hold from WE# High 5 5 5 ns

WHEH

CE# Hold from WE# High 10 10 10 ns

WHWL

WE# Pulse Width High 30 30 30 ns

WHRL

WE# High to RY/BY# Going Low

90 90 90 ns

WHGL

Write Recovery before Read 0 0 0 ns

QVVL

VPPHold from Valid SRD,

2, 4 0 0 0 ns

RY/BY# High

QVPH

RP# VHHHold from Valid SRD,

2, 4 0 0 0 ns

RY/BY# High

VERSIONS

VCC±0.25 V

VCC±0.5 V

(NOTE 5)

LH28F800SG-L70

LH28F800SGH-L70

(NOTE 6)

LH28F800SG-L10

LH28F800SGH-L10

(NOTE 6)

LH28F800SG-L70

LH28F800SGH-L70

UNIT

6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (contd.)

(NOTE 1)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C

Page 36

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 36 -

VPP (V)

VIH

VOH

VOL

VIL

VPPH1/2/3

VPPLK

RP# (P)

WP# (S)

RY/BY# (R)

DATA (D/Q)

WE# (W)

OE# (G)

CE# (E)

ADDRESSES (A)

AVAV tAVWH

tELWL

tWHGL

tWHQV1/2/3/4

tWHWL

tWHDX

DIN

AIN AIN

DIN

High Z

PHWL

tWHRL

Valid SRD

tVPWH

tWHEH

VIL

VIH

VIL

VIH

tQVSLtSHWH

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

tDVWH

tWLWH

tWHAX

tQVVL

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Fig. 14 AC Waveform for WE#-Controlled Write Operations

Page 37

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 37 -

6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS

(NOTE 1)

•VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or – 40 to +85˚C

•V

CC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C

VERSIONS

LH28F800SG-L70 LH28F800SG-L10

LH28F

800SG

H-L70 LH28F

800SG

H-L10 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 85 100 ns tPHEL RP# High Recovery to CE# Going Low 2 1 1 µs tWLEL WE# Setup to CE# Going Low 0 0 ns tELEH CE# Pulse Width 70 70 ns tPHHEH RP# VHH Setup to CE# Going High 2 100 100 ns tVPEH VPP Setup to CE# Going High 2 100 100 ns tAVEH Address Setup to CE# Going High 3 50 50 ns tDVEH Data Setup to CE# Going High 3 50 50 ns tEHDX Data Hold from CE# High 5 5 ns tEHAX Address Hold from CE# High 5 5 ns tEHWH WE# Hold from CE# High 0 0 ns tEHEL CE# Pulse Width High 25 25 ns tEHRL CE# High to RY/BY# Going Low 100 100 ns tEHGL Write Recovery before Read 0 0 ns tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns t

QVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

VERSIONS

LH28F800SG-L70 LH28F800SG-L10

LH28F

800SG

H-L70 LH28F

800SG

H-L10 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 100 120 ns tPHEL RP# High Recovery to CE# Going Low 2 1 1 µs tWLEL WE# Setup to CE# Going Low 0 0 ns tELEH CE# Pulse Width 70 70 ns tPHHEH RP# VHH Setup to CE# Going High 2 100 100 ns tVPEH VPP Setup to CE# Going High 2 100 100 ns tAVEH Address Setup to CE# Going High 3 50 50 ns tDVEH Data Setup to CE# Going High 3 50 50 ns tEHDX Data Hold from CE# High 5 5 ns tEHAX Address Hold from CE# High 5 5 ns tEHWH WE# Hold from CE# High 0 0 ns tEHEL CE# Pulse Width High 25 25 ns tEHRL CE# High to RY/BY# Going Low 100 100 ns tEHGL Write Recovery before Read 0 0 ns tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns t

QVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

NOTES :

1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

IN and DIN for block erase,

word write, or lock-bit configuration.

4. V

PP should be held at VPPH1/2/3 (and if necessary RP#

should be held at V

HH) until determination of block erase,

word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

Page 38

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 38 -

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX.

AVAV

Write Cycle Time 70 80 100 ns

PHEL

RP# High Recovery to CE#

2111µs

Going Low

WLEL

WE# Setup to CE# Going Low 0 0 0 ns

ELEH

CE# Pulse Width 50 50 50 ns

PHHEH

RP# VHHSetup to CE# Going High

2 100 100 100 ns

VPEH

VPP Setup to CE# Going High 2 100 100 100 ns

AVEH

Address Setup to CE# Going High

3404040ns

DVEH

Data Setup to CE# Going High 3 40 40 40 ns

EHDX

Data Hold from CE# High 5 5 5 ns

EHAX

Address Hold from CE# High 5 5 5 ns

EHWH

WE# Hold from CE# High 0 0 0 ns

EHEL

CE# Pulse Width High 25 25 25 ns

EHRL

CE# High to RY/BY# Going Low 90 90 90 ns

EHGL

Write Recovery before Read 0 0 0 ns

QVVL

VPP Hold from Valid SRD,

2, 4 0 0 0 ns

RY/BY# High

QVPH

RP# VHH Hold from Valid SRD,

2, 4 0 0 0 ns

RY/BY# High

VERSIONS

VCC±0.25 V

VCC±0.5 V

(NOTE 5)

LH28F800SG-L70

LH28F800SGH-L70

(NOTE 6)

LH28F800SG-L10

LH28F800SGH-L10

(NOTE 6)

LH28F800SG-L70

LH28F800SGH-L70

UNIT

NOTES :

1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

IN and DIN for block erase,

word write, or lock-bit configuration.

4. V

PP should be held at VPPH1/2/3 (and if necessary RP#

should be held at V

HH) until determination of block erase,

word write, or lock-bit configuration success (SR.1/3/4/5 = 0).

5. See Fig. 10 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing

characteristics.

6. See Fig. 11 "Transient Input/Output Reference

Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing

characteristics.

6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS (contd.)

(NOTE 1)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C

Page 39

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 39 -

VPP (V)

VIH

VOH

VOL

VIL

VPPH1/2/3

VPPLK

RP# (P)

WP# (S)

RY/BY# (R)

DATA (D/Q)

CE# (E)

OE# (G)

WE# (W)

ADDRESSES (A)

AVAV tAVEH

tWLEL

tWHGL

tEHQV1/2/3/4

tEHEL

tEHDX

DIN

AIN AIN

DIN

High Z

PHEL

tEHRL

Valid SRD

tVPEH

tEHWH

VIL

VIH

VIL

VIH

tQVSLtSHEH

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

tDVEH

tELEH

tEHAX

tQVVL

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Fig. 15 AC Waveform for CE#-Controlled Write Operations

Page 40

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 40 -

6.2.7 RESET OPERATIONS

VIH

VOH

VOL

VIL

RY/BY# (R)

(A) Reset During Read Array Mode

(B) Reset During Block Erase, Word Write, or Lock-Bit Configuration

CC Rising Timing

PLPH

RP# (P)

VIH

VOH

VOL

VIL

RY/BY# (R)

PLRH

tPLPH

RP# (P)

VIH

2.7 V/3.3 V/5 V

VIL

VCC

t235VPH

RP# (P)

Fig. 16 AC Waveform for Reset Operation

Reset AC Specifications

(NOTE 1)

NOTES :

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, word write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns.

3. A reset time, t

PHQV, is required from the latter of RY/BY#

or RP# going high until outputs are valid.

4. When the device power-up, holding RP#-low minimum 100 ns is required after V

CC has been in predefined

range and also has been in stable there.

VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V

SYMBOL

PARAMETER NOTE

MIN. MAX. MIN. MAX.

UNIT

PLPH

RP# Pulse Low Time (If RP# is tied to VCC,

100 100 ns

this specification is not applicable)

PLRH

RP# Low to Reset during Block Erase,

2, 3

12 µs

Word Write or Lock-Bit Configuration

28 (2.7 V VCC)

VCC 2.7 V to RP# High

t235VPH VCC 3.0 V to RP# High 4 100 100 ns

CC 4.5 V to RP# High

Page 41

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 41 -

6.2.8

BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE

(NOTE 3, 4)

•VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C

•V

CC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C

NOTES :

1. Typical values measured at TA = +25˚C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Sampled, not 100% tested.

VPP = 3.3±0.3 V VPP = 5.0±0.5 V VPP = 12.0±0.6 V

SYMBOL

PARAMETER NOTE

MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX.

UNIT

tWHQV1

Word Write Time 2 35 45 14 20 11 µs

tEHQV1

Block Write Time 2 1.2 1.5 0.5 0.7 0.4 s

WHQV2

Block Erase Time 2 2.1 1.4 1.3 s

tEHQV2 tWHQV3

Set Lock-Bit Time 2 31 20 17.4 µs

tEHQV3 tWHQV4 Clear Block Lock-Bits

2 2.7 1.8 1.6 s

tEHQV4 Time tWHRH1 Word Write Suspend

9 7.5 7.5 µs

tEHRH1 Latency Time to Read t

WHRH2

Erase Suspend Latency

24.3 14.4 14.4 µs

EHRH2

Time to Read

VPP = 2.7 to 3.0 V VPP = 5.0±0.5 V VPP = 12.0±0.6 V

SYMBOL

PARAMETER NOTE

MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX.

UNIT

WHQV1

Word Write Time 2 49 63 20 28 15.4 µs

tEHQV1

Block Write Time 2 1.7 2.1 0.7 1.0 0.56 s

tWHQV2

Block Erase Time 2 3.0 2.0 1.9 s

tEHQV2 tWHQV3

Set Lock-Bit Time 2 44 28 24.4 µs

tEHQV3 tWHQV4 Clear Block Lock-Bits

2 3.8 2.6 2.3 s

tEHQV4 Time t

WHRH1 Word Write Suspend

12.6 10.5 10.5 µs

tEHRH1 Latency Time to Read t

WHRH2

Erase Suspend Latency

34.1 20.2 20.2 µs

EHRH2

Time to Read

Page 42

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 42 -

VPP = 5.0±0.5 V VPP = 12.0±0.6 V

SYMBOL

PARAMETER NOTE

MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX.

UNIT

WHQV1

Word Write Time 2 10 14 7.5 µs

EHQV1

Block Write Time 2 0.4 0.5 0.25 s

WHQV2

Block Erase Time 2 1.3 1.2 s

EHQV2

WHQV3

Set Lock-Bit Time 2 18 15 µs

EHQV3

WHQV4

Clear Block Lock-Bits Time 2 1.6 1.5 s

EHQV4

WHRH1

Word Write Suspend Latency Time to Read 7.5 6 µs

EHRH1

WHRH2

Erase Suspend Latency Time to Read 14.4 14.4 µs

EHRH2

NOTES :

1. Typical values measured at TA = +25˚C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Sampled, not 100% tested.

6.2.8

BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (contd.)

(NOTE 3, 4)

•VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C

Page 43

7 ORDERING INFORMATION

LH28F800SG

(H)

E-L70

Device Density 800 = 8 M-bit

Access Speed (ns) 70 : 70 ns (5.0±0.25 V), 80 ns (5.0±0.5 V),

85 ns (3.3±0.3 V), 100 ns (2.7 to 3.0 V)

10 : 100 ns (5.0±0.5 V), 100 ns (3.3±0.3 V),

120 ns (2.7 to 3.0 V)

Package E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend B = 48-ball CSP (FBGA048-P-0808)

Architecture S = Symmetrical Block

Power Supply Type G = SmartVoltage Technology

Operating Temperature

Blank = 0 to +70°C

H = –40 to +85°C

Product line designator for all SHARP Flash products

VALID OPERATIONAL COMBINATIONS

= 2.7 to 3.0 V VCC= 3.3±0.3 V VCC= 5.0±0.5 V VCC= 5.0±0.25 V

OPTION ORDER CODE

50 pF load, 50 pF load, 100 pF load, 30 pF load,

1.35 V I/O Levels 1.5 V I/O Levels TTL I/O Levels 1.5 V I/O Levels

LH28F800SGXX-L70

100 ns 85 ns 80 ns 70 ns

LH28F800SGXX-L10

120 ns 100 ns 100 ns

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 43 -

Page 44

PACKAGING

1.2

0.1

±0.2

±0.05

±0.1

MAX.

±0.2

TYP.

12.0

0.2

0.5

0.1

0.10

±0.08

20.0

±0.3

18.4

0.125

19.0

±0.1

1.0

±0.1

Package base plane

48 TSOP (TSOP048-P-1220)

Page 45

PACKAGING

0.30 AB SCD

0.15

8.0

0.2

1.2

MAX.

0.35

±0.05

0.1 S

∗

0.4

TYP.

0.45

±0.03

0.8

TYP.

0.4

TYP.

2.0

TYP.

0.8

TYP.

0.4

TYP.

1.2

TYP.

∗Land hole diameter

for ball mounting

8.0

0.2

/ /

48 CSP (FBGA048-P-0808)

Datasheet LH28F800SGB-L10, LH28F800SGR-L70, LH28F800SGR-L10, LH28F800SGHR-L70, LH28F800SGHR-L10 Datasheet (Sharp)

Specifications and Main Features

Frequently Asked Questions

User Manual