Datasheet LH28F160S5T-L70 Datasheet (Sharp)

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Page 1

PRODUCT SPECIFICATIONS

Integrated Circuits Group

LH28F160S5T-L70A

Flash Memory

16M (2MB × 8/1MB × 16)

(Model No.: LHF16KA9)

Spec No.: EL127112A

Issue Date: August 29, 2000

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LHF16KA9

Handle this document carefully for it contains material protected by international copyright

law. Any reproduction, full or in part, of this material is prohibited without the express

written permission of the company.

When using the products covered herein, please observe the conditions written herein

and the precautions outlined in the following paragraphs. In no event shall the company

be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following

application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed

in Paragraph (3).

4 *Office electronics

instrumentation and measuring equipment

*Machine tools

Audiovisual equipment

Home appliance

*Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment

which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system.

+ntrol and safety devices for airplanes, trains, automobiles, and other

transportation equipment

*Mainframe computers

iraff ic control systems @Gas leak detectors and automatic cutoff devices oRescue and security equipment

Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands

extremely high performance in terms of functionality, reliability, or accuracy.

*Aerospace equipment *Communications equipment for trunk lines aControl equipment for the nuclear power industry *Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above

three Paragraphs to a sales representative of the company.

Please direct all queries regarding the products covered herein to a sales representative

of the company.

Rev.1.9

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I INTRODUCTION.

1 .l Product Overview

2 PRINCIPLES OF OPERATION..

2.1 Data Protection

3 BUS OPERATION

3.1 Read ...................................................................

3.2 O&put Disable ....................................................

3.3 Standby.. ............................................................. 7

3.4 Deep Power-Down

3.5 Read Identifier Codes Operation.. .........

3.6 Query Operation

3.7 Write ....................................................................

1 COMMAND DEFINITIONS.. ..................................... 8

4.1 Read Array Command..

4.2 Read Identifier Codes Command..

4.3 Read

4.4

4.5 Query Command,

4.51 Block Status Register .................................. 12

4.5.2 CFI CIuery Identification

4.5.3 System Interface Information.. ..................... 13

4.5.4 Device Geometry Definition ......................... 14

4.5.5 SCS OEM Specific Extended Query Table.. 14

4.6 Block Erase Command

4.7 Full Chip Erase Command

4.8 Word/Byte Write Command..

4.9 Multi Word/Byte Write Command..

4.10 Block Erase Suspend Command..

4.11 (Multi) Word/Byte Write Suspend Command ... 17

4.12 Set Block Lock-Bit Command.. ........................ 18

4.13 Clear Block Lock-Bits Command.. ................... 18

4.14 STS Configuration

Clear

Status Status

.....................................................

................................................

.............................. 6

................................................... 7

....................................................

..............................................

..................................................

..................................... 1 1

....................

...............................................

Stiing.. ................... 13

...................................... 15

................................ 15

............................. 16

.................... 16

................... 17

Command ......................... 19

LHFlGKA9

CONTENTS

PAGE PAGE

. ............. 8

5 DESIGN CONSIDERATIONS ................................ .30

5.1 Three-Line Output Control ................................ .30

5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration

Polling.. ............................................................. .30

5.3 Power Supply Decoupling.. ............................... .30

5.4 V,, Trace on Printed Circuit Boards.. ............... .30

5.5 V,,, V,,, RP# Transitions.. .............................. .31

5.6 Power-Up/Down Protection.. ............................. .31

5.7 Power Dissipation ............................................. .31

6 ELECTRICAL SPECIFICATIONS.. ........................ .32

6.1 Absolute Maximum Ratings .............................. .32

6.2 Operating Conditions ........................................ .32

6.2.1 Capacitance ................................................ .32

6.2.2 AC Input/Output Test Conditions.. ............... .33

6.2.3 DC Characteristics.. ..................................... .34

6.2.4 AC Characteristics - Read-Only Operations .36

6.2.5 AC Characteristics - Write Operations.. ....... .39

6.2.6 Alternative CE#-Controlled Writes.. ............. .41

6.2.7 Reset Operations ........................................ .43

6.2.8 Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit

Configuration Performance.. ........................ .44

7 ADDITIONAL INFORMATION ............................... .45

7.1 Ordering Information ......................................... .45

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LHFlGKA9

LH28F160S5T-L70A

1 GM-BIT (2MBx8/1 MBxl6)

Smart 5 Flash MEMORY

n Smart 5 Technology

- 5v vcc

- 5v vpp

n Common Flash Interface (CFI)

- Universal & Upgradable Interface I Scalable Command Set (SCS) I High Speed Write Performance

- 32 Bytes x 2 plane Page Buffer

- 2ps/Byte Write Transfer Rate n High Speed Read Performance

- 70ns(5V*0.25V), 80ns(5V*0.5V) n Operating Temperature

- 0°C to +7O”C

I Enhanced Automated Suspend Options

- Write Suspend to Read

- Block Erase Suspend to Write

- Block Erase Suspend to Read

n High-Density Symmetrically-Blocked

Architecture

- Thirty-two 64K-byte Erasable Blocks I SRAM-Compatible Write Interface I User-Configurable x8 or x16 Operation

n Enhanced Data Protection Features

- Absolute Protection with Vpp=GND

- Flexible Block Locking

- Erase/Write Lockout during Power Transitions

n Extended Cycling Capability

- 100,000 Block Erase Cycles

- 3.2 Million Block Erase Cycles/Chip

n Low Power Management

- Deep Power-Down Mode

- Automatic Power Savings Mode Decreases ICC in Static Mode

n Automated Write and Erase

- Command User Interface

- Status Register

n Industry-Standard Packaging

- 56-Lead TSOP

n ETOXrM* V Nonvolatile Flash

Technology

n CMOS Process

(P-type silicon substrate)

n Not designed or rated as radiation

hardened

SHARP’s LH28F160S5T-L70A Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile, ,ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory :ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S5T-L70A offers three levels of protection: absolute protection with V,, at 3ND, selective hardware block locking, or flexible software block locking. These alternatives give designers Jltimate control of their code security needs.

The LH28F160S5T-L70A is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer *ates and minimize device and system-level implementation costs.

The LH28F160S5T-L70A is manufactured on SHARP’s 0.35um ETOX

ndustry-standard package: the 56-Lead TSOP, ideal for board constrained applications.

‘ETOX is a trademark of Intel Corporation.

TM* V process technology. It come in

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1 INTRODUCTION

This datasheet contains

specifications. Section 1 provides a flash memory

overview. Sections 2, 3, 4, and 5 describe the

memory organization and functionality. Section 6

covers electrical specifications.

LH28F160S5T-L70A

1.1 Product Overview

The LH28F160S&T-L70A is a high-performance 16Mbit Smart 5 Flash memory organized as 2MBx8/1 MBxl6. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3.

Smart 5 technology provides a choice of V,, and V,, combinations, as shown in Table 1, to meet system performance and power expectations. 5V V,,

provides the highest read performance. V,, at 5V eliminates the need for a separate 12V converter, while V,,=5V maximizes erase and write performance. In addition to flexible erase and program voltages, the dedicated V,, pin gives complete data protection when V,+V,,Lk.

Internal automatically configures the device for optimized read and writeoperations.

A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence

written to the CUI initiates device automation. An

internal Write State Machine (WSM) automatically

executes the algorithms and timings necessary for

block erase, full chip erase, (multi) word/byte write

and block lock-bit configuration operations. A block erase operation erases one of the device’s

64K-byte blocks typically within 0.34s (5V Voo, 5V V,,) independent of other blocks. Each block can be independently erased 100,000 times (3.2 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block.

A word/byte write is performed in byte increments typically within 9.24us (5V Vcc, 5V Vpp). A multi word/byte write has high speed write performance of 2uslbyte (5V Vcc, 5V V,,). (Multi) Word/byte write suspend mode enables the system to read data or

Table 1. Vcc.and VP, Voltage Combinations

Offered by Smart 5 Technology

Vcr: Voltage Vpp Voltage

5v 5v

VCC. and VW

detection Circuitry

execute code from any other flash memory array location.

Individual block locking uses a combination of bit: and WP#, Thirty-two block lock-bits, to lock ant unlock blocks. Block lock-bits gate block erase, ful

chip erase and (multi) word/byte write operations

Block lock-bit configuration operations (Set BlocE Lock-Bit and Clear Block Lock-Bits commands) se

and cleared block lock-bits. The status register indicates when the WSM’s block

erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished.

The STS output gives an additional indicator of WSM

activity by providing both a hardware signal of status (versus software polling) and status masking

(interrupt masking for background block erase, for example). CPU overhead and system power consumption. STS pin can be configured to different states using the Configuration command. The STS pin defaults tc

RY/BY# operation. When low, STS indicates that the WSM is performing a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. STS-High Z indicates that the WSM is ready for a new command, block erase is suspended and (multi) word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-down

mode. The other 3 alternate configurations are all pulse mode for use as a system interrupt.

The access time is 70ns (tAvQv) over the commercial

temperature range (0% to +7O”C) and Vc, supply voltage range of 4.75V-5.25V. At lower Voc voltage, the access time is 80ns (45V-55V).

The Automatic Power Savings (APS) feature substantially reduces active current when the device

is in static mode (addresses not switching). In APS m-ode, the typical lCCR current is 1 mA at 5V V,,.

When either CE,# or CE,#, and RP# pins are at Vcc, the I,, CMOS standby mode is enabled. When the

RP# pin is at GND, deep power-down mode is

enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHav) is required from RP# switching high until outputs are valid. Likewise, the device has a wake

time (tpHEL) from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset and

the status register is cleared. The device is available in 56-Lead TSOP (Thin Small

Outline Package, 1.2 mm thick). Pinout is shown in

Figure 2.

Status

polling using STS minimizes both

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CE# WEW OE#

RP# WP#

STS VW

+L kc

+- GND

‘7

8 9 10 11 12 13

VPP

RP# 16

Ail 17 40 18

2 20 19

GND 21

% 23 A5 24

2 25 26

A2 Al

14 15

Iz:

Figure 1. Block Diagram

56 LEAD TSOP

STANDARD PINOUT

14mm x 20mm

TOP VIEW

56 55 54 OE# 53 52 51 50 b Da;, 49

48 47 46 45

43 42 41 b DQII

40 38 37 vcc

36 35 Ei: 34 33 32 31 30

29 NC

WP# WE#

STS DQts

DC27

DQ,

VCC

GND

:::.

DQ2

DQ,

DQo

BYTE# NC

Figure 2. TSOP 56-Lead Pinout (Normal Bend)

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Symbol

*o-*20

XJo-DQ,

CE,#,

CE,#

RP#

OE#

WE#

STS

WP#

BYTE#

“PP

“cc

GND

_ -

Type

INPUT

INPUT/

OUTPUT

INPUT

INPUT INPUT

OPEN

DRAIN

OUTPUT

INPUT

SUPPLY

Table 2. Pin Descriptions

ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. Ao: Byte Select Address. Not used in x16 mode(can be floated). AI-AK Column Address. Selects 1 of 16 bit lines. As-At!% Row Address. Selects 1 of 2048 word lines.

A16420

DATA INPUT/OUTPUTS: DQo-DC&Inputs data and commands during CUI write cycles; outputs data during memory

array, status register, query, and identifier code read cycles. Data pins float to high-

impedance when the chip is deselected or outputs are disabled. Data is internally latched

during a write cycle.

DQs-DQ15:lnputs data during CUI write cycles in x16 mode; outputs data during memory

array read cycles in xl 6 mode; not used for status register, query and identifier code read

mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(Byte#=V,, ). Data is internally latched during a write cycle. CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense amplifiers. Either CEO# or CE,# VIH deselects the device and reduces power consumption

to standby levels. Both CEn# and CE,# must be VII to select the devices.

RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP# VI, enables normal operation. When driven V,,, RP# inhibits write operations which provides data protection during power transitions. Exit from deep

power-down sets the device to read array mode.

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse. STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal

operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). STS High Z indicates that the WSM is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. For alternate configurations of the STATUS pin, see the Configuration command. WRITE PROTECT: Master control for block locking. When VI,, Locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. BYTE ENABLE: BYTE# V,, places device in x8 mode. All data is then input or output on DQO-,, and DQ8-t5 float. BYTE# V,, places the device in x16 mode , and turns off the Ac input buffer. BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE. BLOCK LOCKBIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or configuring block lock-bits. With Vpp<V+pLK, memory contents cannot be altered. Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid Vpp (see DC Characteristics) produce spurious results and should not be attempted. DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do

not

inhibited. Device operations at invalid Vcc voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated.

: Block Address.

float any power pins. With VCCIVLKO, all write attempts to the flash memory are

LHFlGKA9

Name and Function

Rev. 1.9

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2 PRINCIPLES &OPERATION

The LH28F160S5T-L70A Flash memory includes an

on-chip WSM to manage block erase, full chip erase, (multi) word/byte

configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block

erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings.

After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations.

Status bgister, query structure and identifier codes can be accessed through the CUI independent of the VP, voltage. High voltage on VP, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. All functions associated with altering memory contents--block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codes-are accessed via the CUI and verified through the status register.

write and block lock-bit

Commands are microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, (multi) word/byte write and block lockbit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, Addresses and data are internally cycles. Writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data.

Interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to *cad or write data from any other block. Write suspend allows system software to suspend a (multi) Nerd/byte write to read data from any other flash nemory array location.

written

and mar ining

using

atch during write

standard

of data.

Figure 3. Memory Map

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2.1 Data Protection 3.2 Output Disable

Depending on the application, the system designer may choose to make the V,, power supply

switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to V,,,,. The device accommodates either design practice and encourages optimization of the processor-memory interface.

When Vpp~VppLK,

altered. The CUI, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command protection from unwanted operations even when high

voltage ,is applied to V,,. All write functions are

disabled when V,, is below the write lockout voltage VLKO or when RP# is at V,,. The device’s block locking capability provides additional protection from

inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations.

memory contents cannot be

sequences, provides

3 BUS OPERATION

The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

With OE# at a logic-high level (VI,), the device outputs are disabled. Output pins DQo-DQ,, are placed in a high-impedance state.

3.3 Standby

Either CE,# or CE,# at a logic-high level (V,,) place:

the device in standby mode which substantial!

reduces device power consumption. DQo-DQ,

outputs are placed in a high-impedance state

independent of OE#. If deselected during bloc1 erase, full chip erase, (multi) word/byte write am block lock-bit configuration, the device continue: functioning, and consuming active power until the operation completes.

3.4 Deep Power-Down

RP# at V,, initiates the deep power-down mode. In read modes, RP#-low deselects the memory

places output drivers in a high-impedance state ant turns off all internal circuits. RP# must be held low fo a minimum of 100 ns. Time tpHQv is required afte, return from power-down until initial memory access outputs are valid. After this wake-up interval, norma operation is restored. The CUI is reset to read arra) mode and status register is set to 80H.

3.1 Read

During block erase, full chip erase, (multi) word/byte

Information can be read from any block, identifier codes, query structure;gr status register independent of the V,, voltyge. RP# must be at V,,.

The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component: CE# (CEo#, CE,#), OE#, WE#, RP# and WP#. CE,#, CE,# and OE# must be driven active to obtain data at the outputs. CE,#, CE,# is ihe device selection control, and when active enables the selected memory device. OE# is the data output (DQo-DQ,,) control and when active drives the selected memory data onto the I/O bus. WE# and SP# must be at VI,. Figure 17, 18 illustrates a read :ycle.

write or block lock-bit configuration modes, RP#-Ion will abort the operation. STS remains low until the

reset operation is complete. Memory contents beins altered are no longer valid; the data may be partialI] erased or written. Time t,,,, is required after RP#I goes to logic-high (V,,) before another command car be written.

As with any automated device, it is important tc a$sert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full

chip erase, (multi) word/byte write and block lock-bii configuration. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing

status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP#

input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

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3.5 Read Identifier Codes Operation 3.6 Query Operation

The read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition.

,. :

,..

::. . . .

. . .:.

: :

4 :j /

&&tied f& . . :

-.Ftiu~etmpiementaiion

lFoC&”

-ir.i-i-----------------------------

lFOCQ5 IF0004

,Fooo3 :;-----_------------- ----- - ---- --

Block 31 Status Code

Reserved for ;

,Fo(JJ(;

‘. Future

IEFFFF; : . : .’ .”

020000~

OlFFFF.1.

: :,:

., . . . ‘.’

.*.

01~ i : I,..\

----L ---^ L *----------------- .L ---------

01ooo5 ,,,

010004

o,ooo3 T----------------------------------

. .

., ..

o,m;..‘,. .; ,j.

OOFFFF :.

: : ; :

lmplemehation :

Bfock.41;

: (Blq&s 2thrtigh 3?I,)

: ; ) ,;

.’ Resewed’for

Ftiuie iinpteb3ntation ” .’

Block 1 Status dode

I&serve&for .~

Future. I-nylemg&ftion. I. : .,

.BlQckl~

. . .

Reserved for

Future Implement&ion

c4)0(&

-___ -_--___-- -___ -_-_----_----_----___

ooooO5

OmOO4 000003 000002

_-------------------------------------

OOOOOl

Block 0 Status Code

Device Code

Manufacturer Code

Block 0

The query operation outputs the query structure Query database is stored in the 48Byte ROM. Quer) structure allows system software to gain critica information for controlling the flash component Query structure are always presented on the lowest. order data output (DQo-DQ,) only.

3.7 Write

Writing commands to the CUI enable reading 01

device data and identifier codes. They also contra,

inspection and clearing of the status register. When Vcc=Vcc1,2 and VPP=VPPH1, the CUI additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration.

The Block Erase command requires appropriate

command data and an address within the block to be erased. The Word/byte Write command requires the

command and address of the location to be written.

Set Block Lock-Bit command requires the command

and block address within the device (Block Lock) to be locked. The Clear Block Lock-Bits command

requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 19 and 20 illustrate WE# and CE#-controlled write operations.

4 COMMAND DEFINITIONS

When the VP, voltage I V,,,,, Read operations from the status register, identifier codes, query, or blocks

are enabled. Placing VP,+, on V,, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands.

Figure 4. Device Identifier Code Memory Map

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Table 3. Bus Operations(BYTE#=V,,)

Mode

Read

Output Disable Standby 3 Deep Power-Down 4 V,,

Read Identifier

Codes Query Write 3,7,&g v,H

Mode Read . Outputbisable 3 V,M v,,

Standby 3 Deep Power-Down 4 v,, X X X

Read Identifier

Codes Query

Write 3,7,&g v,H V,, V,, v,,, V,, X X D,N X

NOTES:

1. Refer to DC Characteristics. When VpplVppLK, memory contents can be read, but not altered.

2. X can be VIL or V,H for control pins and addresses, and VP,,, or VP,,+, for V,,. See DC Characteristics for VP,,, and VP,,, voltages.

3. STS is VoL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. It isfloated during when the WSM is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power;down mode.

4. RP# at GNDlt0.2V ensures the lowest deep power-down current.

5. See Section 4.2 for read identifier code data.

6. See Section 4.5 for query data.

7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when VPP=VPr+,1 and Vcc=Vcc,,2.

8. Refer to Table 4 for valid D,, during a write operation.

9. Don’t use the timing both OE# and WE# are VI,.

1 Notes 1 RP# 1

1 1 r&3,9 1 vlH I VII I VII I VII ! VIH !

CEd 1 CEd 1 OE#

I WE# I Address 1 VP,, I DQ,,,li I

1 X b-ml X

STS

3 V,,-, V,, V,, V,,-, V,H X X High Z X

VI,

VI, $H VI,

X X

9 9

VI, VI, VI, VI, vlH

vlH VI, VI, VI, vlH

VI,

V,H

X X X

X X High Z X

X X High Z High Z

See

Figure 4 ’

See Table x

7-11

Note 5 High Z Note 6 High Z

V,, V,, v,H V,, X X D,N X

Table 3.1. Bus Operations(BYTE#=V , )

Notes RP# CEn# CE,# OE# WE# Address VP,, DQ&, STS

1,2,3,9 v,,, V,, V,, V,, v,,, X X DolIT X

V,, V,,-j

VI, vlH

vlH vlH VI,

V,H

X X X X High Z X

X HighZ X

v,, v,,,

9 9

‘1, YL YL YL ‘1,

VI, VI, VI, VI, vlH

X X High Z High Z

See

Figure 4 ’

See Table x

7-11

Note 5 High Z Note 6 High Z

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Command

Read Array/Reset Read Identifier Codes

LHFlGKA9

Table 4. Command Definition@)

Bus Cycles Notes First Bus Cycle

Req’d Oper(‘) Addr(*) Data(“) Ope#) Addr(*) Data@)

1 Write X FFH

Write X 90H Read IA

Second Bus Cycle

Level-Mode for Erase and Write (RY/BY# Mode) STS Configuration

Pulse-Mode for Erase STS Confiauration Pulse-Mod< for Write STS Configuration Pulse-Mode for Erase and Write

dOTES:

. BUS operations are defined in Table 3 and Table 3.1.

I. X=Any valid address within the device.

lA=ldentifief. Code Address: see Figure 4.

QA=Query Offset Address.

BA=Address within the block being erased or locked.

WA=Address of memory location to be written.

‘. SRD=Data read from status register. See Table 14 for a description of the status register bits.

WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high

first).

ID=Data read from identifier codes.

QD=Data read from query database.

. Following the Read Identifier Codes command, read operations access manufacturer, device and block status

codes. See Section 4.2 for read identifier code data.

. If the block is locked, WP# must be at VI, to enable block erase or (multi) word/byte write operations. Attempts

to issue a block erase or (multi) word/byte write to a locked block while RP# is V,,.

. Either 40H or 10H are recognized by the WSM as the byte write setup.

. A block lock-bit can be set while WP# is VI,.

. WP# must be at VI, to clear block lock-bits. The clear block lock-bits operation simultaneously clears nil

lock-bits.

. Following the Third Bus Cycle, inputs the write address and write data of ‘N’ times. Finally, input the confirm

command ‘DOH’.

0. Commands other than those shown above are reserved by SHARP for future device implementations and

should not be used.

1 Write 1

Write Write Write

X 1 B8H 1 Write 1 X

X X X

B8H B8H B8H

Write Write

1 OOH

X X X

OlH 02H 03H

hlnck

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4.1 Read Array Command

Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled For reads until another command is written. Once the internal WSM has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend and (Multi) Word/byte Write Suspend command. The Read Array command functions independently of the V,, voltage and RP# must be

VI,.

4.2 &ad Identifier Codes Command

The identifier code operation is initiated by writing the Read Identifier Codes command. Following the :ommand write, read cycles from addresses shown in =igure 4 retrieve the manufacturer, device, block lock zonfiguration and block erase status (see Table 5 for

dentifier code values). To terminate the operation, Nrite another valid command. Like the Read Array zommand, the Read Identifier Codes command ‘unctions independently of the V,, voltage and RP# nust be Vi,. Following the Read Identifier Codes :ommand, the following information can be read:

Table 5. Identifier Codes

Code

*Block is Unlocked DC&,=0 *Block is Locked DC&= 1 l Last erase operation

completed successfully

*Last erase operation did

not completed successfully

*Reserved for Future Use

MOTE:

1. X selects the specific block status code to be read. See Figure 4 for the device identifier code memory map.

1 Address 1 Data 1

DQ, =0 DC+1

DQ2-,

4.3 Read Status Register Command

The status register may be read to determine when 2 block erase, full chip erase, (multi) word/byte write OI block lock-bit configuration is complete and whethel the operation completed successfully(see Table 14) It may be read at any time by writing the Read Statu: Register command. After writing this command, al subsequent read operations output data from the

status

register until another valid command is written The status register contents are latched on the falling edge of OE# or CE#(Either CE,# or CE,#), whichever occurs. OE# or CE#(Either CEo# or CE,#;

must toggle to VI, before further reads to update the status register latch. The Read Status Register command functions independently of the V,, voltage.

RP# must be VI,.

The extended status register may be read tc

determine multi word/byte write availability(see Table

14.1). The extended status register may be read al any time by writing the Multi Word/Byte Write command. After writing this command, all subsequeni

read operations output data from the extended status

register, until another valid command is written. Multi Word/Byte Write command must be re-issued to update the extended status register latch.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 and SR.1 are set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate

various failure conditions (see Table 14). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking

multiple blocks or writing several bytes in sequence)

may be performed. The status register may be polled to determine if an error occurs during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V,, Voltage. RP# must be V,,. This

command is not functional during block erase, full chip erase, (multi) word/byte write block lock-bit configuration, block erase suspend or (multi) word/byte write suspend modes.

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4.5 Query Command

Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 7-l 1 retrieve the critical information to write, erase and otherwise control the flash component. Ac of query offset address is ignored when X8 mode (BYTE#=V,,).

Query data are always presented on the low-byte data output (DC&,-DQ,). In x16 mode, high-byte :DQs-DQ,,) outputs OOH. The bytes not assigned to xty information or reserved for future use are set to ‘0”. This command functions independently of the L/P,, voltage. RP# must be V,,.

Table 6. Example of Query Structure Output

Oute

Mode 1 Offset Address 1

DQ,c;-j-,

A,,

1 , 0 , 0 , 0 , 0 , 0 (20H) High Z

X8 mode 1 , 0 , 0 , 0 , 0 , 1 (21H) High Z

1, O,O,O,l ,0(22H) HighZ "I?" 1 , 0 , 0 , 0 , 1 , 1 (23H) High Z

X16mode 1 ,O,O,O,O (10H) OOH "Q"

A,, A,, A,, A,

A,, A,, A,, A,,

1 ,O,O,O,l (11H) OOH "R"

Nit

DQ,-,

"Q" "Q"

"Fl"

1.5.1 Block Status Register

rhis field provides lock configuration and erase status for the specified block. These informations are only available when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status Iit will be set to “1”. If bit 1 is “l”, this block is invalid.

Table 7. Query Block Status Register

Offset

(Word Address)

(BA+2)H

Mote:

1. BA=The beginning of a-Block Address.

Length

OlH Block Status Register

bit0 Block Lock Configuration

O=Block is unlocked

bit1 Block Erase Status

O=Last erase operation completed successfully

, 1 =Last erase operation not completed successfully

bit2-7 reserved for future use

1 =Block is Locked

Description

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4.5.2 CFI Query Identification String

The Identification String provides verification that the component supports the Common Flash interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are)

supported.

Table 8. CFI Query Identification String

Description

13H,14H 15H,16H 17H,18H

02H 02H

02H

Primary Vendor Command Set and Control Interface ID Code 01 H,OOH (SCS ID Code) Address for Primary Algorithm Extended Query Table 31 H,OOH (SCS Extended Query Table Offset) Alternate Vendor Command Set and Control Interface ID Code OOOOH (OOOOH means that no alternate exists) Address for Alternate Algorithm Extended Query Table OOOOH (OOOOH means that no alternate exists)

4.5.3 System Interface Information

The following device information can be useful in optimizing system interface software.

Table 9. System Information String

1FH .OlH 20H OlH 21H OlH 22H OlH 23H 24H

25H OlH

26H OlH

01H OlH

V,, Logic Supply Minimum Write/Erase voltage 27H 12.7V)

Vcc Logic Supply Maximum Write/Erase voltage 55H (5.5V)

V,, Programming Supply Minimum-Write/Erase voltage 27H (2.7V) Vpp Programming Supply Maximum Write/Erase voltage 55H (5.5V) Typical Timeout per Single Byte/Word Write 03H (23=8us) Typical Timeout for Maximum Size Buffer Write (32 Bytes) 06H (26=64us) Typical Timeout per Individual Block Erase OAH (OAH=lO, 210=1024ms)Typical Timeout for Full Chip Erase OFH (OFH=15, 215=32768ms) Maximum Timeout per Single Byte/Word Write, 2N times of typical. 04H (24=1 6, 8usxl6=128us) Maximum Timeout Maximum Size Buffer Write, 2N times of typical. 04H (24=1 6, 64usxl6=1024us) Maximum Timeout per Individual Block Erase, 2N times of typical. 04H (24=1 6, 1024msxl6=16384ms) Maximum Timeout for Full Chip Erase, 2N times of typical. 04H (24=1 6,32768msxl6=524288ms)

Description

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1.5.4 Device Geometry Definition

rhis field provides critical details of the flash device geometry.

Table 10. Device Geometry Definition

Offset

(Word Address)

27H 28H,29H 2AH,2BH 2CH 2DH,2EH

2FH,30H

Length Description

01H Device Size

15H (15H=21, 221=2097152=2M Bytes)

02H

02H OlH Number of Erase Block Regions within device 02H The Number of Erase Blocks 02H

Flash Device Interface description 02H,OOH (x8/x1 6 supports x8 and xl 6 via BYTE#) Maximum Number of Bytes in Multi word/byte write 05H,OOH (25=32 Bytes )

01 H (symmetrically blocked)

1 FH,OOH (1 FH=31 ==> 31+1=32 Blocks)

The Number of “256 Bytes” cluster in a Erase block

OOH,Ol H (OlOOH=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block)

$55 SCS OEM Specific Extended Query Table

Zertain flash features and commands may be optional in a vendor-specific algorithm specification. The optional rendor-specific Query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s).

Table 11. SCS OEM Specific Extended Query Table

Offset

(Word Address)

31 H,32H,33H 03H PRI 34H

35H 36H,37H, 38H,39H ”

3AH

3BH,3CH 02H 03H,OOH

3DH 3EH 3FH

Length

50H,52H,49H OlH 31 H (1) Major Version Number , ASCII OlH 30H (0) Minor Version Number, ASCII 04H

OlH OlH

OlH OlH Vpp Programming Supply Optimum Write/Erase voltage(highest performance)

reserved Reserved for future versions of the SCS Specification

QFH,OOH,OOH,OOH

Optional Command Support

bitO=l : Chip Erase Supported bitl=l : Suspend Erase Supported bit2=1 : Suspend Write Supported bit3=1 : Lock/Unlock Supported bit4=0 : Queued Erase Not Supported

bit5-31 =O : reserved for-future use

Supported Functions after Suspend

bitO=l : Write Supported after Erase Suspend

bit1 -7=O : reserved for future use

Block Status Register Mask

bitO=l : Block Status Register Lock Bit [BSR.O] active bitl=l : Block Status Register Valid Bit [BSR.l] active

bit2-l5=0 : reserved for future use Vcc Logic Supply Optimum Write/Erase voltage(highest performance) 50H(5.OV)

50H@OV)

Description

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4.6 Block Erase Command

Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the STS pin or status register bit SR.7.

When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued.

This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SK5 being set to “1 ‘I. Also, reliable block erasure San only occur when Vcc=Vcc1,2 and VPP=VPPH,. In the absence of this high voltage, block contents are orotected against erasure. If block erase is attempted while V&l,,,,, Successful block erase requires that the :orresponding block lock-bit be cleared or if set, that tiP#=V,,. If Flock erase is attempted when the :orrespondincj’ block lock-bit is set and WP#=V,,, SR.l and SR.5 will be set.to “1”.

SR.3 and SR.5 will be set to “1 ‘I.

4.7 Full Chip Erase Command

erase setup is first written, followed by a full chil erase confirm. After a confirm command is written device erases the all unlocked blocks from block 0 tc

Block 31 block by block. This command sequenct requires appropriate sequencing. preconditioning, internally by the WSM (invisible to the system). Afte the two-cycle full chip erase sequence is written, thf device automatically outputs status register da&

when read (see Figure 6). The CPU can detect ful

chip erase completion by analyzing the output data o

the STS pin or status register bit SR.7. When the full chip erase is complete, status registe;

bit SR.5 should be checked. If erase error i: detected, the status register should be cleared before system software attempts corrective actions. The CU remains in read status register mode until a ne\n command is issued. If error is detected on a blocE during full chip erase operation, WSM stops erasing Reading the block valid status by issuing Read IC Codes command or Query command informs whict blocks failed to its erase.

This two-step command sequence of set-up followec

by execution ensures that block contents are no’ accidentally erased. An invalid Full Chip Erase

command sequence will result in both status register

bits SR.4 and SR.5 being set to “1”. Also, reliable ful chip erasure can only occur when Vcc=Vcc,,2 ant VPP=VPPHI. In the absence of this high voltage, block contents are protected against erasure. If full chip

erase is attempted while V,,IV,,,,, SR.3 and SR.5 will be set to “1”. When WP#=V,,, all blocks are erased. independent of block lock-bits status. When WP#=V,,, only unlocked blocks are erased. In this case, SR.l and SR.5 will not be set to “1“. Full chip erase can not be suspended.

erase and verify are handle<

Bloc1

rhis command followed by a confirm command :DOH) erases all of the unlocked blocks. A full chip

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4.8 Word/Byte Write Command

Word/byte write is executed by a two-cycle command sequence. Word/Byte Write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect the completion of the word/byte write event by analyzing the STS pin or status register bit SR.7.

When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully write to “0”s. The CUI remains in read status register mode until it receives another command.

Reliable word/byte writes can only occur when Vcc=Vcc,,2 and VPP=VPPH1. In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while V,,&V,,,,, status register bits SR.3 and SR.4 will be set to “1”. Successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP#=V,,. If word/byte write is attempted when the corresponding block lock-bit is set and WP#=V,L, SR.l and SR.4 will be set to “1”. Word/byte write operations with V,,<WP#<V,, produce spurious results and should not be attempted,

continue monitoring XSR.7 by writing multi word/bytt

write setup with write address until XSR.7 transition:

to 1. When XSR.7 transitions to 1, the device is read)

for loading the data to the buffer. A word/byte coun

(N)-1 is written with write address. After writing ; word/byte count(N)-1, the device automatically turm back to output status register data. The word/byte count (N)-1 must be less than or equal to 1FH in xE mode (OFH in x16 mode). On the next write, device start address is written with buffer data. Subsequen, writes provide additional device address and data depending on the count. All subsequent address must lie within the start address plus the count. After

the final buffer data is written, write confirm (DOH;

must be written. This initiates WSM to begin copying

the buffer data to the Flash Array. An invalid Mult Word/Byte Write command sequence will result ir

both status register bits SR.4 and SR.5 being set tc “1”. For additional multi word/byte write, write another multi word/byte write setup and check XSR.7. The Multi Word/Byte Write command can be queuec

while WSM is busy as long as XSR.7 indicates “1”1 because LH28F160S5T-L70A has two buffers. If an error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded in multi word/byte write command. Status register bit SR.4 will be set to “1 ‘I. No multi word/byte write command is available if either SR.4 or SR.5 are sei

to “1”. SR.4 and SR.5 should be cleared before

issuing multi word/byte write command. If a multi

word/byte write command is attempted past an erase

block boundary, the device will write the data to Flash Array up. to an erase block boundary and then stop writing. Status register bits SR.4 and SR.5 will be se1 to “1 ‘I.

4.9 Multi Word/Byte. Write Command

Vlulti word/byte write is executed by at least fourcycle or up to 35-cycle command sequence. Up to 32 bytes in x8 mode (16 words in x16 mode) can be

oaded into the buffer and written to the Flash Array. ?rst, multi word/byte write setup (E8H) is written with :he write address. At this point, the device automatically outputs extended status register data :XSR) when read (see Figure 8, 9). If extended status register bit XSR.7 is 0, no Multi Word/Byte iNrite command is available and multi word/byte write setup which just has been written is ignored. To retry,

Reliable multi byte writes can only occur when

Vcc=Vcc1,2 and VPP=VPPHI. In the absence of this

high voltage, memory contents are protected against

multi word/byte writes. If multi word/byte write is attempted while V,+V,,,k, status register bits SR.3 and SR.4 will be set to “1”. Successful multi word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP#=V,,. If multi byte write is attempted when the corresponding block lock-bit is set and WP#=V,L, SR.l and SR.4 will be set to “1 I’.

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1.10 Block Erase Suspend Command

The Block Erase Suspend command allows blockerase interruption to read or (multi) word/byte-write data in another block of memory. Once the blockxase process starts, writing the Block Erase Suspend command requests that the WSM suspend :he block erase sequence at a predetermined point in :he algorithm. The device outputs status register data ,vhen read after the Block Erase Suspend command

s written. Polling status register bits SR.7 and SR.6 xn determine when the block erase operation has Deen suspended (both will be set to “1”). STS will also transition to High Z. Specification twHRH2 defines :he block erase suspend latency.

At this Qoint, a Read Array command can be written to read data from blocks other than that which is suspended. A (Multi) Word/Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the (Multi) word/Byte Write Suspend command (see Section

4.1 l), a (multi) word/byte write operation can also be suspended. During a (multi) word/byte write operation with block erase suspended, status register bit SR.7 will return to “0” and the STS (if set to RY/BY#) Dutput will transition to VOL. However, SR.6 will remain “1’ to indicate block erase suspend status.

The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM inrill continue the block erase process. Status register oits SR.6 and SR.7 will automatica!ly clear and STS nil1 return to V&. After the Erase Resume command is written, the device automatically outputs status register data when read ‘(see Figure 10). V,, must remain at VppH1 (the same V,, level used for block erase) while block erase is suspended. RP# must also remain at VI,. Block erase cannot resume until

(multi) word/byte write operations initiated during block erase suspend have completed.

4.11 (Multi) Word/Byte Write Suspend Command

The (Multi) Word/Byte Write Suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. Once the (multi) word/byte write process starts, writing the (Multi) Word/Byte Write Suspend command requests that the WSM suspend the (multi) word/byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the (Multi) Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the (multi) word/byte write operation has been suspended (both will be set

“1”). STS will also transition to High Z.

to Specification twHRHl defines the (multi) word/byte write suspend latency.

At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while

(multi) word/byte write is suspended are Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written

to the flash memory, the WSM will continue the

(multi) word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and STS will

return to V,,. After the (Multi) Word/Byte Write command is written, the device automatically outputs status register data when read (see Figure 11). V,,

must remain at V,,,, (the same V,, level used for

(multi) word/byte write) while in (multi) word/byte write suspend mode. WP# must also remain at V,, or

YL*

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4.12 Set Block Lock-Bit Command

A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V,,,

individual block lock-bits can be set using the Set

Block Lock-Bit command. See Table 13 for a summary of hardware and software write protection options.

Set block lock-bit is executed by a two-cycle command sequence. The set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set block lock-bit algorithp. After the sequence is written, the device automatically outputs status register data when read (see Figure 12). The CPU can detect the completion of the set block lock-bit event by analyzing the STS pin output or status register bit SR.7.

When the set block lock-bit operation is complete, status register bit SR.4 should be checked. If an error

is detected, the status register should be cleared.

The CUI will remain in read status register mode until a new command is issued.

This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being set to “1”. Also, reliable operations occur only when Vcc=Vccv2 and VPP=VPPHI. In the absence of this high voltage, block* lock-bit contents are protected against alteration.

block lock-bits can be cleared using only the Cleal Block Lock-Bits command. See Table 13 for s summary of hardware and software write protectior options.

Clear block lock-bits operation is executed by a two. cycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data

when read (see Figure 13). The CPU can deteci

completion of the clear block lock-bits event by

analyzing the STS Pin output or status register bii

SR.7.

When the operation is complete, status register bii SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued.

This two-step sequence of set-up followed by

execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to “1”. Also, a reliable clear

block lock-bits operation can only occur when Vcc=Vcc1,2 and VPP=VPPH1. If a clear block lock-bits operation is attempted while V,,IV,,,k, SR.3 and SR.5 will be set to “1 I’. In the absence of this high voltage, the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires WP#=V,,. If it is attempted with WP#=V,,, SR.l and SR.5 will be set to “1” and the operation will fail. Clear block lock-bits operations with V,,,<RP# produce spurious results and should not be attempted.

A successful set block ‘lock-bit operation requires WP#=V,,. If it is attempted with WP#=V,,, SR.l and SR.4 will be set to “1” and the operation will fail. Set block lock-bit operations with WP#<V,, produce spurious results and should not be attempted.

4.13 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With WP#=V,,,

If a clear block lock-bits operation is aborted due to

V,, or Voo transitioning out of valid range or RP# active transition, block lock-bit values are left in an

undetermined state. A repeat of clear block lock-bits

is required to initialize block lock-bit contents to known values.

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4.14 STS Configuration Command

The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device is powered down or RP# is set to V,,. Upon initial device power-up and after exit from deep power-down mode, the STS pin defaults to RY/BY# operation where STS low indicates that the WSM is busy. STS High Z indicates that the WSM is ready for a new operation.

To reconfigure the STS pin to other modes, the STS Configuration is issued followed by the appropriate configuration code. The three alternate configurations are all pulse mode for use as a system interrupt. The STS Configuration command functions independently of the Vpp voltage and RP# must be VI,+.

Table 12. STS Configuration Coding Description

Configuration

Bits

OOH

OlH

02H

03H

Set STS pin to default level mode (RY/BY#). RY/BY# in the default

level-mode of operation will indicate ~ WSM status condition. Set STS pin to pulsed output signal for specific erase operation. In this mode, STS provides low pulse at the completion of BLock Erase, Full Chip Erase and Clear Block Lock-bits operations. Set STS pin to pulsed output signal for a specific write operation. In this mode, STS provides low pulse at

the completion of (Multi) Byte Write

and Set Block Lock-bit operation. Set STS pin to pulsed output signal

for specific write and erase operation. STS provides low pulse at the completion of Block Erase,

Full Chip Erase, (Multi) Word/Byte

Write and Block Lock-bit Configuration operations.

Effects

Operation

Block Erase, . 0 (Multi) Word/Byte , Write

Full Chip Erase Set Block Lock-Bit X

Clear Block Lock-Bits X

Block

Lock-Bit

091

X vp , All blocks are erased

Table 13. Write Protection Alternatives

WP# Effect

VI, or VI,., Block Erase and (Multi) Word/Byte Write Enabled

VI,

V,, All unlocked blocks are erased, locked blocks are not erased V,,

V,H

V,,

V,w

Block is Locked. Block Erase and (Multi) Word/Byte Write

Disabled Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled

Set Block Lock-Bit Disabled Set Block Lock-Bit Enabled Clear Block Lock-Bits Disabled

Clear Block Lock-Bits Enabled

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Table 14. Status Register Definition

WSMS j BESS

7 6

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready

0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS

STATUS

1 = Error in Erase or Clear Bloc1 Lock-Bits

0 = Successful Erase or Clear Block Lock-Bits

SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS only after block erase, full chip erase, (multi) word/byte

1 = Error in Write or Set Block Lock-Bit write or block lock-bit configuration command

0 = Successful Write or Set Block Lock-Bit sequences. SR.3 is not guaranteed to reports accurate

SR.3 = V,, STATUS

1 = V,, Low Detect, Operation Abort

O=V,,OK

SR.2 = WRITE SUSPEND STATUS

1 = Write Suspended

0 = Write in Progress/Completed

SR.l = DEVICE PROTECT STATUS

1 = Block Lock-Bit and/or WP# Lock Detected,

Operation Abort

0 = Unlock -

SR.0 = RESERVED FOR FUTURE*ENHANCEMENTS

1 ECBLBS 1 WSBLBS 1 VPPS

5 4 3

LHFlGKA9 20

wss DPS R

2 1 0

NOTES:

Check STS or SR.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. SR.6-0 are invalid while SR.7=“0”.

If both SR.5 and SR.4 are “1”s after a block erase, full

chip erase, (multi) word/byte write, block lock-bit configuration or STS configuration attempt, an improper command sequence was entered.

SR.3 does not provide a continuous indication of V,, level. The WSM interrogates and indicates the V,, level

feedback only when V,p&/,p,, . SR.l does not provide a continuous indication of block

lock-bit values. The WSM interrogates block lock-bit, and WP# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set and/or WP# is not V,,. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock-bit status.

SR.0 is reserved for future use and should be masked out when polling the status register.

Table 14.1. Extended Status Register Definition

SMS

7 6 5

XSR.7 = STATE MACHINE STATUS

1 = Multi Word/Byte Write available After issue a Multi Word/Byte Write command: XSR.7

0 = Multi Word/Byte Write not available indicates that a next Multi Word/Byte Write command is

XSR.G-O=RESERVED FOR FUTURE ENHANCEMENTS

R R R R

4 3 2 1 0

NOTES:

available.

XSR.G-0 is reserved for future use and should be

masked out when polling the extended status register.

R R R

Rev. 1.9

Page 23

SHARP

. -

Block Address

LHFIGKAS

Bus

OpOWlOtl

write

Read

Standby

Write Etaso setup

Writ.3

Read

Standby

Commrnd Comments

Read Status

Rsgister

Erase

confirm

Data-70H Addr-X

Status Ragistar Data

Check SR.7

l-WSM Ready

(bWSM Busy

Data&UH Adds-Within Block to be Erased

Data-DOH

Adds-Within Block to be Erased

Status Register Data

Check SR.7

1 -WSM Ready

O=WSM Busy

Check if Desired

FULL STATUS CHECK PROCEDURE

(C)

Dewce Protect Error

Repeat for subsequent block erasures. Full status check can be dona after each block erase or after a sequence of

block erasures.

Write FFH after the last operation to place device in read away mode.

BUS

Operalion

Standby

standby

Standby

%t.5,SR.4,SR.3 and SR.1 are onb cleared by the Clear Status

f error IS detected. clear the Status Register before attempting

ratly or other error raCO”wy.

Comma”d Comments

Check SR.3

lxVpp Error Detect

Check SR. 1

I-Device Protect Detect

WP#~VIL,Blo& Lock-Bit is Set

Only required for systems

implementing lock-bit configuration

Check SR.4.5 Soti l=Command Sequence Enw

Check SR.5

l=Elock Erase Error

L-

Figure 5. Automated Block Erase Flowchart

Rev. 1.9

Page 24

SHARF=

. -

LHF16KA9

Read

:uII stabs check can be done after each full chip erase. Wit0 FFH after tie last opera(ion to place device in mad array mode.

Status Register Data

Check if Desired

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(Sae Above)

Full Chip Erase

Successful

/ O:~c” 1 GrnrnMd /

Standby

SR.S.SR.4.SR.3 and SR.1 are only dewed by the Clear Status

If error is detected. clear the Status Register before attempting

retry or other error ?-eccNery.

Figure 6. Automated Full Chip Erase Flowchart

Comments

Check SR.3

l=Vpp Error Detect

Chedc SR.4.5 Both l=Command Sequence Error

Check SR.5 l-Full Chip Erase Error

Rev. 1.9

Page 25

SHARI=

stall

SR.7=

_ -

LHFIGKAS 23

Command Comments

Write

Read

standby

Wlite

write

Read

standby

Repeat for subsequent word/byte writes. SR full stah~s check can be done after each worn write. or after a sequence of

wordbyte writes.

Write FFH after the last wotdibyte write operabn to place device in

mad anay mode.

Read status

Setup Word/Byte

wlite

Word/Byte Write

Data-70H

Add,=X

Status Register Data

Check SR.7 l-W% Ready

OIWSM Busy

Datw4OH or 10H Addr-Locabon to Be Written

Data-Data to Be Written Addr-Location to Be Written

Status Register Data

Check SR.7 1 =WSM Reacfy o.wsM Busy

FULL STATUS CHECK PROCEDURE

(5zyttz?] . . . ,

Device Protect Enw

BUS

Op~tiOn

Standby

SR.4,SR.3 and SR.1 are only dearud by the Clear Status Register

command in cases where multiple locations are witten before full status is checked.

If em)r is detected, clear the Status Regster before attempting

retry or other error recovery.

Command

Figure 7. Automated Word/byte Write Flowchart

Comments

Check SR.3

l.Vpp Error Detect

Check SR.1

I-Devise Pmtect Detect

WPY-V#o& Lock-Bit is Set

Only required for systems implementing lock-bit configuration

Check SR.4

l-Data Write Error

Rev. 1.9

Page 26

_ -

LHFlGKA9

Bus

Opsration

Command

Comments

4 Write Buffer Data,

Start Address

Write Buffer Data,

Device Address

Wlite DOH

\ Abort

StiP

Multi WordByte write

write

Read

standby

write

(N&l)

Write

(N&2,3)

Read

Standby

-I-----

1, Byte or word count values on DC!,,., are loaded into the count register.

2. Write Buffer contents will be programmed at the start address.

3. Align the start address on a Write Buffer boundary for maximum programming perfonance.

4.The device aborts the Multi Word/Byte Write command if the current address is outside of theprfginal block address.

B.The Status Register indicates an ‘improper command sequence’ if the Multi

WordByte command is aborted. Follow this with a Clear Status Register command.

SR full status check can be done after each multi wov9byte write,

or after Q sequence of multi wotiyte writes.

Write FFH after the last multi wordbyte write operation to place device in

read array mode.

DataPEBH Add&tart Address

Extended Status Register Data

Check XSR.7 l-Multi Word/Byte Write Ready

O-Multi woldmyte writ0 Buoy

Data-Word or Byte Count (N)-1 Addr-Start Address

DataPBuffer Data Add&tart Address

Data-Buffer Data Addr-Device Address

Data-DOH Addr=X

Status Register Data

Check SR.7 1 =WSM Ready 0s.WSM Busy

L-

Read Status

Figure 8. Automated Multi Word/Byte Write Flowchart

Rev. 1.9

Page 27

SHARP

FULLSTATUSCHECKPROCEWRE FOR MULTI WORD/BYTE WRITE OPERATION

Read status Register Command Comments

Device Protect Enor

LHFIGKAS

Check SR.3 t=Vpp Ermr Detect

Check SR.1

stsndby

Standby

SRS.SR.4.SR.3 and SR.1 are only deamd by the Clear Status Register

command in casas where multiple locations are written before

full status is dmcked.

If ermr is detected. clear the Status Register before attempting

retry oroUw error recovery.

l=Dovlce Protect Detect WPwPV,L,Bfock Lock-Bit is Set Only mquimd for systems implementing lock-bit contigumtion

Check SFt.4.5 Both 1Gommand Sequence Error

Check SR.4

l-Data Write Ermr

Figure 9. Full Status Check Procedure for Automated Multi Word/Byte Write

Rev. 1.9

Page 28

SHARP

_ -

SR.7=

LHFlGKA9 26

Bus

OpeMiOll

Standby

Write

Command Comments

Check SR.7

1 -WSM Ready

ONWSM Bury

Chock SR.6 l-Block Erase Suspended

O-Block Erase Completed

EtWe

ReSUllS

Data&OH Addr-X

(Multi) wofd/Byte write Loop

Figure 10. Block Erase Suspend/Resume Flowchart

Rev. 1.9

Page 29

SHARP

_ -

,*,

I I

SR.7-

Write FFH

(MUlli) worvsvto write\

Compk

ied /

LHFlGKA9

Read

Standby

Write

(Multi) WodSyte Write Data&H

Suspend AddhX

Status Register Data Addr=X

Chock SR.7 l-WSM Ready

0a.Ws.M Busy

Chech 533.2 b(Mul6) Word’eyte Write

SUSpended

O-(Multi) Word/Byte Write

Completed

DatarFFH AddhX

Read Array locatbns other than that being written.

(Multi) Word/Byte Write Data-DOH

Resume

Addr-X

Read Army Data

Figure 11. (Multi) Word/Byte Write Suspend/Resume Flowchart

Rev. 1.9

Page 30

SHARP

Block Address

SR.7=

4 1

Check if Desired

_ -

LHFlGKA9

Command

Writ.3

Repeat for subsequent block lock-bit set operations. Full status chsck can be done after each block l&-bit set operation

or after a sequence of block lock-bit set operations.

Write FFH after the last block lo&-bit set operation to place device in

read army mode.

Set Block

Lock-Bit Setup

Data-6Ol-l

Add&lock Address

FULL STATUS CHECK PROCEDURE

(T)

Command Comments

Standby

SRS,SR.4,SR.3 and SR.l am only cleared by tfw Clear Status

If error 1s d&tad. clear the Status Register before attempting

retry or other error recovery.

Check SR.3

I-Vpp Error Detect

Check SR.4

l&at Block Lock-Bit Error

Figure 12. Set Block Lock-Bit Flowchart

Rev. 1.9

Page 31

SHARP

LHF16KA9

Stall

Wnto 60H

I I

FULL STATUS CHECK PROCEDURE

SR.7-

c?-

Read Status Register

Check if Desired

Data(See Above)

Command

q---Q&y

Writ9

Read

Standby

Write FFH after the Clear Block Lock-Sib operation to place device in read array mode.

Standby

Clear Blodc Data=DOH

Lock-Sits Confirm

Command

Data&OH Add-X

Addr-X

chak SR.7

l=WSM Ready

OIWSM Busy

Chedc SR.3

I+,, Error Detect

Standby

Check SR.5 l-Clear Block Lock-Bits Error

Clear Block Lock-Bits

SUCCeSSfUl

Standby

SR.S,SR.4,SR.3 and SR.1 am only deared by the Clear Status

If error is detected. clear the Status Register before attempting

retry or other ermr mcovely.

Figure 13. Clear Block Lock-Bits Flowchart

L-

Rev. 1.9

Page 32

LHFlGKA9

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory arrays. SHARP provides three control accommodate multiple memory connections. ThreeLine control provides for:

a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will

not occur.

To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’s READ#Qontrol line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.

inputs to

5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Polling

STS is an open drain output that should be connected to Vcc y hardware method of detecting block erase, full chip erase, (multi) .word/byte write and block lock-bit configuration completion. In default mode, it transitions low after block erase,, full chip erase, (multi) word/byte write or block lock-bit configuration commands and returns to V,, when the WSM has finished executing the’ internal algorithm. For alternate STS pin configurations, see the

Configuration command.

b a pullup resistor to provide a

STS, in default mode, is also High Z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics require

careful device decoupling. System designers are

interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a O.luF ceramic capacitor connected between its Vcc and GND and between its V,, and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7uF electrolytic capacitor should be placed at the array’s power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.

5.4 Vpp Trace on Printed Circuit Boards

Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V,, Power supply trace.

The V,, pin supplies the memory cell current for

block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. Use similar trace

widths and layout considerations given to the V,,

power bus. Adequate V,, supply traces and

decoupling will decrease V,, voltage spikes and overshoots.

STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.

Rev. 1.9

Page 33

SHARP

. -

LHFlGKA9

5.5 VCC, Vpp, RP# Transitions

Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if V,, falls outside of a valid V,,,, range, Voo falls outside of a valid VCCIR range, or RP#=V,,. If V,,X error is detected, status register bit SR.3 is set to “1” along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V,, during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, STS(if set to RY/BY# mode) will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to V,, clear the status register.

The CUI latches commands issued by system software and is not altered by V,, or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after Voc transitions below VLko.

After block erase, full chip erase, (multi) word/byte

write or block lock-bit configuration, even after V,, transitions down to V,,,,, the CUI must be placed in

read array mode via the Read Array command if subsequent access to the memory array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against accidental block and- full chip , erasure, (multi) word/byte writfhg or block lock-bit configuration during power transitions. Upon. power-up, the device is

indifferent as to which power supply (V,, or Vc,)

powers-up first. Internal circuitry resets the CUI tc read array mode at power-up.

A system designer must guard against spuriou: writes for Voo active. Since both WE# and CE# must be low for : command write, driving either to V,, will inhibit writes

The CUl’s two-step command sequence architecturt

provides added level of protection against dat: alteration.

In-system block lock and unlock capability prevent: inadvertent data alteration. The device is disablec

while RP#=VIL regardless of its control inputs state.

voltages above VLKo when V,, i!

5.7 Power Dissipation

When designing portable systems, designers mus consider battery power consumption not only durin! device operation, but also for data retention durin! system idle time. Flash memory’s nonvolatiliQ

increases usable battery life because data is retainec

when system power is removed.

In addition, deep power-down mode ensure: extremely low power consumption even when systen power is applied. For example, portable computin{ products and other power sensitive applications tha use an array of devices for solid-state storage car consume negligible power by lowering RP# to V,, standby or sleep modes. If access is again needed the devices can be read following the tPHQV ant t,,,, wake-up cycles required after RP# is firs raised to V,,. See AC Characteristics- Read OnI) and Write Operations and Figures 17, 18, 19, 20 foi more information.

Rev. 1.9

Page 34

SHARI=

_ -

LHFIGKAS

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings*

Operating Temperature

During Read, Erase, Write and

Block Lock-Bit Configuration . . . . . . ..O”C to +70”C(1)

Temperature under Bias . . . . . . . . . . . . . . . -10°C to +8O”C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125X

Voltage On Any Pin

(except Voo, V,,) . . . . . . . . . . . . . . . -0.5V to Voo+O5V(*)

Voc Suply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .

V,, Update Voltage during

Erase, Write and

Block Lock-Bit Configuration . . . . ..-0.2V to +7.OV(*)

Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . lOOmA

-0.2v to +7.ov(*)

*WARNING: Stressing the device beyond th

“Absolute Maximum Ratings” may cause permaner damage. These are stress ratings only. Operatio, beyond the “Operating Conditions” is nc recommended and extended exposure beyond th,

“Operating Conditions” may affect device reliability.

NOTES:

1. Operating temperature

temperature product defined by this specification.

2. All specified voltages are with respect to GND Minimum DC voltage is -0SV on input/output pin

and -0.2V on Vco and V,, pins. Durin! transitions, this level may undershoot to -2.OV fo periods <20ns. Maximum DC voltage OI input/output pins and Vcc is Vc,+O.5V which during transitions, may overshoot to Voc+2.OV fo periods e20ns.

3. Output shorted for no more than one second. Nc more than one output shorted at a time.

is for commercia

6.2 Operating Conditions

6.2.1 CAPACITAN’CE(‘) .I’

Symbol Parameter C,N

cn, ,T Output Capacitance

NOTE:

1. Sampled, not 100% tested.

Input Capacitance

T,=+25”C,

Typ. Max.

9 12

f=l MHz

Unit

pF pF ‘Jr-,, ,r=O.OV

v,,=o.ov

Condition

Rev. 1.9

Page 35

SHARP

LHF16KA9

6.2.2 AC INPUTiiJTPUT TEST CONDITIONS

AC test inputs are driven at 3.OV for a Logic “1” and O.OV for a Logic “0.” Input timing begins, and output timing en&, at 1.5V. Input rise and fall times (10% to 90%) cl0 ns.

Figure 14. Transient Input/Output Reference Waveform for Vcc=5V~0.25V

(High Speed Testing Configuration)

AC test inputs are driven at VOH (2.4 Vm) for a Logic “1” and (2.0 Vm) and

VIL

(0.8 Vm). Output timing ends at

Figure 15. Transient Input/Output Reference Waveform for Vcc=5V+0.5V

1.3v

RL=3.3kR

-t-

CL Includes Jig

Capacitance

Figure 16. Transient Equivalent Testing

Load Circuit

-I- CL

VOL

VIH

and

VIL.

(Standard Testing Configuration)

lN914

(0.45

VTTL)

for a Logic “0.” Input timing begins at

Input rise and fall times (10% to 90%) <lo ns.

VIH

Rev. 1.9

Page 36

SHARP

5.2.3 DC CHARACTERISTICS

Symbol Parameter Notes

‘Ll

‘LO

‘cc,

‘CC0

‘CCR

Input Load Current

Output Leakage Current 1

Vcc Standby Current

Vcc Deep Power-Down

’ Current

Vcc Read Current

1,396

1 A6 CMOS Inputs

LHFlGKA9

DC Characteristics

v(-c=sv

TYP.

25 100

2 4 mA

Max. Unit

*lO

50 mA

65 mA

lJA

CIA

Test

Conditions Vcc=VccMax. V,,=V,c or GND Vcc=V&lax. VCllIT=VCC or GND CMOS Inputs V,,=V,,Max. CE#=RP#=Vcc’0.2V

TTL Inputs Vcc=VccMax. CE#=RP#=V,,

RP#=GND*O.2V I,,,,(STS)=OmA

Vcc=VccMax.

CE#=GND f=8MHz, louT=OmA TTL Inputs Vcc=VccMax., CE#=V,, f=8MHz, 10,,T=OmA ,

B Write or Set Block

Rev. 1.9

Page 37

SHARP

LHFlGKA9

DC Characteristics (Continued)

VOTES: I. All currents are in RMS unless otherwise noted. Typical values at nominal V,, voltage and TA=+25”C.

!* ‘CC,, and ‘CCES

the device’s current draw is the sum of lccws or lCCES and I,,, or I,,,, respectively.

3. Includes STS.

1. Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when V#I,,Lk, and not guaranteed in the range between V,,Lk(max.) and V,,,,(min.) and above VppH,(max.).

5. Automatic Power Savings (APS) reduces typical ICC, to 1 mA at 5V Vcc in static operation.

j. CMOS inputs are either Vcc+0.2V or GNDk0.2V. TTL inputs are either V,, or V,,.

7. Sampled, not 100% tested.

are specified with the device de-selected. If read or byte written while in erase suspend mode,

Page 38

SHARI=

_ -

LHFlGKA9

6.2.4 AC CHARA-iTERlSTlCS - READ-ONLY OPERATIONS(‘)

Vcc=5V+0.5V, 5Vt0.25V, T,pO ‘C to +7O”C

Vcc=5V*0.25V) LH28F _ _ _ _ _ . :16OS5-L70@) 1 ,

vcc=5v*o.5v 1 1 LH28F16OS5-L80@)

fF, n, tELFL

tF, FH

NOTES:

1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.

2. OE# may be delayed up to t,Lav-bLov after the falling edge of CE# without impact on tELQV.

3. Sampled, not 100% tested.

4. See Ordering Information for device speeds (valid operational combinations).

5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing characteristics.

6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics.

BYTE# to Output in High Z 3 25 30 CE# Low to BYTE# High or Low

5 5 ns

Rev. 1.9

Page 39