Page 1
®
PRODUCT SPECIFICATIONS
Integrated Circuits Group
LH28F160BJHE-TTL90
Flash Memory
16M (1M × 16/2M × 8)
(Model No.: LHF16J04)
Spec No.: EL11X036
Issue Date: November 11, 1999
Page 2
SliARP
LHF16504
l Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.
l When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).
*Office electronics
aInstrumentation and measuring equipment
@Machine tools
*Audiovisual equipment
*Home appliance
l Com’munication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands hiuh reliabilitv, should first contact a sales representative of the company and then
accept responsibility for incorporatin,
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
@Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
*Mainframe computers
@Traffic control systems
*Gas leak detectors and automatic cutoff devices
*Rescue and security equipment’
aOther safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high oerformance in terms of functionality, reliability, or accuracy.
aAerospace equipment
*Communications equipment for trunk lines
*Control equipment for the nuclear power industry
*Medical equipment related to life support, etc.
(4) Please direct all queries and comments regardin,
Paragraphs to a sales representative of the company.
0 into the design fail-safe operation, redundancy, and
0 the interpretation of the above three
l Please direct all queries regardin,
company.
0 the products covered herein to a sales representative of the
Rev. 1.15
Page 3
SHARP
LHFl6504
CONTENTS
PAGE
INTRODUCTION.. ............................................................ 3
1.1 Features ........................................................................ 3
1.2 Product Overview..
1.3 Product Description.. ................................................... .4
1.3.1 Package Pinout ...................................................... .4
1.3.2 Block Organization.. ............................................... 4
PRINCIPLES OF OPERATION.. ...................................... 7
2.1 Data Protection.. .......................................................... .8
BUS OPERATION
3.1 Read .............................................................................. 8
3.2 Output Disable
3.3 Standby.. ....................................................................... 8
3.4 Reset ............................................................................. 8
3.5 Read Identifier Codes.. ................................................ .9
3.6 Write.. ..........................................................................
COMMAND DEFINITIONS ............................................. 9
4.1 Read Array Command.. .............................................. 12
4.2 Read
4.3 Read Status Register Command.. ............................... 12
4.4 Clear Status Register Command..
4.5 Block Erase Command..
4.6 Full Chip Erase
4.7 Word/Byte Write Command.. ..................................... 13
4.8 Block Erase Suspend Command ................................ I4
4.9 Word/Byte Write Suspend Command..
4.10 Set Block and Permanent Lock-Bit Command.. ....... I5
4.1 1 Clear Block Lock-Bits Command
4.12 Block Locking by the WP#
Identifier Codes Command ............................... 12
....................................................... 3
............................................................ 8
.............................................................. 8
.9
...............................
............................................. 13
Command ......................................... 13
......................
............................ 15
......................................
12
14
16
PAGE
5 DESIGN CONSIDERATIONS ....................................... 25
5.1 Three-Line Output Control
5.2 RY/BY# and WSM Polling .......................................
5.3 Power Supply Decoupling
5.4 Vccw Trace on Printed Circuit Boards
5.5 v,, . vccw.
5.6 Power-Up/Down
5.7 Power Dissipation
5.8 Data Protection Method
6 ELECTRICAL SPECIFICATIONS ................................
6.1 Absolute Maximum Ratings..
6.2 Operating Conditions .................................................
6.2.1 Capacitance
AC Input/Output Test Conditions.. ...................... 28
6.2.2
6.2.3 DC Characteristics ............................................... 29
6.2.4 AC Characteristics - Read-Only Operations..
6.2.5 AC Characteristics - Write Operations
6.2.6 Alternative CE#-Controlled Writes
6.2.7 Reset Operations
6.2.8 Block Erase. Full Chip Erase, Word/Byte Write and
Lock-Bit Configuration Performance ................. 39
7 PACKAGE AND PACKING SPECIFICATIONS
RP# Transitions .................................... 25
Protection.. ..................................... 26
...................................................... 26
.......................................................... 27
........................................ 25
25
......................................... 25
..................... 25
............................................. 26
27
.................................... 27
27
...... 31
................ 34
...................... 36
.................................................. 38
.......... 40
1
Rev. 1.25
Page 4
LI-IFI 6504
LH28F 160B JHE-TTL90
2
IGM-BIT ( 1Mbit x16 / 2Mbit
Boot Block Flash MEMORY
n Low Voltage Operation
- v,,=v(-cw-L.
n User-Configurable x8 or x 16 Operation
n High-Performance Read Access Time
- 90ns(Vcc=2.7V-3.6V)
n Operating Temperature
- -40°C to +85”C
I Low Power Management
-
Typ. 2uA (V,,=3,OV) Standby Current
-
Automatic Power Savings Mode Decreases ICCR in
Static Mode
- Typ. 120pA (V,,=3.OV, T,=+25”C. f=32kHz)
Read Current
n Optimized Array Blocking Architecture
-
Two 4K-word (8K-byte) Boot Blocks
-
Six 4K-word (8K-byte) Parameter Blocks
-
Thirty-one 32K-word (64K-byte) Main Blocks
- Top Boot Location
n Extended Cycling Capability
-
Minimum 100,000 Block Erase Cycles
-’ 7V-3.6V Single Voltage
x8
)
H Enhanced Automated Suspend Options
-
Word/Byte Write Suspend to Read
-
Block Erase Suspend to Word/Byte Write
-
Block Erase Suspend to Read
n Enhanced Data Protection Features
-
Absolute Protection with VCCWIVCCWLK
-
Block Erase, Full Chip Erase, Word/Byte Write and
Lock-Bit Configuration Lockout during Power
Transitions
-
Block Locking with Command and WP#
-
Permanent Locking
n
Automated Block Erase, Full Chip Erase,
Word/Byte Write and Lock-Bit Configuration
-
Command User Interface (CUB
-
Status Register (SR)
n SRAM-Compatible Write Interface
n Industry-Standard Packaging
-
G-Lead TSOP
n ETOXTkt* Nonvolatile Flash Technology
W CMOS Process (P-type silicon substrate)
w Not designed or rated as radiation hardened
iHARP’s LH28F160BJHE-TTL90 Flash memory is a high-density. low-cost. nonvolatile, read/write storage solution for a
vide range of applications.
,H28F160BJHE-TTL90 can operate at V,,=2.7V-3.6V and Vc-w--.
:apability realize battery life and suits for cellular phone application.
ts Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component
uitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code
- data storage applications.
:or secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to
IRAM, the LH28F160BJHE-TTL90 offers four levels of protection: absolute protection with VccwlVc-wLK, selective
lardware block locking or flexible software block locking. These alternatives Z
ecurity needs.
he LH28F160BJHE-‘ITL90 is manufactured on SHARP’s 0.25pm ETOXT”*
tandard package: the 4%lead TSOP, ideal for board constrained applications.
ETOX is a trademark of Intel Corporation.
-3 TV-3.6V or 11.7V-12.3V. Its low voltage operation
oive designers ultimate control of their code
process technology. It come in industry-
Rev. 1.25
Page 5
SHARP
LHF16504
1 INTRODUCTION
This
specifications. Section 1 provides a flash memory
overview. Sections 2. 3. 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
datasheet
contains
LH28F160BJHE-T-IL90
1.1 Features
Key enhancements of LH28F16OBJHE-TTL90 boot block
Flash memory are:
Gingle low voltage operation
*Low power consumption
*Enhanced Suspend Capabilities
l Boot Block Architecture
Please note following:
l
VCCWLK has been lowered to l.OV to support 2.7V-
3.6V block erase. full chip erase. word/byte write and
lock-bit configuration operations. The Vccw voltage
transitions to GND is recommended for designs that
switch Vccw off during read operation.
1.2 Product Overview
The LH28F160BJHE-TTL90 is a high-performance 16Mait Boot Block Flash memory organized as lM-word of 16
aits or 2M-byte of 8 bits. The lM-word/2M-byte of data is
u-ranged in two 4K-word/SK-byte boot blocks, six 4Kword/8K-byte parameter blocks and thirty-one 32Kvord/64K-byte main blocks which are individually
:rasable, lockable and unlockable in-system. The memory
nap is shown in Figure 3.
Ihe dedicated V ccw pin gives complete data protection
vhen V
CCW’VCCWLK.
4 Command User Interface (CUD serves as the interface
jetween the system processor and internal operation of the
ievice. A valid command sequence written to the CUI
nitiates device automation. An internal Write State
vlachine (WSM) automatically executes the algorithms
md timings necessary for block erase, full chip erase.
vord/byte write and lock-bit configuration operations.
3
A block erase operation erases one of the device’s 32K-
word/6JK-byte blocks typically within 1.2s (3V Vcc. 3V
ccw). JK-word/8K-byte blocks typically within 0.6s (3V
V
V,,. 3V Vccw) independent of other blocks. Each block
can be independently erased minimum 100,000 times.
Block erase suspend mode allows system software to
suspend block erase to read or write data from any other
block.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 33~s (3V V,,. 3V Vccw). 6JK-byte blocks
typically within 31~s (3V V,,. 3V Vccw). 4K-word
blocks typically within 36~s (3V Vcc. 3V V,,,), 8Kbyte blocks typically within 32~s (3V Vcc. 3V Vccw).
Word/byte write suspend mode enables the system to read
data or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits, thirty-
nine block lock-bits. a permanent lock-bit and WP# pin. to
lock and unlock blocks. Block lock-bits gate block erase.
full chip erase and word/byte write operations. while the
permanent lock-bit pates block lock-bit modification and
locked block alternation. Lock-bit configuration
operations (Set Block Lock-Bit, Set Permanent Lock-Bit
and Clear Block Lock-Bits commands) set and cleared
lock-bits.
The status register indicates when the WSM‘s block erase,
fuli chip erase. word/byte write or lock-bit configuration
operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase. full chip erase.
word/byte write or lock-bit configuration. RY/BY#-high Z
indicates that the WSIM is ready for a new command.
block erase is suspended (and word/byte write is
inactive), word/byte write is suspended. or the device is in
reset mode.
1
Rev. 1.25
Page 6
LHFl6504
4
The access time is 90ns (tAv v) over the operating
temperature range (-40°C to + 5°C) 8 and V,- supply
voltage range of 2.7V-3.6V.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typicaJ ICCR
current is 2pA (CMOS) at 3.OV V,,.
When CE# and RP# pins are at V,-. the I,, CMOS
standby mode is enabled. When the RP# pin is at GND,
reset
mode is enabled which minimizes power
consumption and provides write protection. A reset time
(tpHQv) is required from RP# switching high until outputs
are valid. Likewise, the device has a wake time (tpHEL)
from RP#-high until writes to the CljI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
Please do not
has already been programed “0”. Overwrite operation may
generate unerasable bit. In case of reprogramming “0” to
the data which has been programed “1”.
.Prograrn “0” for the bit in which you want to change
data from ” 1” to “0”.
.Program “1” for the bit which has already been
programmed “0”.
For example, changing data from “10111101” to
‘10111100” requires “11111110” programming.
execute
reprogramming “0” for the bit which
1.3 Product Description
1.3.1 Package Pinout
LH28F160BJHE-TTL90 Boot Block Flash memory is
available in J8-lead TSOP package (see Figure 2).
1.32 Block Organization
This product features an asymmetrically-blocked
architecture providing system memory integration. Each
erase block can be erased independently of the others up to
100,000 times. For the address locations of the blocks. see
the memory map in Figure 3.
Boot Blocks: The boot block is intended to replace a
dedicated boot PROM in a microprocessor or
microcontroller-based system. This boot block 4K words
(4.096words) features hardware controllable write-
protection to protect the crucial microprocessor boot code
from accidental modification. The protection of the boot
block is controlled using a combination of the Vccw, RP#.
WP# pins and block lock-bit.
Parameter Blocks: The boot block architecture includes
parameter blocks to facilitate storage of frequently update
small parameters that would normally require an
EEPROM. By using software techniques. the word-rewrite
functionality of EEPROMs can be emulated. Each boot
block component contains six parameter blocks of 4K
words (4.096 words) each. The protection of the parameter
block is controlled using a combination of the Vccw. RP#
and block lock-bit.
Main Blocks: The reminder is divided into main blocks for
data
or
code storage.
one 32K words (32,768 words) blocks. The protection of
the main block is controlled using a combination of the
Vccw, RP#
and
Each 16M-bit device contains thirty-
block lock-bit.
Rev. 1.25
Page 7
SHARI=
LHF16504 5
CEY
WEX
OEX
RF?+
Buffer h /
WE#
RP#
vccw
WP#
RYlBY#
Al5
Al4
A13
A12
All
40
A9
‘48
49
NC
‘418
A17
A7
%
A5
A.,
A3
A2
Al
Figure 1. Block Diagram
4%LEAD TSOP
STANDARD PINOUT
12mm x 20mm
TOP VIEW
Figure 2. TSOP -%Lead Pinout
A16
BYTE?4
GND
DQJA-I
DQ7
DQu
DQ6
DQu
DQ5
DQlr
DQa
vcc
DQII
DQ3
DQIO
DQz
DQ!,
DQI
DQs
DQo
OE#
GND
CE#
A0
Rev. 1.25
Page 8
LHFl6JO4
Table 1. Pin Descriptions
Symbol
A-1
A,-‘419
"Qo-DQ,,
CE#
RP#
OE#
WE#
WP#
BYTE# INPUT DQO-,. and DQ,., j float. BYTE# V,, places the device in word mode (x16), and turns off the A-,
RY/BY# DRAIN
Vccw
vcc
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internal connected: it may be driven or floated.
Type
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
INPUT A-,: Lower address input while BYTE# is V,,. A-, pin changes DQ, j pin while BYTE# is Vt,.
A, j-A,,: Main Block Address.
A,,-A,,: Boot and Parameter Block Address.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles: outputs data
INPUT/
OUTpUT
INPUT
INPUT low. RP# inhibits write operations which provides data protection during power transitions. Exit
INPUT
INPUT
INPUT V,,, locked boot blocks can not be written or erased. WP# is not affected parameter and main
OPEN
OUTPUT
SUPPLY
SUPPLY the flash memory are inhibited. Device operations at invalid V,, voltage (see 6.2.3 DC
during memory array. status register and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched during a
write cycle. DQs-DQ, j pins are not used while byte mode (BYTE#=V,,). Then. DQls pin
changes A-, address input.
CHIP ENABLE: Activates the device’s control logic. input buffers. decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
_.
RESET: Resets the device internal automation. RP#-high enables normal operation. When driven
from reset mode sets the device to read array mode. RP# must be V,, during power-up.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WRITE PROTECT: When WP# is V,,. boot blocks cannot be written or erased. When WP# is
blocks.
BYTE ENABLE: BYTE# V,, places device in byte mode (x8). All data is then input or output on
input buffer.
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an
internal operation (block erase. full chip erase. word/byte write or lock-bit configuration).
RY/BY#-high Z indicates that the WSM is ready for new commands. block erase is suspended,
and word/byte write is inactive. word/byte write is suspended. or the device is in reset mode.
BLOCK ERASE. FULL CHIP ERASE. WORD/BYTE WRITE OR LOCK-BIT
CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words/bytes or
configuring lock-bits. With VCCW<VCCWLK.
chip erase, word/byte write and lock-bit configuration with an invalid V,--w (see 6.2.3 DC
Characteristics) produce spurious results and should not be attempted. Applying 12Va0.3V to
Vc-w during erase/write can only be done for a maximum of 1000 cycles on each block. V,,,
may be connected to 12V@.3V for a total of 80 hours maximum.
DEVICE POWER SUPPLY: Do not float any power pins. With V&V,,,, all write attempts to
Characteristics) produce spurious results and should not be attempted.
Name and Function
memory contents cannot be altered. Block erase, full
6
Rev. 1.25
Page 9
SHARI’=
LHFI 6504 7
2 PRINCIPLES OF OPERATION
The LH?8F160BJHE-TTL90
on-chip WSM to manage block erase. full chip erase.
wordlbyte write and lock-bit configuration functions. It
allows for: 100% TILleve control inputs. fixed power
supplies during block erase, full chip erase. word/byte
write and lock-bit configuration. and minimal processor
overhead with RAIM-like interface timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the Vccw voltage. High
voltage on Vccw enables successful block erase, full chip
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents-block
:rase, full chip erase. word/byte write. lock-bit
:onfiguration, status and identifier codes-are accessed via
he CUI and verified through the status register.
Commands are written using standard microprocessor
vrite timings. The CUI contents serve as input to the
WSM, which controls the block erase. full chip erase,
vord/byte write and lock-bit configuration. The internal
tlgorithms are regulated by the WSM, including pulse
,epetition, internal verification and margining of data.
iddresses and data are internally latched during write
:ycles. Writing the appropriate command outputs array
lata. accesses the identifier codes or outputs status register
lata.
nterface software that initiates and polls progress of block
‘rase. full chip erase, word/byte write and lock-bit
onfiguration can be stored in any block. This code is
opied to and executed from system RAIM during flash
nemory updates.
After successful
gain possible via the Read Array command. Block erase
uspend allows system software to suspend a block erase
I read/write data from/to blocks other than that which is
uspend. Word/byte write suspend allows system software
I suspend a word/byte write to read data from any other
lash memory array location.
flash memory includes an
completion, reads are
[AII-&II
FtlTF
FFm
FE.
Flilx4
rnr7+
mow
FCtFF
FCMI
FBWF
FBCW
FAFFF
FAlKK?
F9tFF
FW”,,
FRWF
FPIIXK)
RFFF
FM*)
EFFFF
E8MO
E7FFF
Eixml
DFFFF
D8D00
D7WF
c%
C8cix)
c7m
ET?=
B8Nx)
B7tFF
BOOM)
AFFFF
A8033
Am
AcmO
9tFFF
98wxl
97FFF
9MXJ
WFFF
88mo
87FFF
8oIx)t)
7FFFF
780X
77m
7oM
6FFFF
68oMl
67FFF
5Fkz
58Mo
57FFF
5OlXKl
JFFFF
48*M
J7FFF
:I
38mi,
37FFF
3otml
FFFF
28ooo
27FFF
XOXJ
IFFFF
,R,XX,
I7FFT
IIWX
OFFFF
“8MM
“7FFF
OO~KHI
Top Boot
B
Main
Block
32KWlhAKB Mam Block 23
32KW/6-lKB Xlam Block
32KWNKB ,Mun Block 28
Figure 3. Memory ~Map
Rev. 1.35
Page 10
SHARP
LHFl6504
2.1 Data Protection
Wkn vccw~vccw,,~
altered. The GUI. with two-step block erase. full chip
erase. word/byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
even when high voltage is applied to Vccw. All write
functions are disabled when Vcc is below the write
lockout voltage VLKO or when RP# is at V,,. The device’s
block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and word/byte write operations.
Refer to Table 5 for write protection alternatives.
memory contents cannot be
3 BUS OPERATlON
l3e local CPU reads and writes flash memory in-system.
411
bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
nformation can be read from any block. identifier codes
)r status register independent of the Vccw voltage. RP#
:an be at V,,.
i-he first task is to write the appropriate read mode
:ommand (Read Array, Read Identifier Codes or Read
itatus Register) to the GUI. Upon initial device power-up
jr after exit from reset mode, the device automatically
esets to read array mode. Six control pins dictate the data
low in and out of the component: CE#. OE#. BYTE#,
JZ#, RP# and WP#. CE# and OE# must be driven active
3 obtain data at the outputs. CE# is the device selection
ontrol. and when active enables the selected memory
evice. OE# is the data output (DQ,-DQlj) control and
{hen active drives the selected memory data onto the l/O
us. BYTE# is the device l/O interface mode control.
VE# must be at V,,, RP# must be at V,,. and BYTE#
nd WP# must be at V,,
:ad cycle.
2 Output
v’ith OE# at a logic-high level (VI,), the device outputs
re disabled. Output pins (DQ,-DQ,,) are placed in a
igh-impedance state.
Disable
or V,,. Figure 14. 15 illustrates
8
3.3 Standby
CE# a.t a logic-high level (V,,) places the device ir
standby mode which substantially reduces device powel
consumption. DQ,-DQ,, outputs are placed in a highimpedance state independent of OE#. If deselected during
block erase, full chip erase, word/byte write or lock-bil
confi,ouration, the device continues functioning, ant
consuming active power until the operation completes.
3.4 Reset
RP# at V,, initiates the reset mode.
In read modes, RP#-low deselects the memory. places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum ot
IOOns. Time tpHQV
mode until initial memory access outputs are valid. After
this wake-up interval. normal operation is restored. The
GUI is reset to read array mode and status register is set to
80H.
During block erase. full chip erase, word/byte write or
lock-bit configuradon modes. RP#-low will abort the
operation. RY/E%Y# remains low until the reset operation
is complete. Memory contents being altered are no longer
valid; the data may be partially erased or written. Time
tpmvL is required after RP# goes to logic-high (VIH)
before another command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase. full chip erase. word/byte write or
lock-bit configuration modes. If a CPU reset occurs with
no flash memory reset. proper CPU initialization may not
occur because the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In this
application. RP# is controlled by the same RESET# signal
that resets the system CPU.
is required after return from reset
Rev. 1.25
Page 11
SHARP
I:::_::_::::::
LHFl6504
3.5 Read Identifier Codes
The read identifier codes operation outputs the
manufacturer
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes. the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit settin:.
code.
device code. block lock configuration
3.6 Write
Writing commands to the CUI enable reading of device
data
and
identifier codes. They also control inspection and
clearing of the status register. When V&=2.7V-3.6V and
V
CCW=VCCWHIR)
erase. full chip erase, word/byte write and lock-bit
configuration.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and
an address within the device. The Word/Byte Write
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
zlevice (Permanent Lock) or block within the device
iBlock Lock) to be locked. The Clear Block Lock-Bits
:ommand requires the command and address within the
levice.
lhe CUI does not occupy an addressable memory
ocation. It is written when WE# and CE# are active. The
iddress and data needed to execute a command are latched
)n the rising
‘First). Standard microprocessor write timings are used.
?gures 16 and 17 illustrate WE# and CE# controlled write
operations.
t COMMAND DEFINITIONS
Nhen the VCcw voltage IV,,,,. Read operations from
he
status
register, identifier codes. or blocks are enabled.
‘lacing VCCWH,,2 on VCCw enables successful block
:rase. full chip erase. word/byte write and lock-bit
configuration operations.
device operations are selected by writing specific
ommands into the CUI. Table 3 defines these commands.
the CUI additionally controls block
edge
of WE# or CE# (whichever goes high
FFFFFf
Reserved for Future Implementation
FFrm
I
_______________-----------------------
FFOOZ
FFOOI
FFOOO
FEFFF
FE003
FE002
FDOOl
FDmil
FCFFF ;
FW,-!il !
. ,.I--
FXOO?
F8001
F8000
F7FFF
FOO03
EFFFF:
“----
07FFF
00004
00003
OOOO?
0000 I
00000 Manufacturer Code Main Block
Figure 4. Device Identifier Code Memory .Map
Boot Block 0 Lock Conliguration Co&
_________------------~~~~~~~~~~~~~~~~~
Reserved for Future Implementation
Boot Block 0
Reserved for Future Implementation
_____________ ------- ---------- ------
Boot Block 1 Lock Conlieuration Code
__________---------------_----_-
Reserved for Future Implementation
(Parameter Blocks I through -I)
Reserved for Future Implementation
_--_-______-__-___-_------------------
Reserved for Future ImpIementation
Reserved for Future Implementation
(Main Blocks 1 through 29)
Reserved for Future Implementation
Permanent Lock Conligrration Code
Main Block 30 Lock Configuration Code
____________________------------------
*: Address A.1 don‘t care.
Device Code
Parameter Block 0
-
Parameter Block 5
9
1
I
j[J
Rev. 1.25
Page 12
SHAl?P
Read Identifier Codes
LHFl6J04
Table 2.1. Bus Onerations (BYTE#=V,U)tt+z)
Write 1 6.7.8
VOTES:
1. Refer to DC Characteristics. When V,-,wIV,,w,,. memory contents can be read. but not altered.
2. X can be V,, or V,, for control pins and addresses. and V,,,,, or V,,,,,,? for Vccw. See DC Characteristics for
VCCwLK voltages.
3. RY/BY# is V,, when the WSM is executing internal block erase. full chip erase, word/byte write or lock-bit configuration
algorithms. It is High Z during when the WSIM is not busy, in block erase suspend mode (with word/byte write inactive),
word/byte write suspend mode or reset mode.
4. RP# at GNDk0.2V ensures the lowest power consumption.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase. full chip erase. word/byte write or lock-bit configuration are reliably executed
when VCCw=VCCWHln and V,-,=2.7V-3.6V.
7. Refer to Table 3 for valid Dt, during a write operation.
8. Never hold OE# low and WE# low at the same timing.
VI, VI, VI, VI,
X
DIN
X
Rev. 1.25
Page 13
SHARP
LHF 16504 11
Table 3. Command Definition&to)
1 Block Erase I 2 1 5 1 Write 1 X 1 20H 1 Write 1 BA 1 DOH 1
1 Full Chio Erase
Word/Byte Write
Block Erase and Word/Byte
Write Suspend -.
Block Erase and Word/Byte
Write Resume
Set Block Lock-Bit
Clear Block Lock-Bits
Set Permanent Lock-Bit
NOTES:
1. BUS operations are defined in Table 2.1 and Table 2.2.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 6 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and
permanent lock configuration codes. See Section 4.2 for read identifier code data.
5. If WP# is V,, boot blocks are locked without block lock-bits state. If WP# is V,,, boot blocks are locked by block lockbits. The parameter and main blocks are locked by block lock-bits without WP# state.
6. Either 4OH or 10H are recognized by the WSM as the word/byte write setup.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
9. Once the permanent lock-bit is set. permanent lock-bit reset is unable.
10. Commands other than those shown above are reserved by SHARP for future device implementations and should
I
2 I
2
1 5 Write X BOH
1 5 Write X DOH
2 8 Write X 60H
2 7.8 Write X 60H Write X DOH
2 9 Write X 60H
56
I
Write
Write X
I
X
l
30H I Write ( X I DOH I
40H or
10H
Write WA WD
Write BA
Write
X FlH
OIH
not be
Rev. 1.25
Page 14
LHF16504
12
4.1 Read Array Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This
aperation is also initiated by writing the Read Array
zomrnand. The device remains enabled for reads until
mother command is written. Once the internal WSM has
started a block erase. full chip erase. word/byte write or
.ock-bit configuration the device will not recognize the
Read Array command until the WSIM completes its
operation unless the WSM is suspended via an Erase
Suspend or Word/Byte Write Suspend command. The
iead Array command functions independently of the
Vccw
voltage and RP# can be Vt,.
L
1.2 Read Identifi& Codes Command
The identifier code operation is initiated by writing the
i
tead Identifier Codes command. Following the command
\
write. read cycles from addresses shown in Figure 4
r
etrieve the manufacturer. device, block lock configuration
a
tnd permanent lock configuration codes (see Table 4 for
i’
dentifier code values). To terminate the operation. write
a
another valid command. Like the Read Array command,
t
he Read Identifier Codes command functions
ndependently of the Vccw voltage and RP# can be V,,.
;
:ollowing the Read Identifier Codes command. the
f
ollowing information can be read:
Table 4. Identifier Codes
4.3 Read Status Register Command
The status register may be read to determine when a block
erase, full chip erase. word/byte write or lock-bil
configuration is complete and whether the operation
completed successfully. It may be read at any time by
writing the Read Status Register command. After writing
this command, all subsequent read operations output data
from the status register until another valid command is
written. The status register contents are latched on the
falling edge of OE# or CE#. whichever occurs. OE# or
CE# must toggle to V,, before further reads to update the
status register latch. The Read Status Register command
functions independently of the Vccw voltage. RP# can be
VI,.
4.4 Clear Status Register Command
Status register bits SRS. SR.4 SR.3 or SR.1 are set to
“1”s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 6). By allowing system software to
reset these bits. several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied Vccw
command is not functional during block erase or
word/byte write suspend modes.
Voltage. RP# can be V,,. This
Block Lock Configuration
*Block is Unlocked
*Block is Locked
*Reserved for Future Use
Permanent Lock Configuration
*Device is Unlocked
*Device is Locked
*Reserved for Future Use
IOTE:
BA selects the specific block lock configuration code
to be read. See Figure 4 for the device identifier code
memory map.
A-, don’t care in byte mode.
DQ, ,-DQ, outputs OOH in word mode.
DQI-7
Rev. 1.25
Page 15
SHARP
LHF 16JO4
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written.
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH/FFH). Block preconditioning. erase, and verify
are handled internally by the WSIM (invisible to the
system). After the two-cycle block erase sequence is
written. the device automatically outputs status register
data when read (see Figure 5). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
When the block erase-is complete, status register bit SR.5
should be checked. If a block erase error is detected. the
status register should be cleared before system software
Ittempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
I’his two-step command sequence of set-up followed by
:xecution ensures that block contents are not accidentally
:rased. An invalid Block Erase command sequence will
esult in both status register bits SR.4 and SR.5 being set
o “1”. Also, reliable block erasure can only occur when
dcc=2.7V-3.6V and VCCW=VC-wBl,,. In the absence of
his high voltage. block contents are protected against
:rasure. If block erase is attempted while VCCW<VCCWLK.
iR.3 and SR.5 will be set to “1”. Successful block erase
equires for boot blocks that WP# is V,, and the
,orresponding block lock-bit be cleared. In parameter and
nain blocks case, it must be cleared the corresponding
Ilock lock-bit. If block erase is attempted when the
xcepting above conditions. SR.1 and SR.5 will be set to
1 ‘I,
I.6 Full Chip Erase Command
his command followed by a confirm command erases all
f the unlocked blocks. A full chip erase setup (30H) is
lrst written, followed by a full chip erase confirm (DOH).
hfter a confirm command is written, device erases the all
nlocked blocks block by block. This command sequence
:quires appropriate sequencing. Block preconditioning,
rase and verify are handled internally by the WSM
nvisible to the system). After the two-cycle full chip
rase sequence is written, the device automatically outputs
atus register data when read (see Figure 6). The CPU can
etect full chip erase completion by analyzing the output
ata of the RY/BY# pin or status register bit SR.7.
ihen the full chip erase is complete. status register bit
R.5 should be checked. If erase error is detected, the
atus register should be cleared before system software
tempts corrective actions. The CUI remains in read
13
status register mode until a new command is issued. I
error is detected on a block during full chip erase
operation. WSM stops erasing. Full chip erase operatior
start from lower address block. finish the higher addres:
block. Full chip erase can not be suspended.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Full Chip Erase command sequencr
will result in both status register bits SR.4 and SR.5 being
set to “1”. Also, reliable full chip erasure can only occur
when V,,=2.JV-3.6V and VCCW=VCCWHt,2. In thr
absence of this high voltage, block contents are protectec
against erasure. If full chip erase is attempted while
ccwlV,,,,, SR.3 and SR.5 will be set to “1”
V
Successful full chip erase requires for boot blocks thal
WP# is V,, and the corresponding block lock-bit be
cleared. In parameter and main blocks case, it must be
cleared the corresponding block lock-bit. If all blocks are
locked. SR.1 and SR.5 will be set to “1”.
4.7 Word/Byte Write Command
Word/Byte write is executed by a two-cycle command
sequence.
alternate 10H) is written. followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSiM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written. the device
automatically outputs status register data when read (see
Figure 7). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected. the
status register should be cleared. The internal WSM verify
only detects errors for “1”s that do not successfully write
to “0”s. The CUI remains in read status register mode until
it receives another command.
Reliable word/byte writes can only occur when
V,,=2.7V-3.6V and VCCw=VC-wHIR. In the absence of
this high voltage. memory contents are protected against
word/byte writes. If word/byte write is attempted while
V CCwIVCCLVLK. status register bits SR.3 and SR.4 will be
set to “1”. Successful word/byte write requires for boot
blocks that WP# is Vt, and the corresponding block lockbit be cleared. In parameter and main blocks case. it must
be cleared the corresponding block lock-bit. If word/byte
write is attempted when the excepting above conditions,
SR. 1 and SR.4 will be set to “1”.
Word/Byte write setup (standard 40H
OI
Rev. 1.25
Page 16
SHARP
LHFl6JO4
4.8 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block erase process starts.
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to “1”).
RY/BY# will also transition to High Z. Specification
tWHR-,,, defines the block erase suspend latency.
When Block Erase Suspend command write to the GUI. if
block erase was finished. the device places read array
mode. Therefore. after Block Erase Suspend command
write to the CUI, Read Status Register command (70H)
has to write to CUI. then status register bit SR.6 should be
checked for places the device in suspend mode.
At this point. a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.9), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended. status register bit SR.7 will return to “0”
and the RY/BY# output will transition to VOL. However,
SR.6 will remain “1” to indicate block erase suspend
datus.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command,is written
:o the flash memory. the WSM will continue the block
:rase process. Status register bits SR.6 and SR.7 will
automatically clear and RY/BY# will return to VOL. After
.he Erase Resume command is written. the device
automatically outputs status register data when read (see
3gure 8). Vccw must remain at VC-WHt,z (the same
Vccw level used for block erase) while block erase is
xrspended. RP# must also remain at V,,. WP# must also
.emain at V,, or V,, (the same WP# level used for block
:rase). Block erase cannot resume until word/byte write
operations initiated during block erase suspend have
:ompleted.
14
4.9
Word/Byte
The Word/Byte Write Suspend command allows
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts. writing the Word/Byte Write Suspend command
requests that the WSIM suspend the Word/Byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to “1”). RY/BY# will also transition to
High Z. Specification tWHRZl
suspend latency.
When Word/Byte Write Suspend command write to the
CUI, if word/byte write was finished. the device places
read array mode. Therefore. after Word/Byte Write
Suspend command write to the CUI. Read Status Register
command (70H) has to write to CUI. then status register
bit SR.2 should be checked for places the device in
suspend mode.
At this point. a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte Write
Resume command is written to the flash memory. the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Word/Byte Write
Resume command is written. the device automatically
outputs status register data when read (see Figure 9).
Vccw must remain at VCCWHtjz (the same Vccw level
used for word/byte write) while in word/byte write
suspend mode. RP# must also remain at Vt,. WP# must
also remain at V,, or V,, (the same WP# level used for
word/byte write).
If the period of from Word/Byte Write Resume command
write to the CUI till Word/Byte Write Suspend command
write to the GUI be short and done again and again. write
time be prolonged.
Write Suspend Command
defines the word/byte write
f the period of from Block Erase Resume command write
o the GUI till Block Erase Suspend command write to the
XI be short and done again and again, erase time be
irolonged.
Rev. I.25
Page 17
LHFI 6JO4
15
4.10 Set Block and Permanent Lock-Bit
Commands
A
flexible block locking and unlocking scheme is enabled
via a combination of block lock-bits. a permanent lock-bit
and WP# pin. The block lock-bits and WP# pin gates
program and erase operations while the permanent lock-bit
gates block-lock bit modification. With the permanent
lock-bit not set, individual block lock-bits can be set using
the Set Block Lock-Bit command. The Set Permanent
Lock-Bit command. sets the permanent lock-bit. After the
permanent lock-bit is set, block lock-bits and locked block
contents cannot altered. See Table 5 for a summary of
hardware and software write protection options.
Set block lock-bit and-permanent lock-bit are executed by
1 two-cycle command sequence. The set block or
aermanent lock-bit setup along with appropriate block or
device address is written followed by either the set block
ock-bit confirm (and an address within the block to be
ocked) or the set permanent lock-bit confirm (and any
ievice address). The WSIM then controls the set lock-bit
Algorithm. After the sequence is written, the device
automatically outputs status resister data when read (see
:&tire IO). The CPU can detect the completion of the set
ock-bit event by analyzing the RY/BY# pin output or
tatus register bit SR.7.
Nhen the set lock-bit operation is complete, status register
bit SR.4 should be checked. If an error is detected, the
tatus register should be cleared. The CUI will remain in
ead status register mode until a new command is issued.
his two-step sequence of set-up followed by execution
nsures that lock-bits are not accidentally set. An invalid
‘et Block or Permanent Lock-Bit command will result in
tatus register bits SR.4 and SR.5 being set to “1”. Also,
:liable operations occur only when Vcc=2.7V-3.6V and
rCCW=vCCWHIR~
)ck-bit contents are protected against alteration.
i successful set block lock-bit operation requires that the
ermanent lock-bit be cleared. If it is attempted with the
ermanent lock-bit set. SR.1 and SR.4 will be set to “1”
?d the operation will fail.
In the absence of this high voltage,
4.1 I Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clea
Block Lock-Bits command. With the permanent lock-bi
not set. block lock-bits can be cleared using only the Clea
Block Lock-Bits command. If the permanent lock-bit i:
set, block lock-bits cannot cleared. See Table 5 for ;
summary of hardware and software write protectior
options.
Clear block lock-bits operation is executed by a two-cycle
command sequence. A clear block lock-bits setup is firs
written. After the command is written. the device
automatically outputs status register data when read (set
Figure 11). The CPU can detect completion of the cleai
block lock-bits event by analyzing the RY/BY# Pin outpu’
or status register bit SR.7.
When the operation is complete. status register bit SR.5
should be checked. If a clear block lock-bit error is
detected. the status register should be cleared. The GUI
will remain in read status register mode until another
command is issued.
This two-step sequence of set-up followed by execution
ensures that block lock-bits are not accidentally cleared.
An
invalid Clear Block Lock-Bits command sequence will
result in status register bits SR.4 and SR.5 being set to “1”.
Also, a reliable clear block lock-bits operation can only
occur when V,,=2.7V-3.6V and VCCW=VCCWHt,,. If a
clear block lock-bits operation is attempted -while
VCCWIVCCwtK, SR.3 and SR.5 will be set to “1”. In the
absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block
lock-bits operation requires that the permanent lock-bit is
not set. If it is attempted with the permanent lock-bit set.
SR.1 and SR.5 will be set to “1” and the operation will
fail.
If a clear block lock-bits operation is aborted due to Vccw
or V,, transitioninp out of valid range or RP# active
transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
values. Once the permanent lock-bit is set. it cannot be
cleared.
Rev. 1.25
Page 18
SHARP
LHFl6J04
. . 12 Block Locking by the WP#
his Boot Block Flash memory architecture features two
ardware-lockable boot blocks so that the kernel code for
le system can be kept secure while other blocks are
rogrammed or erased as necessary.
he lockable blocks are locked when WP#=V,: any
rogram or erase operation to a locked block will result in
Table 5. Write Protection Alternatives
16
an error. which will be reflected in the status register. FOI
top configuration. the top two boot blocks are lockable
For the bottom configuration. the bottom two boot block:
are lockable. If WP# is V,, and block lock-bit is not set
boot block can be programmed or erased normally (Unles:
Vccw is below V,,,,,). WP# is valid only two boo
blocks. other blocks are not affected.
‘1,
Set
Permanent >VcCWLK V,
Lock-Bit
‘VCCWLK ’
VI,
0 X X Clear Block Lock-Bits Enabled.
1
X X X Set Permanent Lock-Bit Disabled.
X X X Set Permanent Lock-Bit Disabled.
X X X Set Permanent Lock-Bit Enabled.
X
X Clear Block Lock-Bits Disabled.
Rev. 1.25
Page 19
SHARP
WSlMS 1 BESS
LHFl6504 17
Table 6. Status Register Definition
1 ECBLBS 1 WBWSLBS 1 VCCWS 1 WBWSS 1 DPS
R
7
SR.7 = WRITE STATE MACHINE STATUS (WSMS) Check RY/BY# or SR.7 to determine block erase. full chip
1 = Ready erase. word/byte write or lock-bit configuration completion.
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS (ECBLBS)
1 = Error in Block Erase. Full Chip Erase or Clear Block command sequence was entered.
Lock-Bits
0 = Successful Block Erase, Full Chip Erase or Clear
Block Lock-Bits
SR.4 = WORD/BYTE WRITE
STATUS (WBWSLBS)
1 = Error in Word/Byte Write or Set Block/Permanent
Lock-Bit only after Block Erase. Full Chip Erase, Word/Byte Write or
0 = Successful Word/Byte Write or Set Block/Permanent
Lock-Bit guaranteed to reports accurate feedback only when
jR.3 = Vccw STATUS (VCCWS)
1 = Vccw Low Detect, Operation Abort
0 = Vccw OK
jR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
iR. 1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-Bit, Permanent Lock-Bit and/or WP#
Lock Detected. Operation Abort
0 = Unlock
6 5
AND
SET LOCK-BIT
4
3
SR.6-0 are invalid while SR.7=“0”.
If both SR.5 and SR.l are “1”s after a block erase, full chip
erase or lock-bit configuration attempt. an improper
SR.3 does not provide a continuous indication of V,--w
level. The WSM interrogates and indicates the Vccw level
Lock-Bit Configuration command sequences. SR.3 is not
VCCW'VCCWHIR.
SR. 1 does not provide a continuous indication of permanent
and block lock-bit and WP# values. The WSM interrogates
the permanent lock-bit, block lock-bit and WP# only after
Block Erase. Full Chip Erase. Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
set. permanent lock-bit is set and/or WP# is V,,. Reading
the block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.
2 1
NOTES:
0
iR.0 = RESERVED FOR FUTURE ENHANCEMENTS CR) SR.0 is reserved for future use and should be masked out
when polling the status register.
Rev. 1.25
i
Page 20
r
LHFI 6JO4
IT’LL STATUS CHECK PRCCEDCRE
(-)
Check SR.,
,=Dev,ce Praect Dew?
Figure 5. Automated Block Erase Flowchart
Rev. 1.25
Page 21
SHARI=
LHFI 6504 19
Full Swnu
Check ,f Dewed
&i&j
FL’LL STATLr.5 CHECK PROCEDCRE
(F)
Cummand Scquencc
Standby
Standby
Standby
Command
Commen1s
Clwk SR.3
,=Vccw Erra Detect
Check SR.I
I=Dcr,ce Rara Detect
(All Bids are loclud)
Cixck SR.4.3
Both I=Co-nd Scqucncc Enor
Check SR.5
I=RII Clup Eras Eira
Full Ch,p Exlse
S”ccwf”l
Figure 6. Automated Full Chip Erase Flowchart
_1
Rev. 1.25
Page 22
r
LHFl6504
FL’LL STM-L’S CHECK PROCEDCRE
Read
Standby
Stmr Regwter Data
ChcckSR.7
,=WSMRendy
o=WSM Bury
Figure 7. Automated Word/Byte Write Flowchart
Rev. 1.25
Page 23
SHARP
Write DOH
Block Erase Ramcd
Wntc FFH
R,ad hay Dm
I
Figure 8. Block Erase Suspend/Resume Flowchart
Rev. 1.25
Page 24
SHARP
Wntc BOH
LHFl6JO4
22
Figure 9. Word/Byte Write Suspend/Resume Flowchart
Rev. 1.15
Page 25
SHARf=
r
r
LHFl6504
Cheek ,f Dared
FLZL STATUS CHECK PROCEDURE
Figure 10. Set Block and Permanent Lock-Bit Flowchart
Rev. 1.15
Page 26
SHARP
Red Swu
Rsgner
LHF 16JO4 24
SR.7=
.::5:-lr
FL’LL STATL’S CHECK PROCEDURE
(F)
0
Standby
Command
l=WSM Ready
C=WSM Busy
Commen,s
check SR.3
I=Vccw Fna rktcc1
Command Sequence
C,<Y Block Lmk-B,u
Standby
Swmfby
Figure 11. Clear Block Lock-Bits Flowchart
Check SR.J.5
Both ,=Command Scqurne Error
Rev. 1.25
Page 27
LHFl6JO4 25
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and ‘the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
:oggIe during system reset.
5.2 RYlBY# and WSM Polling
IY/BY# is an open drain output that should be connected
o V,, by a pull up resistor to provides a hardware method
If detecting block erase, full chip erase, word/byte write
md lock-bit configuration completion. It transitions low
tfter block erase. full chip erase. word/byte write or lock)it configuration commands and returns to VOH (while
cY/BY# is pull up) when the WSM has finished executin,o
he internal algorithm.
<Y/BY# can be connected to an interrupt input of the
ystem CPU or controller. It is active at all times. RY/BY#
s also High Z when the device is in block erase suspend
with word/byte write inactive), word/byte write suspend
)r reset modes.
5.3 Power Supply Decoupling
Flash memory power switchins characteristics require
careful device decoupling. System designers are interested
in three supply current issues: standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magitudes depend on the device outputs‘ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a O.lpF ceramic capacitor
connected between its V,, and GND and between its
Vccw and GND. These high-frequency. low inductance
capacitors should be placed as close as possible to package
leads. Additionally. for every eight devices. a 4.7pF
electrolytic capacitor should be placed at the array’s power
supply connection between Vcc and GND. The bulk
capacitor will overcome voltape slumps caused by PC
board trace inductance.
5.4 VCCW Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the Vccw
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V,, power bus. Adequate
Vccw supply traces and decoupling will decrease Vccw
voltage spikes and overshoots.
Power supply trace. The Vccw pin
5.5 Vcc, Vccw, RP# Transitions
Block erase, full chip erase. word/byte write and lock-bit
configuration are not guaranteed if V,-, falls outside of a
valid VCCWHt,z range, V,, falls outside of a valid 2.7V-
3.6V range. or RP##VtH. If Vccw error is detected, status
register bit SR.3 is set to “1” along with SR.4 or SR.5,
depending on the attempted operation. If RP# transitions
to V,, during block erase. full chip erase. word/byte write
or lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then. the operation will
abort and the device will enter reset mode. The aborted
operation may leave data partially altered. Therefore. the
command sequence must be repeated after normal
operation is restored. Device power-off or RP# transitions
to V,, clear the status register.
The CUI latches commands issued by system software and
is not altered by Vccw
actions. Its state is read array mode upon power-up. after
exit from reset mode or after Vcc transitions below V,,,.
or CE# transitions or WSIM
Rev. 1.25
Page 28
SHARP
LHFl6504 26
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erase. full chip erase. word/byte write or
lock-bit configuration during power transitions. Upon
power-up. the device is indifferent as to which power
supply WCCW or VCC) P
resets the CUI to read array mode at power-up.
A system designer must guard against spurious writes for
V,, voltages above V,,, when Vccw is active. Since
both WE# and CE# must be low for a command write,
driving either to V,, will inhibit writes. The GUI’s twostep command sequence architecture provides added level
of protection against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled while
RP#=Vl, regardless of its control inputs state.
owers-up first. Internal circuitry
_.
5.7 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
5.8 Data Protection Method
Noises having a level exceeding the limit specified in the
specification may be generated under specific operating
conditions on some systems. Such noises, when induced
onto WE# signal or power supply. may be interpreted as
false commands, causing undesired memory updating. To
protect the data stored in the flash memory against
unwanted overwriting, systems operating with the flash
memory should have the following write protect designs.
as appropriate:
1) Protecting data in specific block
When a lock bit is set. the corresponding block (includes
the 2 boot blocks) is protected against overwriting. By
setting a WP# to low, only the 2 boot blocks can be
protected against overwriting. By using this feature. the
flash memory space can be divided into the program
section (locked section) and data section (unlocked
section). The permanent lock bit can be used to prevent
false block bit setting. For further information on
settinS/resettinp lock-bit, refer to the specification. (See
chapter-l.lOand-l.11.)
2) Data protection through Vccw
When the level of V,--w is lower than VCCWLK (lockout
voltage), write operation on the flash memory is disabled.
All blocks are locked and the data in the blocks are
completely write protected. For the lockout voltage. refer
to the specification. (See chapter 6.2.3.)
3) Data protection through RP#
When the RP# is kept low during read mode. the flash
memory will be reset mode. then write protecting all
blocks, When the RP# is kept low during power up and
power down sequence such as voltage transition, write
operation on the flash memory is disabled, write
protecting all blocks. For the details of RP# control, refer
to the specification. (See chapter 5.6 and 6.2.7.)
Rev. 1.75
Page 29
LHFl6JO4
27
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase.
Full Chip Erase, Word/Byte Write
and Lock-Bit Configuration ._........... -40°C to +SS’C(t)
Storage Temperature
During under Bias _..............._.............. -4Q”C to +85”C
During non Bias _................_.............. -65°C to +125”C
Voltage On Any Pin
(except V,, and vccw) . . . ..__.... -0.5V to V,,+O.5V(‘)
V,, Supply Voltage . . . . . . . . .._..................... -0.2V to +4.6V(*)
Vccw Supply Voltage . . . . . .._._.._._.......... -02V to +13.OV(*v3)
Output Short Circuit Current . . . . . . .._...__................ 1OOmA(J)
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings on/x Operation be?.ond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” ma! affect device
reliability.
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on V,, and Vccw pins. During transitions.
this level may undershoot to -2.OV for periods <20ns.
Maximum DC voltage on input/output pins are
V,,+0.5V which. during transitions, may overshoot to
V,-+2.OV for periods <?Ons.
3. Maximum DC voltage on Vccw may overshoot to
+13.OV for periods <20ns. Applying 12V+O.3V to
V,,, during erase/write can only be done for a
maximum
of 1000 cycles on
each block. Vccw may be
connected to 12Va.3V for a total of 80 hours
maximum.
4. Output shorted for no more than one second. No more
than one output shorted at a time.
I
6.2 Operating Conditions
Symbol Parameter
TA
V,,
Operating Temperature
V,, Supply Voltage (2.7V-3.6V) 2.7
6.2.1 CAPACITANCE(I)
Symbol
,CIN
1 C,”
Input Capacitance
1 Output Capacitance
NO;:
1 1. Sampled, not 100% tested.
Parameter
Temperature and Vcc Operating Conditions
Min. Max. Unit Test Condition
-40 +85 “C Ambient Temperature
3.6
T,=+25”C, f=IMHz
TYP.
Max.
7 10
9 l? i
Unit
PF
PF
V
1
Condition
v,,=o.ov
v,“T=o.ov
Rev. 1.25
Page 30
LHF 16JO4 28
.2.2 AC INPUT/OUTPUT TEST CONDITIONS
I,~~z2~@T-
AC test inputs are driven at ?.7V for a Logic “1” and O.OV for a Logic “0”. Input timing be_eins. and output hung ends, ~1 1.35V.
input rise and fall limes (10% IO 9tYZ) <IO ns.
Figure 12. Transient Input/Output Reference Waveform for V,,=2.7V-3.6V
lN91-l
Test Configuration Cauacitance Loading Value
Test Configuration
V,e2.7V-3.6V
C,(pF)
50
OUT
Figure 13. Transient Equivalent Testing Load Circuit
I
Rev. 1.25
Page 31
52.3 DC CHARACTERISTICS
LHF16JO4
DC Characteristics
Conditions
-I
Rev. 1.35
I
Page 32
SHARP
LHFI 6504
DC Characteristics (Continued)
Parameter
"OH2
“CCWLK
"CCWHI
"CCWH2
"LKO
30TES:
All currents are in RMS unless otherwise noted. Typical values at nominal V,, voltage and T,=+25”C.
:: I ccws and IccEs are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the
device‘s current draw is the sum of Iccws or I,,,, and ICCR or Iccw. respectively.
8. Includes RY/BY#.
. . Block erases, full chip erase, word/byte writes and lock-bit configurations are inhibited when V,,wIV,,wLK, and not
guaranteed in the range between VCCwLK(max.) and VCcwH,(min.), between VccwH,(max.) and V~cwB#nin.) and
above Vr-cwB2(max.).
The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more
than 300ns while read mode.
. About all of pin except describe Test Conditions, CMOS level inputs are either V&O.2V or GND*O.?V, TIL level
inputs are either V,, or VI,.
Sampled. not 100% tested.
Applying 12VkO.3V to Vccw during erase/write can only be done for a maximum of 1000 cycles on each block. Vccw
may be connected to 12Vtio.3V for a total of 80 hours maximum.
Output High Voltage
(CMOS)
.
Vccw Lockout during Normal 4,7
Operations
Vccw during Block Erase. Full Chip
Erase, Word/Byte Write or Lock-Bit
Configuration Operations
Vccw during Block Erase. Full Chip
Erase. Word/Byte Write or Lock-Bit
Configuration Operations
Vcc Lockout Voltage
7
8
0.85
Vr--
“cc
-0.4
1.0
2.7 3.6
11.7 12.3
2.0
V
V
V
V
V
V
Test Conditions
V,,=V,c Min.
IO,=-2smA
Vcc=Vcc Min.
I,,=- lOOpA
30
Rev. 1.25
Page 33
LHF16504
62.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(‘)
,[EHOZ
tGLOX
tGHOZ
tOH
tFVOV
‘FL02
tlzr “I CE# to BYTE# High or Low 3.4 5 ns
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tErqv-tGLQv after the falling edge of CE# without impact on tF, &.
3. Sampled. not 100% tested.
4. If BYTE# transfer during reading cycle. exist the regulations separately.
CE# High to Output in High Z 3
OE# to Output in Low Z 3 0 ns
OE# Highto Output in High. Z
Output Hold from Address, CE# or OE# Change, Whichever
Occurs Fist
BYTE# to Output Delay 3
BYTE# Low to Output in High Z
3
3 0 ns
3
40 ns
15 ns
90
25 ns
ns
Rev. 1.25
Page 34
LHFl6504
32
VIH
rDDRESSES(A)
VIL
WE#(W)
V’H r------
hLJ
VOH
lATA(D/Q)
DQ&Qu)
VOL
Slandby
HIGH Z
Device
Address Seleclion
Address Stable
kLQV
kryx
kLQXD-+
tAVQV
tcLQV
Data Valid
l
___________
__---------
lOHb--4
I
h
Figure 14. AC Waveform for Read Operations
Rev. 1.25
Page 35
SHARP
r
VIH
ADDRESSES
VIL
Standby
Device
Address Selection Data Valid
r
Address Stable
__________.
VIH
CENE)
VU
VIH
OE#(G)
VU
VIH
BYTEWFI
VU
VOH
DATA(D/Q, HIGH Z
-.
(DQo--DQI)
VOL
VOH
)ATA(D/Q) HIGH Z
DQs-DQ1.s)
VOL
tELQV
4
,
P
tAVQV
kLFv
h
b
tGLQV
, ______-----
________..- -
kLQX
4
r
c
-:;:;:-:::(~;>j HIGH Z
4
a
tFLQ2
HIGH Z
Figure 15. BYTE# timing Waveform
Rev. I.25
Page 36
SHARP
LHFl6504
6.25 AC CHARACTERISTICS - WRITE OPERATIONS(l)
34
NOTES:
1. Read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are
the same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled. not 100% tested.
3. Refer to Table 4 for valid A,, and D,, for block erase, full chip erase. word/byte write or lock-bit configuration.
4. V,-,, should be held at VCCWHt,2 until determination of block erase. full chip erase, word/byte write or lock-bit
configuration success (SR. l/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.35
Page 37
r
LHFl6504
ADDRESSES(A)
DATACDIQ)
vCCW(~ VCCWLK
NOTES:
1. VCc power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 16. AC Waveform for WE#-Controlled Write Operations
Rev. 1.25
Page 38
LHFl6504 36
62.6 ALTERNATIVE CE#-CONTROLLED WRIT ES(‘)
V,,=?.lV-3.6V, T,=-40°C to +85”C
Sym. 1
I ~~
t AVAV
tPHEL
tWLEL WE# Setup to CE# Going Low
Write Cycle Time
RP# High Recovery to CE# Going Low
Parameter Notes Min.
I I ,T,Y
2
YU IlS
1
0 ns
-,.
1 Max Unit
I I
P
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold. and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table J for valid A,, and D,, for block erase, full chip erase. word/byte write or lock-bit configuration.
4. V,,w should be held at VCCwH,,, , until determination of block erase, full chip erase, word/byte write or lock-bit
configuration success (SR. l/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.25
1
Page 39
SHARP
ADDRESSES(A)
OE#G)
DATA(DlQ)
BYTES(F)
RYIBYMR) (“1”
(SR.7)
LHFl6JO4
1 2 3 4
---v-v
37
5 6
“CCW(“) VCCWLK
VIL ‘““““““““““““”
NOTES:
1. Vcc power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data.
4. Automated erase or program delay.
5. Read statos register data.
6. Write Read Array command.
Figure 17. AC Waveform for CE#-Controlled Write Operations
Rev. 1.25
Page 40
SHARP
6.27 RESET OPERATIONS
RY/BY#(R)(“I”)
RY/BY#(R) (“1”)
High Z
(SR.7) VoL
RFW’)
High Z
(SR.7) VOL
(“0”)
_.
RP#(P)
2.7V
(“0”)
VIH
VIL
VIH
VI1
(B)Reset During Block Erase, Full Chip Erase. Word/Byte Write or Lock-Bit Configuration
LHFl6JO4
(A)Reser During Read Array Mode
k
38
RP#(P)
I
VIH
VIL
(C)RP# rising Timing
Figure 18. AC Waveform for Reset Operation
Reset AC Specifications
Sym. Parameter Notes
tPLPH
RP# Pulse Low Time
RP# Low to Reset during Block Erase, Full Chip Erase,
tPLRZ
i %VPH
Word/Byte Write or Lock-Bit Configuration
V,, 2.7V to RP# High
2
172
2.3
Min. Max.
100
30
100 ns
Unit
lFi
PS
NOTES:
1. If RP# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing,
the reset will complete within 1OOns.
2. A reset time, tptt v,
valid. Refer to A 8
3. When the device power-up, holding RP# low minimum 1OOns is required after Vcc
is required from the later of RY/BY#(SR.7) going High Z(“1”) or RP# going high until outputs are
Characteristics - Read-Only Operations for tpHQV.
has been in predefined range and also
has been in stable there.
Rev. 1.25
Page 41
LHFl6JO4
2.8
BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE AND LOCK-BIT
CONFIGURATION PERFORMANCE(3)
Set Lock-Bit Time
WHQVJ Clear Block Lock-Bits Time 2 1 5
EH0V.l
WHFCZI
EHRZl
wHRz2
EHRZ2
OTES:
Typical values measured at TA=+25”C and Vcc=3.0V, Vccw-
Word/Byte Write Suspend Latency Time to 4
Read
Block Erase Suspend Latency Time to
Read
6 15 6
4 16 30 16
-3 OV or 12.OV. Assumes corresponding lock-bits are not
0.69
1.5
30
set. Subject to change based on device characterization.
Excludes system-level overhead.
Sampled but not 100% tested.
A latency time is required from issuing suspend command(WE# or CE# going high) until RYIBY# going High Z or
going ” 1”.
S
PS
PS
SK7
Rev. 1.25
Page 42
LHF16J04
_____________.______~~..~~~~~~~~~~~~~~..-.--~~~-.--------------------.~~~~~---~.~~~~~~~~~~~~-~~~~-~~~~~~.-~~~~~~~~~~.~-~~~~~------..---------------.------------
_____.__-_-___._____~~---~~~~~.~--~~~~~.~.--~~~...-------...~...-----~~~~~~~~~~~~~~~~~~..~~~~~~~~~..~~~~.~.~.~~~~~~-.~~~~~~.~~~~~...~~~~~~-.~----~~~~--------~.~
..---.~..~~...--...~~~~.~...--~~~~.-----.-----------.----~----------~~~~~~~~~.~~~~~~~~~~~~~~~~~~~~~~~~~.~.~~~~~~-~~~~~~~~~~~~~~~--.~~-~~~~--------~---------~~~
.------.---.-------_~~...------~..-----------------------------------~~~~~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~~.~-~~~~~~~-~~~~~~~~~~~~~~~..-~~~~~~~.~.--~~~~~~~~~~~~~-~
.______________.--__.~~~~~..-~.~~~~..~-~~.~~~~-~~~~~~~~~~~~~.~~~~.~~~~~~~~~~~~~~~~~~~~~~~~~~.-~~~~~~~~~~.~~~~~~-~~~~~~.~--~~~~~~~~--~~~~~.~-~---~~~~~~~~~~~~~~~~
SHARP
7 Package and packing specification
1. Package Outline Specification
Refer to drawing No.AAl 14 2
2. Markings
2 - 1. Marking contents
(1) Product name : LH28F160BJHE-TTL90
(2) Company name : SHARP
( 3 ) Date code
(Example) 2 YY WW xxx Indicates the product was manufactured
(4) “JAPAN” is marked on the package when both wafer and assembly processes are
2 - 2. Marking layout
Refer drawing No. AA1 1 4 2
(This layout does not define the dimensions of marking character
- -in the WWth week of 19YY.
Denotes the production ref.code (l-3)
Denotes the production week.
(Ol,OZ, 03, . . . . . 52,53)
Denotes the product ion year.
(Lower two digit of the year.)
l
Denotes the product ion ref .code
(No marking , A , B , C )
done in Japan , indicating the country of origin.
40
and marking position.)
3. Packing Specification (Dry packing for surface mount packages)
Dry packing is used for the purpose of maintaining IC qua1
packages on the PCB (Printed Circuit Board).
When the epoxy resin which is used for plastic packages is
humidity, it may absorb 0.15% or more of its weight in moisture. If the surface
mount type package for a relatively Iarge chip absorbs a large amount of moisture
between the epoxy resin and insert material (e.g. chip, lead frame) this moisture
may suddenly vaporize into steam when the entire package is heated during the
soldering process (e.g. VPS). This causes expansion and results in separation
between the resin and insert material, and sometimes cracking of the package.
This dry packing is designed to prevent the above problem from occurring in
surface mount packages.
3 - 1. Packing Materials
Material Name Material Specificaiton Purpose
Tray Conductive plastic (50devices/tray) Fixing of device
Upper cover tray Conductive plastic
Laminated aluminum bag Aluminum polyethylene (lbag/case) Drying of device
Desiccant Silica gel Drying of device
P P band Polypropvlene (3pcs/case) Fixing of tray
.
Inner case Card board (500device/case) Packaging of device
Label Paper Indicates part number, quantity
Outer case Card board Outer packing of tray
(Devices shall be placed into a tray in the same direction.)
(ltray/case) Fixing of device
ity after mounting
stored at high
and date of manufacture
Page 43
LHF16J04
SHARP
3- 2. Outline dimension of tray
Refer to attached drawing
Storage and Opening of Dry Packing
4.
4-l. Store under conditions shown below before opening the dry packing
( 1) Temperature range : 5-40°C
(2) Humidity : 80% RH or less
4-2. Notes on opening the dry packing
(1) Before opening the dry packing, prepare a working table which is
grounded against ESD and use a grounding strap.
(2) The tray has been treated to be conductive or anti-static. If the
device is transferred to another tray, use a equivalent tray.
_.
4-3. Storage after opening the dry packing
Perform the following to prevent absorption of moisture after opening.
(1) After opening the dry packing, store the ICs in an environment with a
temperature of 5--25°C and a relative humidity of 60% or less and
mount ICs within 72 hours after opening dry packing.
41
4-4. Baking (drying) before mounting
(1) Baking is necessary
(A) If the humidity indicator in the desiccant becomes pink
(B) If the procedure in section 4-3 could not be performed
(2) Recommended baking conditions
If the above conditions (A) and (B) are applicable, bake it before
mounting The recommended conditions are 16-24 hours at 120°C.
Heat resi stance tray is used for shipping tray.
5. Surface Mount Conditi
Please perform
quality.
5-1.Solderin.g conditions(The following conditions are valid only for one time soldering.)
Mounting Method Temperature and Duration
Reflow soldering Peak temperature of 230°C or less,
(air)
I
Manual soldering
(soldering iron)
I
ons
the following conditions when mounting ICs not to deteriorate IC
duration of less than 15 seconds.
200°C or over,durat ion of less than 40 seconds.
I
Measurement Point
IC package
5 - 2. Conditions for removal of residual flux
(I) Ultrasonic washing power : 25 Watts/liter or less
(2) Washing time
(3) Solvent temperature
: Total 1 minute maximum
: 15-40°C
Page 44
SHARP
LHF16J04
42
LH28FlIUBJHE-TTL90
YYWW xxx
24
?
I
/SEE DETAIL A
!
DETAIL A
P-
.
s1
d
6
i-
PKG.BASE PLANE
-7r
@;z :
NOTES : Marking specification when “JAPAN” is marked.
aim !J-b-Ii2
(AME ; TSOP4S-P-1220 LEAD FINISH j PLATING NOTE Plastic body dimensions do not include burr
DRAWING NO. ~ AA1142
r J APANJ ~~i2tj~~Z5%$~;a>7-3~f~
1 TIN-LEAL $$@$ If~~71/:7~-~~~~~It,,i~pgb8c~l~~I~.
%W i
UNIT ~ mm
of resin.
Page 45
SHARP
LHF16j04
43
I
_,
24
/ I
/ii. DE:;, A
LH28F16OElJHE-TT'*"
ILJU
sHARfz#
ZYYWW xxx
!
19. 0 -co. 1
DETA,L A
7 Lnl
25
I -
1
:
/
k
T --I
j2E.E : r J APANJ ~~Z;b~f~~\%-&j-a>~-S’ft~
NOTES :Marking specification when “JAPAN” is not marked.
#fi ~
JAME! TSOP48-P-1220 LEAD FINISH ~ PLATING NOTE Plastic body dimensions do not include burr
DRAWING NO. : AA1142 IJNIT / mm
!J - r&t 1 TIN-LEN @j%
kg{2 ;
~j~f7?Jfyf-:i#f$f&ii, Jiy @i&$flki!$ o
of resin.
Page 46
SHARP
-
;
-
.
LHFlGJO4
44
J
3
;
:
:
I
P
:
0
3
;
n
-
<
-
9
7
i.8
NAME/TSOP48-1220TCM-RH
DRAWING NO.
~ CV756 / UNIT ~
I 1;
I...?-
g/c :
___
--.
25.0*0.3*4=100i.0.3
I
35.
NOTE
mm 1
El $3
__
=..I
-..a
Page 47
SHARP
LHF16J04
45
Gupplementary data)
Recommended mounting conditions for two time reflow soldering .
Product name(Package) LH28Fl6OBJHE-TTL9O(TSOP48-P-1220)
Packing specification - Tray (Dry packing)
Mounting method Reflow soldering (Air)
Reflow soldering conditions Peak temperature of 230°C or less.
Measurement point
1
LHF16.J04
200°C or over, duration of less than 40 seconds.
Preheat temperature of 125-150”C,durat ion of less
than 180 seconds. Temperature increase rate of
l--4“C/second.
IC package surface
Storage conditions
Note
Recommended Reflow SolderinglAir) Temperature Profile
After opening the dry packing, store the ICs in
an environment with a temperature of 5-25°C and
a relative humidity of 60% or less.
If doing reflow soldering twice,do the first
reflow soldering within 72 hours after opening
dry packing and do the second reflow soldering
within 72 hours after the first reflow soldering.
If the above storage conditions are not
applicable, bake it before reflow soldering.
The recommended conditions are 16-24 hours
at 120°C.
(Heat resistance tray is used for shipping tray.)
rature
(Less than
40 seconds)
Temperature increase
rate 1 -4%/second
I
Peak tempe
\
Time
(NO. 990928-X15)
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