Datasheet LH28F160BGHR-TTL12, LH28F160BGHR-TTL10, LH28F160BGHR-BTL10, LH28F160BGHE-TTL12, LH28F160BGHE-TTL10 Datasheet (Sharp)

- 1 -

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

PRELIMINARY

LH28F160BG-TL/BGH-TL

16 M-bit (1 MB x 16) Smart 3

Flash Memories

LH28F160BG-TL/BGH-TL

DESCRIPTION

The LH28F160BG-TL/BGH-TL flash memories with
Smart 3 technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F160BG-TL/
BGH-TL can operate at V

CC and VPP = 2.7 V.

Their low voltage operation capability realizes
longer battery life and suits for cellular phone
application. Their boot, parameter and main-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for portable terminals and personal
computers. Their enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F160BG-TL/BGH-TL offer two levels of
protection : absolute protection with V

PP at GND,

selective hardware boot block locking. These
alternatives give designers ultimate control of their
code security needs.

FEATURES

• Smart 3 technology
– 2.7 to 3.6 V V

CC

– 2.7 to 3.6 V or 12 V VPP

• High performance read access time
LH28F160BG-TL10/BGH-TL10
– 100 ns (2.7 to 3.6 V)
LH28F160BG-TL12/BGH-TL12
– 120 ns (2.7 to 3.6 V)

• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read

• SRAM-compatible write interface

• Optimized array blocking architecture
– Two 4 k-word boot blocks
– Six 4 k-word parameter blocks
– Thirty-one 32 k-word main blocks
– Top or bottom boot location

• Enhanced cycling capability
– 100 000 block erase cycles

• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I

CC

in static mode

• Automated word write and block erase
– Command user interface
– Status register

• ETOX

TM

∗

V nonvolatile flash technology

• Packages
– 48-pin TSOP Type I (TSOP048-P-1220)

Normal bend/Reverse bend

– 60-ball CSP (FBGA060/048-P-0811)

∗ ETOX is a trademark of Intel Corporation.

VERSIONS BIT CONFIGURATION OPERATING TEMPERATURE

LH28F160BG-TL 1 MB x 16 0 to +70°C
LH28F160BGH-TL 1 MB x 16 – 25 to +85°C
LH28F160BV-TL

∗

2 MB x 8/1 MB x 16 0 to +70°C

LH28F160BVH-TL

∗

2 MB x 8/1 MB x 16 – 40 to +85°C

COMPARISON TABLE

∗ Refer to the datasheet of LH28F160BV-TL/BVH-TL.

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 2 -

PIN CONNECTIONS

NC

1

A

B

C

D

E

NC2NC

A14 A13

34

A11

WE#

WP#

A17

5

A10

NC

RP#

VPP

A18

A15

6

A12

A9

RY/BY#

A19

A7

A16

7

DQ15

DQ6

DQ12

DQ10

DQ1

GND

8

DQ14

DQ5

VCC

DQ11

DQ2

F

G

NC NC NC NC NC NC

A5A2A6A3A4A1OE#A0DQ8

NC

9

DQ7

DQ13

DQ4

DQ3

DQ9

DQ0

NC10NC11NC

12

GND

CE#

H

A

8

(FBGA060/048-P-0811)

60-BALL CSP

48-PIN TSOP (Type I)

(TSOP048-P-1220)

A15
A14
A13
A12
A11
A10

A9
A8

NC

RY/BY#

WE#

RP#

V

PP

WP#

A

19

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
NC
GND
DQ

15

DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A

0

TOP VIEW

NOTE :

Reverse bend available on request.

PRELIMINARY

BLOCK ORGANIZATION

This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in

Fig. 1.

Boot Blocks : The two boot blocks are intended to

replace a dedicated boot PROM in a micro­processor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the V

PP, RP# and

WP# pins.

Parameter Blocks : The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques, the byte-rewrite functionality of
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.

Main Blocks : The reminder is divided into main
blocks for data or code storage. Each 16 M-bit
device contains thirty-one 32 k words (32 768
words) blocks.

LH28F160BG-TL/BGH-TL

INPUT

BUFFER

BUFFER

OUTPUT

MULTIPLEXER

VCC

CE#

RP#

OE#

IDENTIFIER

REGISTER

COMMAND

USER

INTERFACE

WRITE
STATE

MACHINE

PROGRAM/ERASE
VOLTAGE SWITCH

I/O

LOGIC

STATUS

REGISTER

DATA

REGISTER

DATA

COMPARATOR

X

DECODER

Y

DECODER

RY/BY#
VPP

VCC
GND

DQ0-DQ15

INPUT

BUFFER

ADDRESS

LATCH

ADDRESS
COUNTER

WP#

WE#

OUTPUT

A0-A19

BOOT BLOCK 0

BOOT BLOCK 1

PARAMETER BLOCK 0

PARAMETER BLOCK 1

PARAMETER BLOCK 2

PARAMETER BLOCK 3

PARAMETER BLOCK 4

PARAMETER BLOCK 5

MAIN BLOCK 0

MAIN BLOCK 1

MAIN BLOCK 29

MAIN BLOCK 30

31

32 k-WORD

MAIN BLOCKS

Y GATING

BLOCK DIAGRAM

- 3 -

- 4 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

SYMBOL TYPE NAME AND FUNCTION

A0-A19 INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.

CE# INPUT

CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. Block erase or word write with V

IH <

RP# < VHH produce spurious results and should not be attempted.

OE# INPUT OUTPUT ENABLE : Gates the device’s outputs during a read cycle.

WE# INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.

WP# INPUT

WRITE PROTECT : Master control for boot blocks locking. When VIL, locked boot
blocks cannot be erased and programmed.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase or word write). RY/BY#-high-impedance
indicates that the WSM is ready for new commands, block erase is suspended, and
word write is inactive, word write is suspended, or the device is in deep power-down
mode.
BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or
writing words. With V

PP ≤ VPPLK, memory contents cannot be altered. Block erase and

word write with an invalid V

PP (see Section 6.2.3 "DC CHARACTERISTICS") produce

spurious results and should not be attempted.
DEVICE POWER SUPPLY : 2.7 to 3.6 V. Do not float any power pins. With V

CC ≤

VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid
V

CC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results

and should not be attempted.

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not internal connected; recommend to be floated.

PIN DESCRIPTION

DQ0-DQ15

INPUT/

OUTPUT

RP# INPUT

RY/BY# OUTPUT

V

PP SUPPLY

V

CC SUPPLY

PRELIMINARY

LH28F160BG-TL/BGH-TL

1 INTRODUCTION

This datasheet contains LH28F160BG-TL/BGH-TL
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160BG-TL/
BGH-TL flash memories documentation also
includes ordering information which is referenced in
Section 7.

1.1 New Features

Key enhancements of LH28F160BG-TL/BGH-TL
Smart 3 flash memories are :

• 2.7 V V

CC and VPP Write/Erase Operation

• Enhanced Suspend Capabilities

• Boot Block Architecture

Note following important differences :

•V

PPLK has been lowered to 1.5 V to support

2.7 V block erase and word write operations.
Designs that switch V

PP off during read

operations should make sure that the V

PP

voltage transitions to GND.

• To take advantage of Smart 3 technology, allow
V

PP connection to 2.7 V or 12 V.

1.2 Product Overview

The LH28F160BG-TL/BGH-TL are high-performance
16 M-bit Smart 3 flash memories organized as
1 024 k-word of 16 bits. The 1 024 k-word of data
is arranged in two 4 k-word boot blocks, six 4 k­word parameter blocks and thirty-one 32 k-word
main blocks which are individually erasable in­system. The memory map is shown in Fig. 1.

V

PP at 2.7 V eliminates the need for a separate 12 V

converter, while V

PP = 12 V maximizes block erase

and word write performance. In addition to flexible
erase and program voltages, the dedicated V

PP pin

gives complete data protection when V

PP ≤ VPPLK.

A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.

A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (3.0 V
V

CC and VPP), independent of other blocks. Each

block can be independently erased 100 000 times.
Block erase suspend mode allows system software
to suspend block erase to read data from, or write
data to any other block.

Writing memory data is performed in word
increments of the device’s 32 k-word blocks
typically within 55 µs, 4 k-word blocks typically
within 60 µs (3.0 V V

CC and VPP). Word write

suspend mode enables the system to read data
from, or write data to any other flash memory array
location.

The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 4.9 for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
V

IH.

The status register indicates when the WSM’s block
erase or word write operation is finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal

- 5 -

- 6 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or word write.
RY/BY#-High-impedance indicates that the WSM is
ready for a new command, block erase is
suspended (and word write is inactive), word write
is suspended, or the device is in deep power-down
mode.

The access time is 100 ns or 120 ns (t

AVQV) at the

V

CC supply voltage range of 2.7 to 3.6 V over the

temperature range, 0 to +70°C (LH28F160BG-TL)/
– 25 to +85°C (LH28F160BGH-TL).

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I

CCR current is 3 mA at

2.7 V V

CC.

When CE# and RP# pins are at V

CC, the ICC

CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t

PHQV) is

required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t

PHEL)

from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 7 -

0
1
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

4 k-Word Boot Block

4 k-Word Boot Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block

32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block

Top Boot

FFFFF
FF000
FEFFF
FE000
FDFFF
FD000
FCFFF
FC000
FBFFF
FB000
FAFFF
FA000
F9FFF
F9000
F8FFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
1
0

32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block

32 k-Word Main Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block

4 k-Word Boot Block
4 k-Word Boot Block

Bottom Boot

FFFFF
F8000
F7FFF
F0000
EFFFF
E8000
D7FFF
D0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000

Fig. 1 Memory Map

BLOCK CONFIGURATION VERSIONS

Top Boot

LH28F160BG-TTL
LH28F160BGH-TTL

Bottom Boot

LH28F160BG-BTL
LH28F160BGH-BTL

NOTES :

PRELIMINARY

LH28F160BG-TL/BGH-TL

2 PRINCIPLES OF OPERATION

The LH28F160BG-TL/BGH-TL Smart 3 flash
memories include an on-chip WSM to manage
block erase and word write functions. It allows for :
fixed power supplies during block erasure and word
write, and minimal processor overhead with RAM­like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 1 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby and output disable operations.

Status register and identifier codes can be
accessed through the CUI independent of the V

PP

voltage. High voltage on VPP enables successful
block erasure and word writing. All functions
associated with altering memory contents—block
erase, word write, status and identifier codes—are
accessed via the CUI and verified through the
status register.

Commands are written using standard micro­processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase
and word write. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or
outputs status register data.

Interface software that initiates and polls progress
of block erase and word write can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read/write data from/to blocks other than that which
is suspended. Word write suspend allows system

software to suspend a word write to read data from
any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V

PP power supply

switchable (available only when memory block
erases or word writes are required) or hardwired to
V

PPH1/2. The device accommodates either design

practice and encourages optimization of the
processor-memory interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase or word
write command sequences, provides protection
from unwanted operations even when high voltage
is applied to V

PP. All write functions are disabled

when V

CC is below the write lockout voltage VLKO

or when RP# is at VIL. The device’s blocks locking
capability provides additional protection from
inadvertent code or data alteration by gating erase
and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in­system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes or status register independent of the V

PP

voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power­down mode, the device automatically resets to read
array mode. Five control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,
RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the

- 8 -

- 9 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ

0-DQ15) control and when active drives

the selected memory data onto the I/O bus. WE#
must be at V

IH and RP# must be at VIH or VHH.

Fig. 9 illustrates read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins (DQ

0-DQ15) are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ

0-DQ15 outputs are placed

in a high-impedance state independent of OE#. If
deselected during block erase or word write, the
device continues functioning, and consuming active
power until the operation completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t

PHQV is required

after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

During block erase or word write modes, RP#-low
will abort the operation. RY/BY# remains low until
the reset operation is complete. Memory contents
being altered are no longer valid; the data may be
partially erased or written. Time t

PHWL is required

after RP# goes to logic-high (V

IH) before another

command can be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase or
word write modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
not occur because the flash memory may be
providing status information instead of array data.
SHARP’s flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.

3.5 Read Identifier Codes

The read identifier codes operation outputs the
manufacture code and device code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms.

Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.

FFFFF

00002
00001

00000

Reserved for

Future Implementation

Device Code

Manufacture Code

- 10 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 10 and
Fig. 11 illustrate WE# and CE# controlled write
operations.

4 COMMAND DEFINITIONS

When the VPP ≤ VPPLK, read operations from the
status register, identifier codes, or blocks are
enabled.

Device operations are selected by writing specific
commands into the CUI. Table 2 defines these
commands.

Table 1 Bus Operations

MODE NOTE RP# CE# OE# WE#

ADDRESS

V

PP

DQ

0-15

RY/BY#

Read 1, 2, 3, 8

VIHor V

HH

V

IL

V

IL

V

IH

XXD

OUT

X

Output Disable 3

VIHor V

HH

V

IL

V

IH

V

IH

X X High Z X

Standby 3

VIHor V

HH

V

IH

XXXXHigh Z X
Deep Power-Down 4 VIL XXXXXHigh Z High Z
Read Identifier Codes 8

VIHor V

HH

V

IL

V

IL

V

IH

See Fig. 2

X(

NOTE 5)

High Z

Write 3, 6, 7, 8

VIHor V

HH

V

IL

V

IH

V

IL

XXDINX

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

IL or VIH for control pins and addresses, and

V

PPLK or VPPH1/2 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for V

PPLK and VPPH1/2 voltages.

3. RY/BY# is V

OL when the WSM is executing internal

block erase or word write algorithm. It is high-impedance
when the WSM is not busy, in block erase suspend
mode (with word write inactive), word write suspend
mode or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

6. V

IH < RP# < VHH produce spurious results and should

not be attempted.

7. Refer to Table 2 for valid D

IN during a write operation.

8. Don’t use the timing both OE# and WE# are V

IL.

- 11 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE SECOND BUS CYCLE

REQ’D.

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Word Write 2 5, 6 Write WA

40H or 10H

Write WA WD

Block Erase and

1 5 Write X B0H

Word Write Suspend
Block Erase and

1 5 Write X D0H

Word Write Resume

Table 2 Command Definitions

(NOTE 7)

NOTES :

1. Bus operations are defined in Table 1.

2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased.
WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 5 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever
goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read
operations access manufacture and device codes. See
Section 4.2 for read identifier code data.

5. If the block is boot block, WP# must be at V

IH or RP#

must be at V

HH to enable block erase or word write

operations. Attempts to issue a block erase or word write
to a boot block while WP# is V

IH or RP# is VIH.

6. Either 40H or 10H is recognized by the WSM as the
word write setup.

7. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.

- 12 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

4.1 Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase or word write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend or Word Write
Suspend command. The Read Array command
functions independently of the V

PP voltage and

RP# can be V

IH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture and device codes
(see Table 3 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V

PP voltage and RP# can be

V

IH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 3 Identifier Codes

4.3 Read Status Register Command

The status register may be read to determine when
a block erase or word write is complete and
whether the operation completed successfully. It
may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is
written. The status register contents are latched on

the falling edge of OE# or CE#, whichever occurs.
OE# or CE# must toggle to V

IH before further reads

to update the status register latch. The Read Status
Register command functions independently of the
V

PP voltage. RP# can be VIH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 5). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing
multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V

PP voltage. RP# can

be V

IH or VHH. This command is not functional

during block erase or word write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFFFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.

CODE ADDRESS DATA

Manufacture Code 00B0H

00000H

Device Code (Top Boot) 0068H

00001H

Device Code (Bottom Boot) 0069H

00001H

- 13 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

The CUI remains in read status register mode until
a new command is issued.

This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V

CC =

V

CC1 and VPP = VPPH1/2. In the absence of this

high voltage, block contents are protected against
erasure. If block erase is attempted while V

PP ≤

V

PPLK, SR.3 and SR.5 will be set to "1". Successful

block erase for boot blocks requires that the
corresponding if set, that WP# = V

IH or RP# = VHH.

If block erase is attempted to boot block when the
corresponding WP# = V

IL or RP# = VIH, SR.1 and

SR.5 will be set to "1". Block erase operations with
V

IH < RP# < VHH produce spurious results and

should not be attempted.

4.6 Word Write Command

Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.

Reliable word writes can only occur when V

CC =

V

CC1 and VPP = VPPH1/2. In the absence of this

high voltage, memory contents are protected
against word writes. If word write is attempted while
V

PP ≤ VPPLK, status register bits SR.3 and SR.4 will

be set to "1". Successful word write for boot blocks
requires that the corresponding if set, that WP# =
V

IH or RP# = VHH. If word write is attempted to

boot block when the corresponding WP# = V

IL or

RP# = V

IH, SR.1 and SR.4 will be set to "1". Word

write operations with V

IH < RP# < VHH produce

spurious results and should not be attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V

OH.

Specification t

WHRH2 defines the block erase

suspend latency.

At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to V

OL.

However, SR.6 will remain "1" to indicate block
erase suspend status.

- 14 -

PRELIMINARY

The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V

OL. After the Erase

Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). V

PP must remain at VPPH1/2 (the

same V

PP level used for block erase) while block

erase is suspended. RP# must also remain at V

IH

or VHH (the same RP# level used for block erase).
WP# must also remain at V

IL or VIH (the same

WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.

4.8 Word Write Suspend Command

The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to high-impedance. Specification
t

WHRH1 defines the word write suspend latency.

At this point, a Read Array command can be written
to read data from location other than that which is
suspended. The only other valid commands while
word write is suspended are Read Status Register
and Word Write Resume. After Word Write Resume
command is written to the flash memory, the WSM
will continues the word write process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to V

OL. After the Word Write

Resume command is written, the device

automatically outputs status register data when read
(see Fig. 6). V

PP must remain at VPPH1/2 (the same

V

PP level used for word write) while in word write

suspend mode. RP# must also remain at V

IH or

V

HH (the same RP# level used for word write). WP#

must also remain at V

IL or VIH (the same WP# level

used for word write).

4.9 Block Locking

This Boot Block flash memory architecture features
two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure
while other blocks are programmed or erased as
necessary.

4.9.1 VPP = VIL FOR COMPLETE PROTECTION

The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device.

4.9.2 WP# = VIL FOR BLOCK LOCKING

The lockable blocks are locked when WP# = VIL;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
boot blocks are lockable. For the bottom
configuration, the bottom two boot blocks are
lockable. Unlocked blocks can be programmed or
erased normally (Unless V

PP is below VPPLK).

4.9.3 BLOCK UNLOCKING

WP# = VIH or RP# =VHH unlocks all lockable
blocks.

These blocks can now be programmed or erased.

WP# or RP# controls all block locking and V

PP

provides protection against spurious writes. Table 4
defines the write protection methods.

LH28F160BG-TL/BGH-TL

- 15 -

PRELIMINARY

Table 4 Write Protection Alternatives

OPERATION

VPP

RP# WP#

EFFECT

Block Erase

VIL X X All Blocks Locked.

or

VIL X All Blocks Locked.

Word Write

> V

PPLK

VHH X All Blocks Unlocked.

VIH

VIL

2 Boot Blocks Locked.

VIH All Blocks Unlocked.

LH28F160BG-TL/BGH-TL

76543210

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready
0 = Busy

SR.6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended
0 = Block Erase in Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error in Block Erase
0 = Successful Block Erase

SR.4 = WORD WRITE STATUS (WWS)

1 = Error in Word Write
0=

Successful Word Write

SR.3 = VPP STATUS (VPPS)

1=V

PP Low Detect, Operation Abort

0=VPP OK

SR.2 = WORD WRITE SUSPEND STATUS (WWSS)

1 = Word Write Suspended
0 = Word Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = WP# or RP# Lock Detected, Operation Abort
0 = Unlock

SR.0 =

RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES :

Check RY/BY# or SR.7 to determine block erase or word
write completion. SR.6-0 are invalid while SR.7 =

"0".

If both SR.5 and SR.4 are

"1"s after a block erase attempt, an

improper command sequence was entered.

SR.3 does not provide a continuous indication of V

PP level.

The WSM interrogates and indicates the V

PP level only after

Block Erase or Word Write command sequences. SR.3 is not
guaranteed to reports accurate feedback only when V

PP ≠

V

PPH1/2.

The WSM interrogates the WP# and RP# only after Block
Erase or Word Write command sequences. It informs the
system, depending on the attempted operation, if the WP# is
not V

IH, RP# is not VHH.

SR.0 is reserved for future use and should be masked out
when polling the status register.

Table 5 Status Register Definition

WSMS ESS ES WWS VPPS WWSS DPS R

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 16 -

Block Erase

Complete

Start

Write 20H,

Block Address

Write D0H,

Block Address

Read

Status Register

0

SR.7 =

1

Full Status

Check if Desired

Repeat for subsequent block erasures.
Full status check can be done after each block erase or after

a sequence of block erasures.
Write FFH after the last block erase operation to place device

in read array mode.

BUS

OPERATION

Write

Write

Read

Standby

COMMAND

Erase Setup

COMMENTS

Data = 20H
Addr = Within Block to be Erased

Data = D0H
Addr = Within Block to be Erased

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

V

PP Range Error

1

0

SR.1 =

Device Protect Error

1

0

BUS

OPERATION

COMMAND

COMMENTS

Standby

Standby

Check SR.1
1 = Device Protect Detect

Check SR.5
1 = Block Erase Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.

If error is detected, clear the status register before attempting
retry or other error recovery.

No

Suspend

Block Erase

Yes

Suspend Block

Erase Loop

Erase

Confirm

Block Erase

Successful

SR.4, 5 =

Command Sequence

Error

1

0

SR.5 =

Block Erase

Error

1

0

Standby

Check SR.3
1 = V

PP Error Detect

Standby

Check SR.4, 5
Both 1 = Command Sequence Error

Fig. 3 Automated Block Erase Flowchart

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 17 -

Word Write

Complete

Start

Write 40H or 10H,

Address

Write Word

Data and Address

Read

Status Register

0

SR.7 =

1

Full Status

Check if Desired

Repeat for subsequent word writes.
SR full status check can be done after each word write or after

a sequence of word writes.
Write FFH after the last word write operation to place device

in read array mode.

BUS

OPERATION

Write

Write

Read

Standby

COMMAND

Setup

Word Write

COMMENTS

Data = 40H or 10H
Addr = Location to be Written

Data = Data to be Written
Addr = Location to be Written

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

V

PP Range Error

1

0

SR.1 =

Device Protect Error

1

0

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1
1 = Device Protect Detect

SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.

If error is detected, clear the status register before attempting
retry or other error recovery.

No

Suspend

Word Write

Yes

Suspend Word

Write Loop

Word Write

Word Write

Successful

SR.4 =

Word Write Error

1

0

Standby

Check SR.3
1 = V

PP Error Detect

Standby

Check SR.4
1 = Data Write Error

Fig. 4 Automated Word Write Flowchart

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 18 -

Block Erase

Resumed

Start

Write B0H

Read

Status Register

0

SR.7 =

1

Word Write

BUS

OPERATION

Write

Read

Standby

Standby

COMMAND

Erase

Suspend

COMMENTS

Data = B0H
Addr = X

Status Register Data
Addr = X

Check SR.7
1 = WSM Ready
0 = WSM Busy

Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed

Erase

Resume

SR.6 =

Done?

Write D0H

Block Erase

Completed

Write FFH

Read

Array Data

1

0

No

Yes

Write

Data = D0H
Addr = X

Read

or Word

Write?

Read

Read Array Data Word Write Loop

Fig. 5 Block Erase Suspend/Resume Flowchart

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 19 -

Word Write Resumed

Start

Write B0H

Read

Status Register

0

SR.7 =

1

Write FFH

BUS

OPERATION

Write

Read

Standby

Standby

COMMAND

Word Write

Suspend

COMMENTS

Data = B0H
Addr = X

Status Register Data
Addr = X

Check SR.7
1 = WSM Ready
0 = WSM Busy

Check SR.2
1 = Word Write Suspended
0 = Word Write Completed

Read Array

SR.2 =

Read

Array Data

Done

Reading

Write D0H

Word Write

Completed

Write FFH

Read

Array Data

1

0

No

Yes

Write

Read

Write

Word Write

Resume

Data = FFH
Addr = X

Read array locations other
than that being written.

Data = D0H
Addr = X

Fig. 6 Word Write Suspend/Resume Flowchart

PRELIMINARY

LH28F160BG-TL/BGH-TL

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three­line control provides for :

a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention

will not occur.

To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.

5.2 RY/BY#, Block Erase and Word
Write Polling

RY/BY# is a output that provides a hardware
method of detecting block erase and word write
completion. It transitions low after block erase or
word write commands and returns to high­impedance when the WSM has finished executing
the internal algorithm.

RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also high-impedance when the
device is in block erase suspend (with word write
inactive), word write suspend or deep power-down
modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current

issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its V

CC and GND and between its VPP

and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between V

CC

and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.

5.4 VPP Trace on Printed Circuit Boards

Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the V

PP power supply

trace. The V

PP pin supplies the memory cell current

for word writing and block erasing. Use similar trace
widths and layout considerations given to the V

CC

power bus. Adequate VPP supply traces and
decoupling will decrease V

PP voltage spikes and

overshoots.

5.5 VCC, VPP, RP# Transitions

Block erase and word write are not guaranteed if
V

PP falls outside of a valid VPPH1/2 range, VCC falls

outside of a valid V

CC1 range, or RP# ≠ VIH or VHH.

If V

PP error is detected, status register bit SR.3 is

set to "1" along with SR.4 or SR.5, depending on
the attempted operation. If RP# transitions to V

IL

during block erase or word write, RY/BY# will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation
may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP#

- 20 -

- 21 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

transitions to VIL clear the status register.

The CUI latches commands issued by system
software and is not altered by V

PP or CE#

transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep power­down or after V

CC transitions below VLKO.

After block erase or word write, even after V

PP

transitions down to VPPLK, the CUI must be placed
in read array mode via the Read Array command if
subsequent access to the memory array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against
accidental block erasure or word writing during
power transitions. Upon power-up, the device is
indifferent as to which power supply (V

PP or VCC)

powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.

A system designer must guard against spurious
writes for V

CC voltages above VLKO when VPP is

active. Since both WE# and CE# must be low for a
command write, driving either to V

IH will inhibit

writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.

WP# provides additional protection from inadvertent
code or data alteration. The device is disabled
while RP# = V

IL regardless of its control inputs

state.

5.7 Power Consumption

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.

In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solid­state storage can consume negligible power by
lowering RP# to V

IL standby or sleep modes. If

access is again needed, the devices can be read
following the t

PHQV and tPHWL wake-up cycles

required after RP# is first raised to V

IH. See Section

6.2.4 through 6.2.6 "AC CHARACTERISTICS

- READ-ONLY and WRITE OPERATIONS" and
Fig. 9, Fig. 10 and Fig. 11 for more information.

- 22 -

PRELIMINARY

LH28F160BG-TL/BGH-TL

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

∗

Operating Temperature

• LH28F160BG-TL
During Read, Block Erase and
Word Write

............................

0 to +70°C

(NOTE 1)

Temperature under Bias

.............

– 10 to +80°C

• LH28F160BGH-TL
During Read, Block Erase and
Word Write

........................

– 25 to +85°C

(NOTE 2)

Temperature under Bias

.............

– 25 to +85°C

Storage Temperature

........................

– 65 to +125°C

Voltage On Any Pin

(except VCC, VPP, and RP#)..– 0.5 V to VCC+0.5 V

(NOTE 3)

VCC Supply Voltage

.................

– 0.2 to +3.9 V

(NOTE 3)

VPP Update Voltage during

Block Erase and
Word Write

..................

– 0.2 to +14.0 V

(NOTE 3, 4)

RP# Voltage

........................

– 0.5 to +14.0 V

(NOTE 3, 4)

Output Short Circuit Current

...............

100 mA

(NOTE 5)

∗

WARNING : Stressing the device beyond the

"

Absolute Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.

NOTES :

1. Operating temperature is for commercial product defined

by this specification.

2. Operating temperature is for extended temperature

product defined by this specification.

3. All specified voltages are with respect to GND. Minimum

DC voltage is – 0.5 V on input/output pins and – 0.2 V on
V

CC and VPP pins. During transitions, this level may

undershoot to – 2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins and V

CC is VCC+0.5 V

which, during transitions, may overshoot to V

CC+2.0 V

for periods < 20 ns.

4. Maximum DC voltage on V

PP and RP# may overshoot

to +14.0 V for periods < 20 ns.

5. Output shorted for no more than one second. No more

than one output shorted at a time.

NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.

SYMBOL

PARAMETER NOTE MIN. MAX. UNIT VERSIONS

TA Operating Temperature 1

0

+70

˚

C LH28F160BG-TL

–25

+85

˚C LH28F160BGH-TL

VCC1 VCC Supply Voltage 2.7 3.6 V

6.2 Operating Conditions

NOTE :

1. Test condition : Ambient temperature

NOTE :

1. Sampled, not 100% tested.

SYMBOL PARAMETER TYP. MAX. UNIT CONDITION

CIN Input Capacitance 7 10 pF VIN = 0.0 V
C

OUT Output Capacitance 9 12 pF VOUT = 0.0 V

6.2.1 CAPACITANCE

(NOTE 1)

TA = +25˚C, f = 1 MHz

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 23 -

6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

TEST POINTSINPUT OUTPUT

1.35

1.35

2.7

0.0

Fig. 7 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.6 V

AC test inputs are driven at 2.7 V for a logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing
ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.

DEVICE

UNDER

TEST

C

L Includes Jig

Capacitance

RL = 3.3 kΩ

C

L

OUT

1.3 V

1N914

Fig. 8 Transient Equivalent Testing

Load Circuit

TEST CONFIGURATION CL (pF)

V

CC = 2.7 to 3.6 V 50

Test Configuration Capacitance Loading Value

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 24 -

SYMBOL

PARAMETER NOTE

V

CC = 2.7 to 3.6 V

UNIT

TEST

TYP. MAX.

CONDITIONS

I

LI Input Load Current 1 ±1 µA

V

CC = VCC Max.

VIN = VCC or GND

I

LO Output Leakage Current 1 ±10 µA

V

CC = VCC Max.

VOUT = VCC or GND
CMOS Inputs

25 50 µA V

CC = VCC Max.

ICCS VCC Standby Current 1, 3, 6

CE# = RP# = V

CC±0.2 V

TTL Inputs

0.2 2 mA V

CC = VCC Max.

CE# = RP# = VIH

ICCD VCC Deep Power-Down Current 1 5 10 µA

RP# = GND±0.2 V
IOUT (RY/BY#) = 0 mA
CMOS Inputs
V

CC = VCC Max.

25 mA CE# = GND

f = 5 MHz

ICCR VCC Read Current 1, 5, 6

I

OUT = 0 mA

TTL Inputs
V

CC = VCC Max.

30 mA CE# = GND

f = 5 MHz
IOUT = 0 mA

ICCW VCC Word Write Current 1, 7

17 mA V

PP = 2.7 to 3.6 V

12 mA VPP = 12.0±0.6 V

ICCE VCC Block Erase Current 1, 7

17 mA V

PP = 2.7 to 3.6 V

12 mA VPP = 12.0±0.6 V

I

CCWS VCC Word Write or Block Erase

1, 2 6 mA CE# = V

IH

ICCES Suspend Current
IPPS

VPP Standby or Read Current 1

±2 ±15 µA V

PP ≤ VCC

IPPR 10 200 µA VPP > VCC
IPPD VPP Deep Power-Down Current 1

0.1 5 µA RP# = GND±0.2 V, V

PP ≤ VCC

14 150 µA RP# = GND±0.2 V, VPP > VCC

IPPW VPP Word Write Current 1, 7

12 40 mA V

PP = 2.7 to 3.6 V

30 mA VPP = 12.0±0.6 V

IPPE VPP Block Erase Current 1, 7

11 35 mA V

PP = 2.7 to 3.6 V

20 mA VPP = 12.0±0.6 V

I

PPWS VPP Word Write or Block Erase

1 10 200 µA V

PP = VPPH1/2

IPPES Suspend Current

6.2.3 DC CHARACTERISTICS

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 25 -

SYMBOL

PARAMETER NOTE

V

CC = 2.7 to 3.6 V

UNIT

TEST

MIN. MAX.

CONDITIONS

VIL Input Low Voltage 7 –0.5 0.8 V
VIH Input High Voltage 7 0.7VCC VCC+0.3 V

V

OL Output Low Voltage 3, 7 0.4 V

V

CC = VCC Min.

IOL = 2.0 mA

V

OH1 Output High Voltage (TTL) 3, 7 0.85VCC V

V

CC = VCC Min.

IOH = –2.0 mA

V

OH2 Output High Voltage (CMOS) 3, 7 0.5 V

V

CC = VCC Min.

IOH = –100 µA

V

PPLK

VPP Lockout Voltage during

4, 7 1.5 V

Normal Operations

V

PPH1

VPP Voltage during Word Write or

2.7 3.6 V

Block Erase Operations

V

PPH2

VPP Voltage during Word Write or

11.4 12.6 V

Block Erase Operations

VLKO VCC Lockout Voltage 1.3 V
V

HH RP# Unlock Voltage 8, 9 11.4 12.6 V

Block Erase and Word Write
for Boot Blocks

6.2.3 DC CHARACTERISTICS (contd.)

NOTES :

1. All currents are in RMS unless otherwise noted. Typical
values at V

CC = 3.0 V, VPP = 3.0 V and TA = +25˚C.

These currents are valid for all product versions
(packages and speeds).

2. I

CCWS and ICCES are specified with the device de-

selected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of I

CCWS or

I

CCES and ICCR or ICCW, respectively.

3. Includes RY/BY#.

4. Block erases and word writes are inhibited when V

PP ≤

V

PPLK, and not guaranteed in the range between VPPLK

(max.) and VPPH1 (min.), between VPPH1 (max.) and
V

PPH2 (min.), and above VPPH2 (max.).

5. Automatic Power Saving (APS) reduces typical I

CCR to

3 mA at 2.7 V V

CC in static operation.

6. CMOS inputs are either V

CC±0.2 V or GND±0.2 V. TTL

inputs are either V

IL or VIH.

7. Sampled, not 100% tested.

8. Boot block erases and word writes are inhibited when
the corresponding RP# = V

IH or WP# = VIL. Block erase

and word write operations are not guaranteed with V

IH <

RP# < V

HH and should not be attempted.

9. RP# connection to a V

HH supply is allowed for a

maximum cumulative period of 80 hours.

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 26 -

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS

(NOTE 1)

• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –25 to +85 ˚C

VERSIONS

LH28F160BG-TL10 LH28F160BG-TL12

LH28F160BGH-TL10 LH28F160BGH-TL12

UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Read Cycle Time 100 120 ns
tAVQV Address to Output Delay 100 120 ns
tELQV CE# to Output Delay 2 100 120 ns
tPHQV RP# High to Output Delay 10 10 µs
tGLQV OE# to Output Delay 2 45 50 ns
tELQX CE# to Output in Low Z 3 0 0 ns
tEHQZ CE# High to Output in High Z 3 45 50 ns
tGLQX OE# to Output in Low Z 3 0 0 ns
tGHQZ OE# High to Output in High Z 3 20 25 ns

t

OH

Output Hold from Address, CE# or

30 0 ns

OE# Change, Whichever Occurs First

NOTES :

1. See AC Input/Output Reference Waveform (Fig. 7) for maximum allowable input slew rate.

2. OE# may be delayed up to t

ELQV-tGLQV after the falling edge of CE# without impact on tELQV.

3. Sampled, not 100% tested.

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 27 -

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

(DQ

0-DQ15)

RP# (P)

V

CC

Standby

Device

Address Selection Data Valid

Address Stable

t

AVAV

tEHQZ

tGHQZ

High Z

Valid Output

t

GLQV

tELQV

tGLQX

tELQX

tAVQV

tPHQV

High Z

t

OH

VIL

VOH

VOL

VIH

VIH

VIH

VIH

VIH

VIL

VIL

VIL

VIL

Fig. 9 AC Waveform for Read Operations

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 28 -

6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS

(NOTE 1)

• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –25 to +85 ˚C

VERSIONS

LH28F160BG-TL10 LH28F160BG-TL12

LH28F160BGH-TL10 LH28F160BGH-TL12 UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

tAVAV Write Cycle Time 100 120 ns
tPHWL RP# High Recovery to WE# Going Low 2 10 10 µs
tELWL CE# Setup to WE# Going Low 0 0 ns
tWLWH WE# Pulse Width 50 50 ns
tPHHWH RP# VHH Setup to WE# Going High 2 100 100 ns
tSHWH WP# VIH Setup to WE# Going High 2 100 100 ns
tVPWH VPP Setup to WE# Going High 2 100 100 ns
tAVWH Address Setup to WE# Going High 3 50 50 ns
tDVWH Data Setup to WE# Going High 3 50 50 ns
tWHDX Data Hold from WE# High 0 0 ns
tWHAX Address Hold from WE# High 0 0 ns
tWHEH CE# Hold from WE# High 0 0 ns
tWHWL WE# Pulse Width High 30 30 ns
tWHRL WE# High to RY/BY# Going Low 100 100 ns
tWHGL Write Recovery before Read 0 0 ns
tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns
tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns
tQVSL WP# VIH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

NOTES :

1. Read timing characteristics during block erase and word
write operations are the same as during read-only
operations. Refer to Section 6.2.4 "AC CHARAC-
TERISTICS" for read-only operations.

2. Sampled, not 100% tested.

3. Refer to Table 2 for valid A

IN and DIN for block erase or

word write.

4. V

PP should be held at VPPH1/2 (and if necessary RP#

should be held at V

HH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 29 -

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

VIL

VIH

High Z

V

IH

VIH

VIH

VIL

VIL

VIL

VOL

VIL

VIH

VHH

VIL

VPPLK

VPPH1/2

VIH

VIL

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

VPP (V)

RY/BY# (R)

A

IN AIN

tAVAV tAVWH

tELWL

tWHEH

tWHGL

tWHWL tWHQV1/2/3/4

tWLWH
tDVWH

tWHDX

Valid

SRD

t

PHWL

tWHRL

tVPWH

tQVVL

DIN

DIN

High Z

DIN

WP# (S)

VIH

VIL

tPHHWH

tQVPH

tSHWH

tQVSL

tWHAX

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Fig. 10 AC Waveform for WE#-Controlled Write Operations

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 30 -

6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS

(NOTE 1)

•VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or – 25 to +85˚C
VERSIONS

LH28F160BG-TL10 LH28F160BG-TL12

LH28F160BGH-TL10 LH28F160BGH-TL12

UNIT

SYMBOL

PARAMETER NOTE MIN. MAX. MIN. MAX.

t

AVAV

Write Cycle Time 100 120 ns

t

PHEL

RP# High Recovery to CE# Going Low 2 10 10 µs

t

WLEL

WE# Setup to CE# Going Low 0 0 ns

t

ELEH

CE# Pulse Width 70 70 ns
tPHHEH RP# VHH Setup to CE# Going High 2 100 100 ns
tSHEH WP# VIH Setup to CE# Going High 2 100 100 ns
tVPEH VPP Setup to CE# Going High 2 100 100 ns
tAVEH Address Setup to CE# Going High 3 50 50 ns
tDVEH Data Setup to CE# Going High 3 50 50 ns
tEHDX Data Hold from CE# High 0 0 ns
tEHAX Address Hold from CE# High 0 0 ns
tEHWH WE# Hold from CE# High 0 0 ns
tEHEL CE# Pulse Width High 25 25 ns
tEHRL CE# High to RY/BY# Going Low 100 100 ns
tEHGL Write Recovery before Read 0 0 ns
tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns
tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns
tQVSL WP# VIH Hold from Valid SRD, RY/BY# High 2, 4 0 0 ns

NOTES :

1. In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 2 for valid A

IN and DIN for block erase or

word write.

4. V

PP should be held at VPPH1/2 (and if necessary RP#

should be held at V

HH) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 31 -

VIL

VIH

High Z

V

IH

VIH

VIH

VIL

VIL

VIL

VOL

VIL

VIH

VHH

VIL

VPPLK

VPPH1/2

VIH

VIL

ADDRESSES (A)

WE# (W)

OE# (G)

CE# (E)

DATA (D/Q)

RP# (P)

VPP (V)

RY/BY# (R)

WP# (S)

V

IH

VIL

AIN AIN

tAVAV tAVEH

tWLEL

tEHWH

tEHGL

tEHEL tEHQV1/2/3/4

Valid

SRD

t

PHEL

tEHRL

tVPEH

tQVVL

DIN

DIN

High Z

DIN

tPHHEH

tQVPH

tSHEH

tEHAX

tELEH

tDVEH

tEHDX

tQVSL

(NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6)

NOTES :

1. VCC power-up and standby.

2. Write block erase or word write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Fig. 11 AC Waveform for CE#-Controlled Write Operations

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 32 -

6.2.7 RESET OPERATIONS

RP# (P)

V

IL

VIH

High Z

V

IH

High Z

VOL

VIL

VOL

RY/BY# (R)

RY/BY# (R)

RP# (P)

V

IL

(C) RP# Rising Timing

VIH

2.7 V

VIL

RP# (P)

V

CC

(A) Reset During Read Array Mode

(B) Reset During Block Erase or Word Write

tPLPH

tPLRH

tPLPH

tVPH

Fig. 12 AC Waveform for Reset Operation

Reset AC Specifications

(NOTE 1)

NOTES :

1. These specifications are valid for all product versions
(packages and speeds).

2. If RP# is asserted while a block erase or word write
operation is not executing, the reset will complete within
100 ns.

3. A reset time, t

PHQV, is required from the latter of RY/BY#

or RP# going high until outputs are valid.

4. When the device power-up, holding RP#-low minimum
100 ns is required after V

CC has been in predefined

range and also has been in stable there.

VCC = 2.7 to 3.6 V

SYMBOL

PARAMETER NOTE

MIN. MAX.

UNIT

t

PLPH

RP# Pulse Low Time

100 ns

(If RP# is tied to VCC, this specification is not applicable)
tPLRH RP# Low to Reset during Block Erase or Word Write 2, 3 22 µs
t

VPH

VCC2.7 V to RP# High 4 100 ns

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 33 -

6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE

(NOTE 3, 4)

•VCC = 2.7 to 3.6 V, TA = 0 to +70°C or –25 to +85˚C
VPP = 2.7 to 3.6 V VPP = 12.0±0.6 V

SYMBOL

PARAMETER NOTE

MIN.

TYP.

(NOTE 1)

MAX. MIN.

TYP.

(NOTE 1)

MAX.

UNIT

tWHQV1

Word Write Time

32 k-Word Block

255 15µs

tEHQV1 4 k-Word Block

260 30µs

Block Write Time

32 k-Word Block

2 1.8 0.6 s

4 k-Word Block

2 0.3 0.2 s

tWHQV2

Block Erase Time

32 k-Word Block 2 1.2 0.7 s

tEHQV2 4 k-Word Block 2 0.5 0.5 s

t

WHRH1

Word Write Suspend Latency Time to Read 7.5 8.6 6.5 7.5 µs

tEHRH1
tWHRH2

Erase Suspend Latency Time to Read 19.3 23.6 11.8 15 µs

t

EHRH2

NOTES :

1. Typical values measured at TA = +25˚C and VCC = 3.0 V,
V

PP = 3.0 V/VCC = 3.0 V, VPP = 12.0 V. Subject to

change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed
versions.

4. Sampled, not 100% tested.

PRELIMINARY

LH28F160BG-TL/BGH-TL

- 34 -

VALID OPERATIONAL COMBINATIONS

VCC= 2.7 to 3.6 V

OPTION ORDER CODE

50 pF load,

1.35 V I/O Levels

1 LH28F160BGXX-XTL10 100 ns
2 LH28F160BGXX-XTL12 120 ns

7 ORDERING INFORMATION

LH28F160BG

(H)

ETT-L10

Device Density
160 = 16 M-bit

Access Speed (ns)
10 : 100 ns (2.7 to 3.6 V)
12 : 120 ns (2.7 to 3.6 V)

Package
E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend
R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend
B = 60-ball CSP (FBGA060/048-P-0811)

Architecture
B = Boot Block

Power Supply Type
G = Smart 3 Technology

Limited Voltage Option
TL = 2.7 to 3.6 V VCC Only

Block Locate Option
T = Top Boot
B = Bottom Boot

Operating Temperature

Blank = 0 to +70°C

H = –25 to +85°C

Product line designator for all SHARP Flash products

PACKAGING

1.2

0.1

±0.2

±0.05

±0.1

MAX.

±0.2

TYP.

25

48

24

1

12.0

48

_

0.2

0.5

0.1

0.10

±0.08

20.0

±0.3

18.4

0.125

M

0.125

19.0

±0.1

1.0

±0.1

Package base plane

48 TSOP (TSOP048-P-1220)

PACKAGING

S

M

0.30 AB
SCD

M

0.15

S

C

D

A

B

1.2

MAX.

0.35

±0.05

0.1 S

0.45

±0.03

1.1

TYP.

0.8

TYP.

0.4

TYP.

1.2

TYP.

0.8

TYP.

0.4

TYP.

0.1 S

∗

0.4

TYP.

12

H

A

1

8.0

0

+

0.2

11.0

0

+

0.2

∗Land hole diameter

for ball mounting

/ /

60 CSP (FBGA060/048-P-0811)