Datasheet LH28F016SAT-70 Datasheet (Sharp)

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Page 1

LH28F016SA

16M (1M × 16, 2M × 8) Flash Memory

FEATURES

• User-Configurable x8 or x16 Operation

• User-Selectable 3.3 V or 5 V V

• 70 ns Maximum Access Time

• 0.43 MB/sec Write Transf er Rate

• 100,000 Erase Cycles per Block

• 32 Independently Lockable Blocks (64K)

• Revolutionary Architecture

– Pipelined Command Execution – Write During Erase – Command Superset of

Sharp LH28F008SA

• 50 µA (Typ.) I

in CMOS Standby

• 1 µA (Typ.) Deep Power-Down

• State-of-the-Art 0.55 µm ETOX™ Flash

Technology

• 56-Pin, 1.2 mm × 14 mm × 20 mm

TSOP (Type I) Package

3/5

NC A

A A

A A A A

RP A A

A A

GND

A A A A A A A

3 4

13 44 DQ

15 16

TOP VIEW56-PIN TSOP

54 OE 53

RY/BY

DQ DQ

50



DQ GND

48 47

DQ DQ

43 V

GND

42 41

DQ DQ

38 37

V DQ

36 35 DQ 34 DQ

BYTE

15 7

14 6

13 5 12 4

11 3 10 2

1 8 0

Figure 1. TSOP Configuration

28F016SAT-1

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LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

DQ8 - DQ

OUTPUT BUFFER

OUTPUT

MULTIPLEXER

DQ0 - DQ

OUTPUT BUFFER

CSR

ESRs

ID

DATA

COMPARATOR

INPUT

BUFFER

DATA

QUEUE

REGISTERS

PAGE

BUFFERS

INPUT

BUFFER

CUI

I/O

LOGIC

3/5 BYTE

CE CE

OE WE WP RP

0 1

A0 - A

INPUT

BUFFER

ADDRESS

QUEUE

LATCHES

ADDRESS COUNTER

Y-DECODER

X-DECODER

. . .

64KB BLOCK 0

Y GATING/SENSING

. . .

64KB BLOCK 1

. . .

64KB BLOCK 30

64KB BLOCK 31

WSM

PROGRAM/

ERASE

VOLTAGE 

SWITCH

Figure 2. LH28F016SA Block Diagram (Architectural Evolution Includes Page Buffers,

Queue Registers and Extended Status Registers)

RY/BY

3/5

GND

28F016SAT-2

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16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8

INPUT

mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A input buffer is turned off when BYTE is high).

A1 - A

- A

- DQ7INPUT/OUTPUT

- DQ15INPUT/OUTPUT

, CE

INPUT

» INPUT

WORD-SELECT ADDRESSES: Select a word within one 64K block. A

- A15 selects

1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are latched during Data Writes.

BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are

latched during Data Writes, Erase and Lock-Block operations.

LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.

Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated when the chip is de-selected or the outputs are disabled.

HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs

array, buffer or identifier data in the appropriate Read mode; not used for Status register reads. Floated when the chip is de-selected or the outputs are disabled.

CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and

sense amplifiers. With either CE

or CE

high, the device is de-selected and power

consumption reduces to Standby levels upon completion of any current Data-Write or Erase operations. Both CE

, CE

must be low to select the device. All timing

specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE

RESET/POWER-DOWN: RP

or CE

. The first rising edge of CE

low places the device in a Deep Power-Down state. All

or CE

disables the device.

circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from Deep Power-Down, a recovery time of 400 ns

= 5.0 V ± 0.25 V) is required to allow these circuits to power-up. When RP

goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared).

INPUT

WE INPUT

»/BY

OPEN DRAIN

OUTPUT

OUTPUT ENABLE: Gates device data through the output buffers when low. The

outputs float to tri-state off when OE

NOTE: CE

overrides OE

», and OE » overrides WE.

» is high.

WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers

and Address Queue Latches. WE is active low, and latches both address and data (command or array) on its rising edge.

READY/BUSY: Indicates status of the internal WSM. When low, it in dicates that th e

WSM is busy performing an operation. RB

»/BY » high indicates that the WSM is ready

for new operations (or WSM has completed all pending operations), or Erase is Suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE

» or CE

, CE

are high), except if a RY

»/BY

Pin Disable command is issued.

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LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

PIN DESCRIPTION (Continued)

SYMBOL TYPE NAME AND FUNCTION

WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for

each block. When WP is low, those locke d blocks as reflected by the B lock-Lock Status

WP INPUT

BYTE INPUT

» INPUT

3/5

bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high, all blocks can be Written or Erased regardless of the state of the lock-bits. The WP input buffer is disabled when RP

BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or output

on DQ byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer. Address A1, then becomes the lowest order address.

3.3/5.0 V OLT SELECT: 3/5» high configures internal circuits for 3.3 V operation.

3/5» low configures internal circuits f or 5.0 V operation.

NOTES:

device. There is a significant delay from 3/5» » Switching to valid data.

- DQ7, and DQ

Reading the array with 3/5» high in a 5.0 V system could damage the

- DQ15 float. Address A0 selects between the high and low

» transitions low (deep power-down mode).

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.

SUPPLY

INTRODUCTION

Sharp’s LH28F016SA 16M Flash Memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and communication products. With innovative capabilities, 5 V single v oltage operation and very high read/write performance, the LH28F016SA is also the ideal choice for designing embedded mass storage flash memory systems.

The LH28F016SA is a v ery high density , highest performance non-volatile read/write solution for solid-state storage applications. Its symmetrically blocked architecture (100% compatible with the LH28F008SA 8M Flash memory), extended cycling, low power 3.3 V operation, very fast write and read performance and selective bloc k locking provide a highly fle xible memory component suitable for high density memory cards. Resident Flash Arrays and PCMCIA-ATA Flash Drives. The LH28F016SA’s dual read voltage enables the design of memory cards which can interchangeably be read/written in 3.3 V and 5.0 V systems. Its x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option enables bundling of executable application software in a Resident Flash Array or memory card. Manuf actured on Sharp’s 0.55 µm ETOX™ process technology, the

ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing

words/bytes/pages into the flash array.

DEVICE POWER SUPPLY (3.3 V ±0.3 V, 5.0 V ±0.5 V): Do not leave any

power pins floating.

NO CONNECT: No internal connection to die, lead may be driven or left floating.

DESCRIPTION

The LH28F016SA is a high performance 16M (16,777,216 bit) block erasable non-volatile random access memory organized as either 1M × 16 or 2M × 8. The LH28F016SA includes thirty-two 64K (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 3.

The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use.

Among the significant enhancements of the LH28F016SA:

• 3.3 V Low Power Capability

• Improved Write Performance

• Dedicated Block Write/Erase Protection

A 3/5» input pin reconfigures the device internally for optimized 3.3 V or 5.0 V read/write operation.

The LH28F016SA will be available in a 56-pin,

1.2 mm thick × 14 mm × 20 mm TSOP (Type I) package. This f orm factor and pinout allow f or very high board layout densities.

LH28F016SA is the most cost-effective, high-density

3.3 V flash memory.

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16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte/Word Writes and Block Erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the basic LH28F008SA command-set to achieve higher write performance and provide additional capabilities. These new commands and features include:

• Page Buffer Writes to Flash

• Command Queuing Capability

• Automatic Data Writes During Erase

• Software Locking of Memory Blocks

• T w o-Byte Successive Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed in either byte or word increments typically within 6 µs, a 33% improvement over the LH28F008SA. A Block Erase operation erases one of the 32 blocks in typically 0.6 seconds, independent of the other blocks, which is about 65% improvement ov er the LH28F008SA.

The LH28F016SA incorporates two Page Buffers of 256 Bytes (128 W ords) each to allow page data writes. This feature can improve a system write performance over pre vious flash memory de vices.

All operations are started by a sequence of Write commands to the device. Three Status Registers (described in detail later) and a RY»/BY» output pin provide information on the progress of the requested operation.

While the LH28F008SA requires an operation to complete before the next operation can be requested, the LH28F016SA allows queuing of the next oper ation while the memory executes the current operation. This eliminates system overhead when writing sev eral b ytes in a row to the array or erasing several blocks at the same time. The LH28F016SA can also perform write operations to one block of memory while performing erase of another block.

The LH28F016SA contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is 100%

compatible with the LH28F008SA Flash memory’s Status Register. This register , when used alone, provides a straightforward upgrade capability to the LH28F016SA from a LH28F008SA-based design.

• A Global Status Register (GSR) which informs the

system of command Queue status, Page Buff er status, and over all Write State Machine (WSM) status.

• 32 Block Status Registers (BSRs) which provide

block-specific status inf ormation such as the block lock-bit status.

The GSR and BSR memory maps for Byte-Wide and

Word-Wide modes are shown in Figures 4 and 5.

The LH28F016SA incorporates an open drain RY»/BY» outpin. This feature allows the user to OR-tie many RY»/BY» pins together in a multiple memory configuration such as a Resident Flash Array.

The LH28F016SA also incorporates a dual chipenable function with two input pins, CE »0 and CE»1. These pins have exactly the same functionality as the regular chip-enable pin CE» on the LH28F008SA. F or minimum chip designs, CE»1 may be tied to ground and use CE» as the chip enable input. The LH28F016SA uses the logical combination of these two signals to enable or disable the entire chip. Both CE»0 and CE»1 must be active low to enable the de vice and if either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY»/BY» pin, allows the system de- signer to reduce the number of control pins used in a large array of 16M de vices .

The BY»TE» pin allows either x8 or x16 read/writes to the LH28F016SA. BY»TE» at logic low selects 8-bit mode with address A0 selecting between low byte and high byte. On the other hand, BY»TE» at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don’t care). A block diagram is shown in Figure 2.

The LH28F016SA is specified for a maximum access time of each version, as follo ws:

The LH28F016SA provides user-selectable block locking to protect code or data such as Device Driv ers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the LH28F016SA has a master Write Protect pin (WP memory blocks whose lock-bits are set.

»

) which prevents any modifications to

OPERATING

TEMPERATURE

0 - 70°C 4.75 - 5.25 V 70 ns 0 - 70°C 4.5 - 5.5 V 80 ns 0 - 70°C 3.0 - 3.6 V 120 ns

SUPPLY

MAX. ACCESS

ACC

)

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LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

MEMORY MAPThe LH28F016SA incorporates an Automatic P ow er

Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching).

In APS mode, the typical ICC current is 2 mA at

5.0 V (1 mA at 3.3 V).

A Deep Power-Down mode of operation is invoked when the RP» (called PWD on the LH28F008SA) pin transitions low . This mode brings the device pow er consumption to less than 5 µA, typically , and provides additional write protection by acting as a device reset pin during power transitions. A reset time of 400 ns (VCC = 5.0 V ± 0.25 V system) is required from RP» switching high until outputs are again valid. In the Deep Power-Down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared.

A CMOS Standby mode of operation is enabled when either CE»0 or CE»1 transitions high and RP» sta ys high with all input control pins at CMOS levels. In this mode, the device typically dra ws an ICC standby current of 10 µA.

1FFFFFH

1F0000H 1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H 1BFFFFH

1B0000H

1AFFFFH

1A0000H

19FFFFH

190000H

18FFFFH

180000H

17FFFFH

170000H

16FFFFH 160000H

15FFFFH

150000H

14FFFFH

140000H

13FFFFH

130000H

12FFFFH

120000H

11FFFFH

110000H

10FFFFH

100000H

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H 0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

000000H

64KB BLOCK

64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK

31 64KB BLOCK

29 64KB BLOCK

28 64KB BLOCK 27 64KB BLOCK 26 64KB BLOCK 25 64KB BLOCK 24 64KB BLOCK 23 64KB BLOCK 22 64KB BLOCK

21 64KB BLOCK

20 64KB BLOCK 19 64KB BLOCK 18 64KB BLOCK 17 64KB BLOCK 16 64KB BLOCK 15 14 13 12 11 10

9 8 7 6 5 4 3 2

28F016SAT-3

Figure 3. LH28F016SA Memory Map

(Byte-Wide Mode)

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16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

Extended Status Registers Memory Map

x8 MODE

RESERVED

GSR

RESERVED

BSR31 RESERVED RESERVED

. . .

RESERVED

GSR

RESERVED

BSR0 RESERVED RESERVED

Figure 4. Extended Status Register

Memory Map (Byte-Wide Mode)

A[20:0]

1F0006H 1F0005H 1F0004H 1F0003H 1F0002H 1F0001H 1F0000H

010002H

000006H 000005H 000004H 000003H 000002H 000001H 000000H

28F016SAT-4

x16 MODE

A[20:1] (NOTE)

RESERVED

GSR

RESERVED

BSR31 RESERVED RESERVED

.

F8003H

F8002H

F8001H

F8000H

. .

08001H

RESERVED

GSR

RESERVED

BSR0 RESERVED RESERVED

NOTE: In word-wide mode A0 don't care, address values  are ignored A0.

Figure 5. Extended Status Register

Memory Map (Word-Wide Mode)

00003H

00002H

00001H

00000H

28F016SAT-5

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LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations for Word-Wide Mode (BY»TE» = VIH)

MODE RP

Read V Output Disable V

Standby V

Deep Powe r-Do wn V Manufacturer ID V Devi ce ID V Wri te V

» CE »

XXXXX High-Z VOH1, 3

V V V

V V

V V V

» WE A

DQ0 - DQ

OUT

X High-Z X 1, 6, 7

»/BY » NOTE

X1, 2, 7

X X X High-Z X 1, 6, 7

V V

XDINX1, 5, 6

0089H V 66A0H V

4 4

Bus Operations For Byte-Wide Mode (BY»TE» = VIL)

PPH

» CE »

XXXXX High-Z VOH1, 3

MODE RP

Read V Output Disable V

Standby V

Deep Powe r-Do wn V Manufacturer ID V Devi ce ID V Wri te V

NOTES:

1. X can be VIH or VIL for address or control pins except for RY»/BY», which is either VOL or VOH.

2. RY»/BY» output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY»/BY» will be at VOH if it is tied to VCC through a resistor. When the RY»/BY» at VOH is independent of OE operation is in progress.

3. RP» at GND ± 0.2 V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. A0 and A1, at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero.

5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully completed when VPP = V

6. While the WSM is running, RY»/BY» in Level-Mode (default) stays at VOL until all operations are complete. RY»/BY» goes to VOH when the WSM is not busy or in erase suspend mode.

7. RY»/BY» may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation.

V V V

V V

V V V

» WE A

DQ0 - DQ

OUT

X High-Z X 1, 6, 7

»/BY » NOTE

X1, 2, 7

X X X High-Z X 1, 6, 7

V V

XDINX1, 5, 6

89H V A0H V

»

while a WSM

4 4

Page 9

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

LH28F008SA-Compatible Mode Command Bus Definitions

COMMAND

NOTE

OPER. ADDRESS DATA OPER. ADDRESS DATA

Read Array Write X FFH Read AA AD Intelligent Identifier Write X 90H Read IA ID 1 Read Compatible Status Register Write X 70H Read X CSRD 2 Clear Status Register Write X 50H 3 Word/Byte Write Write X 40H Write WA WD Alternate Word/Byte Write Write X 10H Write WA WD Block Erase/Confirm Write X 20H Write BA D0H 4 Erase Suspend/Resume Write X B0H Write X D0H 4

ADDRESS DATA

AA = Array Address AD = Array Data BA = Block Address CSRD = CSR Data IA = Identifier Address ID = Identifier Data WA = Write Address WD = Write Data X = Don’t Care

NOTES:

1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.

3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.

4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WASM = 1), be sure to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued,while the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed. When you use Erase Suspend/ Resume command, we recommend to issue serial Block Erase command (20H, D0H) and Resume command (D0H). (Refer to Performance Enhancement Command Bus Definitions.)

FIRST BUS CYCLE SECOND BUS CYCLE

Page 10

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

LH28F016SA Performance Enhancement Command Bus Definitions

COMMAND MODE

NOTE

OPER. ADDR. DAT A OPE R. ADDR. DAT A OPE R. ADDR. DAT A

FIRST BUS CYCLE SECOND BUS CYCLE THIRD BUS CYCLE

Read Extended Status Register

Write X 71H Read RA

GSRD

BSRD Page Buffer Swap Write X 72H 7 Read Page Buffer Write X 75H Read PA PD Single Load to

Page Buffer

Writ e X 74H Wr i t e PA PD

x8 Wr it e X E0H Wr it e X BCL Wri te X BCH 4, 6, 1 0

Sequential Load to Page Buffer

Page Buffer Write

x16 Write X E0H Writ e X WC L Writ e X WCH

x8 Write X 0 CH Write A0

(L, H)

Write WA BC (H, L)

4, 5,

6, 10

3, 4,

9, 10

to Flash

x16 Write X 0CH Wr it e X WC L Writ e WA WCH 4, 5, 10

Two-Byte Wri te x8 Write X FBH Write A0

Block Erase/Confirm

Write X 20H Write BA D0H Write X D0H 11

(L, H)

Write WA W D (H, L ) 3

Lock Block/Confirm Write X 77H Write BA D0H Upload Status

Bits/Confirm Uploa d Devic e

Information Erase All Unlocked

Blocks/Confirm RY

»/BY » Enable to

Level-Mode

»/BY » Pulse-On-

RY Writ e

/BY

Pulse-On-

Erase

»/BY » Disable Write X 96H Write X 04H 8

Writ e X 97H Wri t e X D0H 2

Writ e X 9 9H Wri te X D0H

Writ e X A7H Wri te X D0H Wri te X D0H 1 1

Write X 96H Write X 01H 8

Write X 96H Write X 02H 8

Write X 96H Write X 03H 8

Sleep Write X F0H Abort Write X 80H

ADDRESS DATA

BA = Block Address AD = Array Data PA = Page Buffer Address PD = Page Buffer Data RA = Extended Register Address BSRD = BSR Data WA = Write Address GSRD = GSR Data X = Don’t Care WC (L, H) = Word Count (Low, High)

BC (L, H) = Byte Count (Low, High) WD (L, H) = Write Data (Low, High)

Page 11

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

NOTES:

1. RA can be the GSR address or any BSR address. See Figure 4 and 5 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the actual lock-bit status.

3. A0 is automatically complemented to load second byte of data. BY»TE first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.

5. In x16 mode, only the lower byte DQ0 - DQ7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.

6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure RY»/BY» output to one of two pulse-modes or enable and disable the RY»/BY» function.

9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the LH28F016SU User’s Manual.

10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.

11. Unless you issue erase suspend command, it is not necessary to input D0H on third bus cycle.

»

must be at VIL. A0 value determines which WD/BC is supplied

Compatible Status Register

WSMS ESS ES DWS VPPS R R R

76543210

CSR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready 0 = Busy

CSR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended 0 = Erase in Progress/Completed

CSR.5 = ERASE STATUS (ES)

1 = Error in Block Erasure 0 = Successful Block Erase

CSR.4 = DATA-WRITE STATUS (DWS)

1 = Error in Data Write 0 = Data Write Successful

CSR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort 0 = VPP OK

NOTES:

1. RY»/BY» output or WSMS bit must be checked to determine completion of an operation (Erase Suspend, Erase or Data Write) before the appropriate Status bit (ESS, ES or DWS) is checked for success.

2. If DWS and ES are set to ‘1’ during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again.

3. The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP’s level only after the Data-Write or Erase command sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between V

4. CSR.2 - CSR.0 = Reserved for future enhancements. These bits are reserved for future use and should be masked out when polling the CSR.

PPL

and V

PPH

Page 12

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

GLOBAL STATUS REGISTER

WSMS OSS DOS DSS QS PBAS PBS PBSS

76543210

GSR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready 0 = Busy

GSR.6 = OPERATION SUSPEND STATUS (OSS)

1 = Operation Suspended 0 = Operation in Progress/Completed

GSR.5 = DEVICE OPERATION STATUS (DOS)

1 = Operation Unsuccessful 0 = Operation Successful or Currently Running

GSR.4 = DEVICE SLEEP STATUS(DSS)

1 = Device in Sleep 0 = Device Not in Sleep

MATRIX 5/4

00 = Operation Successful or currently Running 01 = Device in Sleep Mode or Pending Sleep 10 = Operation Unsuccesful 11 = Operation Unsuccessful or Aborted

GSR.3 = QUEUE STATUS (QS)

1 = Queue Full 0 = Queue Available

GSR.2 = PAGE BUFFER AVAILABLE STATUS (PBAS)

1 = One or Two Page Buffers Available 0 = No Page Buffer Available

NOTES:

1. RY»/BY» output or WSMS bit must be checked to determine completion of an operation (Block Lock, Suspend, any RY»/BY» reconfiguration, Upload Status Bits, Erase or Data Write) before the appropriate Status bit (OSS or DOS) is checked for success.

2. If operation currently running, then GSR.7 = 0.

3. If device pending sleep, then GSR.7 = 0.

4. Operation aborted: Unsucccessful due to Abort command.

5. The device contains two Page Buffers.

6. Selected Page Buffer is currently busy with WSM operation.

7. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.

GSR.1 = PAGE BUFFER STATUS (PBS)

GSR.0 = PAGE BUFFER SELECT STATUS (PBSS)

1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy

1 = Page Buffer 1 Selected 0 = Page buffer 0 Selected

Page 13

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

BLOCK STATUS REGISTER

BS BLS BOS BOAS QS VPPS R R

76543210

BSR.7 = BLOCK STATUS (BS)

BSR.6 = BLOCK-LOCK STATUS (BLS)

BSR.5 = BLOCK OPERATION STATUS (BOS)

BSR.4 = BLOCK OPERATION ABORT STATUS (BOAS)

MATRIX 5/4

BSR.3 = QUEUE STATUS (QS)

BSR.2 = V

1 = Ready 0 = Busy

1 = Block Unlocked for Write/Erase 0 = Block Locked for Write/Erase

1 = Operation Unsuccessful 0 = Operation Successful or Currently Running

1 = Operation Aborted 0 = Operation Not Aborted

00 = Operation Successful or Currently Running 01 = Not a valid Combination 10 = Operation Unsuccessful 11 = Operation Aborted

1 = Queue Full 0 = Queue Available

STATUS (V

1 = V

Low Detect, Operation Abort

0 = V

PPS

)

NOTES:

1. RY»/BY» output or BS bit must be checked to determine completion of an operation (Block Lock, Suspend, Erase or Data Write) before the appropriate Status bits (BOS, BLS) is checked for success.

2. The BOAS bit will not be set until BSR.7 = 1.

3. Operation halted via Abort command.

4. BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs.

5. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.

Page 14

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

ELECTRICAL SPECIFICATIONS

WARNING: Stressing the device beyond the “Abso-

lute Maximum Ratings” may cause permanent dam-

Absolute Maximum Ratings*

age. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and

Temperature under bias ......................... 0°C to +80°C

Storage temperature .........................-65°C to +125°C

extended e xposure beyond the “Operating Conditions” may affect device reliability.

= 3.3 V ± 0.3 V Systems

SYMBOL PARAMETER MIN. MAX. UNITS TEST CONDITIONS NOTE

T V V

Operating Temperature, Commercial 0 70 °C Ambient Temperature 1 VCC with Respect to GND -0.2 7.0 V 2 VPP Supply Voltage with Respect to GND -0.2 14.0 V 2 Voltage on any Pin (Except VCC, VPP)

with Respe ct t o GN D

-0.5 VCC + 0.5 V 2

I Current into any Non-Supply Pin ±30 mA

OUT

SYMBOL PARAMETER MIN. MAX. UNITS TEST CONDITIONS NOTE

T V V

Output Short Circuit Current 100 mA 3

= 5.0 V ± 0.5 V Systems

Operating Temperature, Commercial 0 70 °C Ambient Temperature 1

VCC with Respect to GND -0.2 7.0 V 2

VPP Supply Voltage with Respect to GND -0.2 14.0 V 2

Voltage on any Pin (Except VCC, VPP) with Respe ct t o GN D

-0.5 7.0 V 2

I Current into any Non-Supply Pin ±30 mA

OUT

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins is V

3. Output shorted for no more than one second. No more than one output shorted at a time.

4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.

Output Short Circuit Current 100 mA 3

+ 0.5 V which, during transitions, may overshoot to V

+ 2.0 V for periods < 20 ns.

Page 15

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

Capacitance For 3.3 V Systems

SYMBOL PARAMETER TYP. MAX. UNITS TEST CONDITIONS NOTE

OUT

LOAD

Capacitance Looking into an Address/Control Pin

Capacitance Looking into an Output Pin 8 12 pF TA = 25°C, f = 1.0 MHz 1 Load Capacitance Driven by Outputs for

Timing Specifications Equivalent Testing Load Circuit 2.5 ns 50

50 pF For VCC = 3.3 V ±0.3 V 1

pF TA = 25°C, f = 1.0 MHz 1

Ω transmission line delay

For 5.0 V Systems

SYMBOL PARAMETER TYP. MAX. UNITS TEST CONDITIONS NOTE

OUT

LOAD

Capacitance Looking into an Address/Control Pin

Capacitance Looking into an Output Pin 8 12 pF TA = 25°C, f = 1.0 MHz 1

Load Capacitance Driven by Outputs for Timing Specifications

Equivalent Testing Load Circuit V

± 10% 2.5 ns 25 Ω transmission line delay

Equivalent Testing Load Circuit VCC ± 5% 2.5 ns

100 pF For VCC = 5.0 V ±0.5 V 1

30 pF

pF TA = 25°C, f = 1.0 MHz 1

For VCC = 5.0 V ±0.25 V

Ω transmission line delay

NOTE:

1. Sampled, not 100% tested.

Page 16

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

Timing Nomenclature

For 3.3 V systems timings are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC crosspoint definitions. Each timing parameter consists of 5 characters. Some common e xamples are defined below:

CEtELQV

OEtGLQV

ACCtAVQV

AStAVWH

DHtWHDX

A Address Inputs H High D Data Inputs L Low Q Da ta Output s V Valid

time (t) from CE» (E) going low (L) to the outputs (Q) becoming valid (V) time (t) from OE

»

(G) going low (L) to the outputs (Q) becoming valid (V) time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V) time (t) from address (A) valid (V) to WE time (t) from WE

PIN CHARACTERS PIN STATES

»

(W) going high (H) to when the data (D) can become undefined (X)

»

(W) going high (H)

ECE

GOE

» (Chip Enable) X Driven, but not necessarily valid » ( Output Enable) Z High Impedance

W WE (Write Enable)

PRP

RRY

» (Deep Power-Down Pin) »/BY » (Ready/Busy)

V Any Voltage Level

Y 3/5 5 V V 3 V V

» Pin

at 4.5 V Min.

at 3.0 V Min.

Page 17

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

2.4 INPUT

0.45 NOTE:

AC test inputs are driven at VOH (2.4 V (0.45 V

TTL

and VIL (0.8 V and fall times (10% to 90%) < 10 ns.

2.0

0.8

) for a Logic '0'. Input timing begins at V

). Output timing ends at VIH and VIL. Input rise

TTL

TEST POINTS

TTL

) for a Logic '1' and V

2.0

0.8

(2.0 V

OUTPUT

TTL

28F016SAT-6

Figure 6. Transient Input/Output

Reference Waveform (VCC = 5.0 V)

3.0 INPUT

0.0

NOTE: AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a Logic '0'. Input timing begins and output timing ends at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.

1.5 1.5

TEST POINTS

OUTPUT

28F016SAT-7

Figure 7. Transient Input/Output

Reference Waveform (VCC = 3.3 V)

2.5 ns OF 50 Ω TRANSMISSION LINE

FROM OUTPUT UNDER TEST

OL

)

TOTAL CAPACITANCE = 50 pF

TEST

POINT

28F016SAT-8

Figure 8. Transient Equivalent Testing

Load Circuit (VCC = 3.3 V)

2.5 ns OF 25 Ω TRANSMISSION LINE

FROM OUTPUT UNDER TEST

TOTAL CAPACITANCE = 100 pF

TEST

POINT

28F016SAT-9

Figure 9. Transient Equivalent Testing

Load Circuit (VCC = 5.0 V)

2.5 ns OF 83 Ω TRANSMISSION LINE

FROM OUTPUT UNDER TEST

TOTAL CAPACITANCE = 30 pF

28F016SAT-10

Figure 10. High Speed Transient Equivalent

Testing Load Circuit (VCC = 5.0 V ±5%)

TEST

POINT

Page 18

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

DC Characteristics

VCC = 3.3 V ±0.3 V, TA = 0°C to +70°C 3/5» = Pin Set High for 3.3 V Operations

SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE

CCS

CCD

CCR

CCW

CCE

CCES

Input Load Current ±1 µA VCC = VCC MAX., VIN = VCC or GND 1 Output Leakage Current ±10 µA VCC = VCC MAX., VIN = VCC or GND 1

VCC = VCC MAX.,

, RP

= VCC ±0.2 V

» = V

, RP

» = V

= VIH or V

, CE

±0.2 V or GND

= GND ±0.2 V

VCC Standby Current

VCC Deep Power-Down Current

, CE

50 100 µA

BYTE, WP, 3/5 ±0.2 V

= VCC MAX.,

14mA

, CE

BYTE, WP, 3/5

15µA

= GND ±0.2 V

= VCC MAX.,

CMOS: CE BYTE = GND ±0.2 V or VCC ±0.2 V

VCC Read Current 30 35 mA

Inputs = GND ±0.2 V or VCC ±0.2 V TTL: CE

BYTE = VIL or V Inputs = V f = 8 MHz, I

, CE

or V

OUT

= V

= 0 mA

IL,

VCC = VCC MAX., CMOS: CE

, CE

= GND ±0.2 V

BYTE = VCC ±0.2 V or GND ±0.2 V

VCC Read Current 15 20 mA

Inputs = GND ±0.2 V or VCC ±0.2 V TTL: CE

BYTE = VIH or V Inputs = V f = 4 MHz, I

, CE

or V

OUT

= V

= 0 mA

IL,

VCC Write Current 8 12 mA Word/Byte Write in Progress 1 VCC Block Erase Current 6 12 mA Block Erase in Progress 1 VCC Erase Suspend

Current

36mA

, CE

= V

CE Block Erase Suspended

1, 4

1, 3, 4

1, 2

PPS

PPD

VPP Standby Current ±1 ±10 µA VPP ≤ V VPP Deep Power-Down

Current

0.2 5 µA

» = GND ±0.2 V

Page 19

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

DC Characteristics (Continued)

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C 3/5» = Pin Set High for 3.3 V Operations

SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE

PPR

PPW

PPE

PPES

PPL

PPH

VPP Read Current 200 µA VPP > V

VPP Write Current 10 15 mA

VPP Erase Current 4 10 mA

VPP Erase Suspend Current

Input Low Voltage -0.3 0.8 V

Input High Voltage 2.0 VCC + 0.3 V

200 µA

Output Low Voltage 0.4 V

2.4 V

Output High Voltage

VPP during Normal Operations

VPP during Write/Erase Operations

12.0 11.4 12.6 V

- 0.2 V

0.0 6.5 V

VPP = V

, Word/Byte

PPH

Write in Progress VPP = V

PPH

Block Erase in Progress VPP = V

PPH

Block Erase Suspended

VCC = VCC MIN. and IOL = 4 mA

IOH = -2.0 mA VCC = VCC MIN.

IOH = -100 µA VCC = VCC MIN.

LKO

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3 V, VPP = 5.0 V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. I

CCES

3. Automatic Power Saving (APS) reduces I

4. CMOS Inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.

VCC Erase/Write Lock Voltage

is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of and I

CCR

to less than 1 mA in Static operation.

CCR

2.0 V

Page 20

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

DC Characteristics

VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C

3.5» Pin Set Low for 5 V Operations

SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE

CCS

CCD

CCR

CCW

CCE

CCES

Input Load Current ±1 µA VCC = VCC MAX., VIN = VCC or GND 1

Output Leakage Current ±10 µA VCC = VCC MAX., VIN = VCC or GND 1

= VCC MAX.,

, RP

, CE

» = V

±0.2 V

»# = V

» = V

or V

= GND ±0.2 V

±0.2 V or

VCC Standby Current

VCC Deep Power-Down Current

, CE

50 100 µA

BYTE, WP, 3/5 GND ±0.2 V

= VCC MAX.,

24mA

, CE

BYTE, WP, 3/5

15µA

» = GND ±0.2 V

= VCC MAX.,

CMOS: CE BYTE = GND ±0.2 V or VCC ±0.2 V

VCC Read Current 50 60 mA

Inputs = GND ±0.2 V or VCC ±0.2 V TTL: CE

BYTE = VIL or V Inputs = V f = 10 MHz, I

, CE

or V

OUT

= V

IL,

= 0 mA

VCC = VCC MAX., CMOS: CE

, CE

= GND ±0.2 V

BYTE = VCC ±0.2 V or GND ±0.2 V

VCC Read Current 30 35 mA

Inputs = GND ±0.2 V or VCC ±0.2 V TTL: CE

BYTE = VIH or V Inputs = V f = 5 MHz, I

, CE

or V

OUT

= V

IL,

= 0 mA VCC Write Current 25 35 mA Word/Byte Write in Progress 1 VCC Block Erase Current 18 25 mA Block Erase in Progress 1 VCC Erase Suspend

Current

510mA

, CE

= V

CE Block Erase Suspended

1, 4

1, 3, 4

1, 2

PPS

PPD

VPP Standby Current ±10 µA VPP ≤ V VPP Deep Power-Down

Current

0.2 5 µA

» = GND ±0.2 V

Page 21

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

DC Characteristics (Continued)

VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C

3.5» Pin Set Low for 5 V Operations

SYMBOL PARAMETER TYPE MIN. MAX. UNITS TEST CONDITIONS NOTE

PPR

PPW

PPE

PPES

PPL

PPH

VPP Read Current 65 200 µA VPP > V

VPP Write Current 7 12 mA

VPP Erase Current 5 10 mA

VPP Erase Suspend Current

Input Low Voltage -0. 5 0.8 V

Input High Voltage 2.0 VCC + 0.5 V

65 200 µA

Output Low Voltage 0.45 V

0.85 V

Output High Voltage

VPP during Normal Operations

VPP during Write/Erase Operations

12.0 11.4 12.6 V

- 0.4 V

0.0 6.5 V

VPP = V

, Word/Byte

PPH

Write in Progress VPP = V

PPH

Block Erase in Progress VPP = V

PPH

Block Erase Suspended

VCC = VCC MIN. and IOL = 5.8 mA

IOH = -2.5 mA VCC = VCC MIN.

IOH = -100 µA VCC = VCC MIN.

LKO

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 5.0 V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. I

CCES

3. Automatic Power Saving (APS) reduces I

4. CMOS Inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.

VCC Erase/Write Lock Voltage

is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of and I

CCR

to less than 2 mA in Static operation.

CCR

2.0 V

Page 22

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

AC Characteristics - Read Only Operations

TA = 0°C to +70°C

= 3.3 V ± 0.3V

SYMBOL PARAMETER

AVAV

AVEL

AVGL

AVQV

ELQV

PHQV

GLQV

ELQX

EHQZ

GLQX

GHQZ

Read Cycle Time 120 ns Address Setup to CE Address Setup to OE

» Going Low 10 ns 3, 4

» Going Low 0 ns 3, 4

Address to Output Delay 120 ns CE

» to Output Delay 120 ns 2

High to Output Delay 620 ns

» to Output Delay 45 ns 2

» to Output in Low Z 0 ns 3

» to Output in High Z 50 ns 3

» to Output in Low Z 0 ns 3

» to Output in High Z 30 ns 3

Output Hold from Address, CE OE

change, whichever occurs first

MIN. MAX.

0ns3

UNITS NOTE

FLQV

FHQV

FLQZ

ELFL

ELFH

BYTE to Output Delay 120 ns 3

BYTE Low to Output in High Z 30 ns 3

» Low to BYTE High or Low 5 ns 3

Page 23

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

AC Characteristics - Read Only Operations1 (Continued)

TA = 0°C to +70°C

= 5.0 V ± 0. 25 V VCC = 5.0 V ± 0.5 V

SYMBOL PARAMETER

MIN. MA X. MI N. MAX.

UNITS NOTE

AVAV

AVEL

AVGL

AVQV

ELQV

PHQV

GLQV

ELQX

EHQZ

GLQX

GHQZ

FLQV

FHQV

FLQZ

ELFL

ELFH

Read Cycle Time 70 80 ns Address Setup to CE Address Setup to OE Address to Output Delay 70 80 ns CE

» to Output Delay 70 80 ns 2

High to Output Delay 400 480 ns

» to Output Delay 30 35 ns 2

» to Output in Low Z 0 0 ns 3

» to Output in High Z 25 30 ns 3

» to Output in Low Z 0 0 ns 3

» to Output in High Z 25 30 ns 3

Output Hold from Address, CE OE

change, whichever occurs first

BYTE to Output Delay 70 80 ns 3

BYTE Low to Output in High Z 25 30 ns 3

» Low to BYTE High or Low 5 5 ns 3

» Going Low 10 10 ns 3, 4

» Going Low 0 0 ns 3, 4

00ns3

NOTES:

1. See AC Input/Output Reference Waveforms for timing measurements, Figures 5 and 6.

2. OE

»

may be delayed up to t

3. Sampled, not 100% tested.

4. This timing parameter is used to latch the correct BSR data onto the outputs.

ELQV

- t

after the falling edge of CE» without impact on t

GLQV

ELQV

Page 24

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

ADDRESSES (A)

CEX (E)  (NOTE)

OE (G)

WE (W)

DATA (D/Q)



POWER-UP

STANDBY

DEVICE AND

ADDRESS 

SELECTION OUTPUTS ENABLED DATA VALID STANDBY

ADDRESSES STABLE

AVAV

. . . . . .

CC

POWER-DOWN

. . .

AVEL

EHQZ

. . .

AVGL

GHQZ

. . .

GLQV

ELQV

GLQX

ELQX

HIGH-Z HIGH-Z

AVQV

. . .

VALID OUTPUT

. . .

5.0 V

GND

PHQV

RP (P)

NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.

Figure 11. Read Timing Waveforms

28F016SAT-11

Page 25

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

ADDRESSES (A)

CEX (E)

(NOTE)

OE (G)

BYTE (F)

DATA (DQ0 - DQ7)

AVQV

DATA

OUTPUT

. . . . . .

. . .

. . . . . .

DATA

OUTPUT

EHQZ

GHQZ

AVEL

HIGH-Z HIGH-Z

AVEL

ADDRESSES STABLE

= t

ELFL

AVGL

ELQV

ELQX

AVQV

GLQV

GLQX

AVAV

FLQV

FLQZ

= t

DATA (DQ8 - DQ15)

HIGH-Z HIGH-Z

DATA

OUTPUT

NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.

Figure 12. BY»TE» Timing Waveforms

28F016SAT-12

Page 26

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

POWER UP

RP (P)

3/5 (Y)

(3 V, 5 V)

ADDRESS (A)

DATA (Q)

0 V

YHPH

3.3 V

PHQV

AVQV

VALID

VALID 

3.3 V OUTPUTS

PLYL

PL5V

YLPH

4.5 V

Figure 13. VCC Power-Up and RP» Reset Waveforms

5.0 V

PHQV

AVQV

5.0 V OUTPUTS

VALID

VALID 

28F016SAT-13

SYMBOL PARAMETER MI N. MAX. UNIT NOTE

PLYL

PLYH

YLPH

YHPH

PL5V

PL3V

AVQV

PHQV

NOTES:

CE»0, CE»1 and OE

1. Minimum of 2 µs is required to meet the specified t

2. The power supply may start to switch concurrently with RP» going Low.

3. The address access time and RP» high to data valid time are shown for 5 V VCC operation. Refer to the AC Characteristics Read Only Operations 3.3 V VCC operation and all other speed options.

»

are switched low after Power-Up.

Low to 3/5

3/5

» Low (High) to RP » High 2 µs 1

» Low to V

(to VCC at 3.0 V MIN. or 3.6 V MAX.)

Low (High) 0 µs

at 4.5 V MIN.

0µs2

Address Valid to Data Valid for VCC = 5 V ± 10% 80 ns 3 RP

» High to Data Valid for V

= 5 V ± 10% 480 ns 3

times.

PHQV

Page 27

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

AC Characteristics for WE

»

- Controlled Command Write Operations

TA = 0°C to +70°C

SYMBOL PARAMETER

AVAV

VPWH

PHEL

ELWL

AVWH

DVWH

WLWH

WHDX

WHAX

WHEH

WHWL

GHWL

WHRL

RHPL

Write Cycle Time 120 ns VPP Setup to WE Going High 100 ns 3 RP

» Setup to CE » Going Low 480 ns

» Setup to WE Going Low 10 ns

Address Setup to WE Going High 75 ns 2, 6 Data Setup to WE Going High 75 ns 2, 6 WE Pulse Wi dth 75 ns Data Hold from WE High 10 ns 2 Address Hold from WE High 10 ns 2 CE

Hold from WE High 10 ns

WE Pulse Width High 45 ns Read Recovery before Write 0 ns WE High to RY RP

Hold from Valid Status Register

»/BY » Going Low 100 ns

(CSR, GSR, BSR) Data and RY

/BY

High

= 3.3 ± 0.3 V

TYP. MIN. MAX.

0ns3

UNITS NOTE

PHWL

WHGL

QVVL

WHQV

» High Recovery to WE Going Low 1 µs

Write Recovery before Read 95 ns VPP Hold from Valid Status Register

(CSR, GSR, BSR) Data and RY Duration of Word/Byte Write Operation 9 5 µs 4, 5 Duration of Block Erase Operation 0.3 s 4

»/BY » High

0µs

Page 28

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

AC Characteristics for WE

TA = 0°C to +70°C

SYMBOL PARAMETER

AVAV

VPWH

PHEL

ELWL

AVWH

DVWH

WLWH

WHDX

WHAX

WHEH

WHWL

GHWL

WHRL

RHPL

Write Cycle Time 70 80 ns VPP Setup to WE Going High 100 100 ns 3 RP

» Setup to CE » Going Low 480 480 ns

» Setup to WE Going Low 0 0 ns

Address Setup to WE Going High 50 50 ns 2, 6 Data Setup to WE Going High 50 50 ns 2, 6 WE Pulse Wi dth 40 50 ns Data Hold from WE High 0 0 ns 2 Address Hold from WE High 10 10 ns 2 CE

Hold from WE High 10 10 ns

WE Pulse Width High 30 30 ns Read Recovery before Write 0 0 ns WE High to RY RP

Hold from Valid Status Register

/BY

Going Low 100 100 ns

(CSR, GSR, BSR) Data and RY

/BY

High

»

- Controlled Command Write Operations1 (Continued)

= 5.0 ± 0.25 V VCC = 5.0 ± 0.5 V

UNITS NOTE

TYP. MIN. MAX. TYP. MIN. MAX.

00ns3

PHWL

WHGL

» High Recovery t o WE

Going Low Write Recovery before Read 60 65 ns

11µs

VPP Hold from Valid Status

QVVL

WHQV

NOTES:

CE» is defined as the latter of CE»0 or CE»1 going Low or the first of CE»0 or CE»1 going High.

1. Read timing during write and erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Write/Erase durations are measured to valid Status Register (CSR) Data.

5. Word/Byte write operations are typically performed with 1 Programming Pulse.

6. Address and Data are latched on the rising edge of WE

Duration of Word/Byte Write

Operati on

Duration of Block Erase Operation 0.3 0.3 s 4

»/BY » High

64.5 64.5 µs4, 5

»

for all Command Write Operations.

00µs

Page 29

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

POWER-DOWN

ADDRESSES (A)

(NOTE 1)

ADDRESSES (A)

(NOTE 2)

CEX (E)

(NOTE 4)

OE (G)

WE (W)

DEEP

WRITE

DATA-WRITE

OR ERASE

SETUP COMMAND

AVAV

WHEH

ELWL

WRITE VALID

ADDRESS AND DATA

(DATA-WRITE) OR ERASE CONFIRM

COMMAND

AVWH

AVWHtWHAX

WHWL

AUTOMATED DATA-WRITE

OR ERASE

DELAY

WHAX

WHQV 1, 2

WRITE READ

EXTENDED

COMMAND

(NOTE 3)

READ

EXTENDED

STATUS

A = RA

READ

COMPATIBLE

STATUS

A = RA

WHGL

GHWL

DATA (D/Q)

RY/BY (R)

RP (P)

(V)

WLWH

HIGH-Z

PHWL

PPH

PPL

WHDX

DVWH

VPWH

WHRL

NOTES:

1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.

2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.

4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH. 

5. RP low transition is only to show t

; not valid for above Read and Write cycles.

RHPL

QVVL

OUT

(NOTE 5)

28F016SAT-14

Figure 14. AC Waveforms for Command Write Operations

Page 30

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

AC Characteristics for CE» - Controlled Command Write Operations

TA = 0°C to +70°C

= 3.3 V ± 0.3 V

SYMBOL PARAMETER

AVAV

PHWL

VPEH

WLEL

AVEH

DVEH

ELEH

EHDX

EHAX

EHWH

EHEL

GHEL

EHRL

RHPL

Write Cycle Time 120 ns RP

Setup to WE Going Low 480 ns 3

VPP Set up to CE WE Setup to CE Address Setup to CE Data Setup to CE CE

» Pulse Width 75 ns

Data Hold from CE Address Hold from CE WE Hold f rom CE CE

» Pulse Width High 45 ns

» Going High 100 ns 3

» Going Low 0 ns

Going High 75 ns 2, 6

» Going High 75 ns 2, 6

» High 10 ns 2

High 10 ns

Read Recovery before Write 0 ns CE

» High to RY »/BY » Going Low 100 ns

Hold from Valid Status Register

(CSR, GSR, BSR) Data and RY

/BY

High

TYP. MIN. MAX.

0ns3

UNITS NOTE

PHEL

EHGL

QVVL

EHQV

» High Recovery t o CE » Going Low 1 µs

Write Recovery before Read 95 ns VPP Hold from Valid Status Register

(CSR, GSR, BSR) Data and RY Duration of Word/Byte Write Operation 9 5 µs 4, 5 Duration of Block Erase Operation 0.3 s 4

»/BY » High

0µs

Page 31

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

AC Characteristics for CE» - Controlled Command Write Operations1 (Continued)

TA = 0°C to +70°C

= 5.0 V ± 0.25 V VCC = 5.0 V ± 0.5 V

SYMBOL PARAMETER

TYP. MIN. MAX. TYP. MIN. MAX.

UNITS NOTE

AVAV

PHWL

VPEH

WLEL

AVEH

DVEH

ELEH

EHDX

EHAX

EHWH

EHEL

GHEL

EHRL

RHPL

Write Cycle Time 70 80 ns RP

Setup to WE Going Low 480 480 ns

VPP Setup to CE WE Setup to CE Address Setup to CE Data Setup to CE CE

» Pulse Width 40 50 ns

Data Hold from CE Address Hold from CE WE Hold f rom CE CE

» Pulse Width High 30 50 ns

» Going High 100 100 ns 3

» Going Low 0 0 ns

Going High 50 50 ns 2, 6

» Going High 50 50 ns 2, 6

» High 0 0 ns 2

» High 10 10 ns 2

High 10 10 ns

Read Recovery before Write 0 0 ns CE

» High to RY »/BY » Going Low 100 100 ns

Hold from Valid Status Register

(CSR, GSR, BSR) Data and RY

/BY

High

00ns3

PHEL

EHGL

» High Recovery to CE » Going Low 1 1 µs

Write Recovery before Read 60 80 ns VPP Hold from Valid Status

QVVL

EHQV

NOTES:

CE» is defined as the latter of CE»0 or CE»1 going Low or the first of CE»0 or CE»1 going High.

1. Read timing during write and erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Write/Erase durations are measured to valid Status Register (CSR) Data.

5. Word/Byte write operations are typically performed with 1 Programming Pulse.

6. Address and Data are latched on the rising edge of CE» for all Command Write Operations.

Duration of Word/Byte Write

Operati on

Duration of Block Erase Operation 0.3 0.3 s 4

»/BY » High

6 4.5 6 4.5 µs 4, 5

00µs

Page 32

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

POWER-DOWN

ADDRESSES (A)

(NOTE 1)

ADDRESSES (A)

(NOTE 2)

WE (W)

OE (G)

CEX (E)

(NOTE 4)

DEEP

WRITE

DATA-WRITE

OR ERASE

SETUP COMMAND

AVAV

EHWH

WLEL

WRITE VALID

ADDRESS AND DATA

(DATA-WRITE) OR

ERASE CONFIRM

COMMAND

AVEH

AVEHtEHAX

EHEL

EHAX

AUTOMATED DATA-WRITE

OR ERASE

DELAY

EHQV 1, 2

WRITE READ

EXTENDED

COMMAND

(NOTE 3)

READ

EXTENDED

STATUS

A = RA

READ

COMPATIBLE

STATUS

EHGL

GHEL

DATA (D/Q)

RY/BY (R)

RP (P)

(V)

ELEH

HIGH-Z

PHEL

PPH

PPL

EHDX

DVEH

VPEH

EHRL

NOTES:

1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.

2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations. is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH. 

4. CE

5. RP low transition is only to show t

; not valid for above Read and Write cycles.

RHPL

QVVL

OUT

(NOTE 5)

28F016SAT-15

Figure 15. Alternate AC Waveforms for Command Write Operations

Page 33

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

AC Characteristics for Page Buffer Write Operations

TA = 0°C to +70°C

= 3.3 V ± 0.3 V

SYMBOL PARAMETER

AVAV

ELWL

AVWL

DVWH

WLWH

WHDX

WHAX

WHEH

WHWL

GHWL

WHGL

Write Cycle Time 120 ns CE

» Setup to WE Going Low

Address Setup to WE Going Low 0 ns Data Setup to WE Going High 75 ns WE Pulse Wi dth 75 ns Data H old f rom WE High Address Hold from WE High 10 ns CE

» Hold from WE High 10 ns

WE Pulse Width High 45 ns Read Recovery before Write 0 ns Write Recovery before Read 95 ns

TYP. MIN. MAX.

UNITS NOTE

3 2

2 2

= 5.0 V ± 0.25 V VCC = 5.0 V ± 0.5 V

SYMBOL PARAMETER

TYP. MIN. MAX. TYP. MIN. MAX.

AVAV

ELWL

AVWL

DVWH

WLWH

WHDX

WHAX

WHEH

WHWL

GHWL

WHGL

NOTES:

CE» is defined as the latter of CE»0 or CE»1 going Low or the first of CE»0 or CE»1 going High.

1. These are WE

2. Sampled, but not 100% tested.

3. Address must be valid during the entire WE

Write Cy cle Ti me CE

» Setup to WE Going Low

Address Setup to WE Going Low 0 0 ns Data Setup to WE Going High WE Pulse Wi dth 40 50 ns Data Hold from WE High Address Hold from WE High 10 10 ns CE

» Hold from WE High 10 10 ns

WE Pulse Width High 30 30 ns Read Recovery before Write 0 0 ns Write Recovery before Read 60 65 ns

»

controlled write timings, equivalent CE» controlled write timings apply.

»

Low pulse.

70 80

50 50

00ns2

UNITS NOTE

ns ns

Page 34

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

WHEH

CEX (E)

ELWL

WE (W)

AVWL

ADDRESSES (A)

DATA (D/Q)

HIGH-Z

Figure 16. Page Buffer Write Timing Waveforms

Erase and Word/Byte Write Performance

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C

SYMBOL PARAMETER TYP.

WHRH

Word/By te Wri te Ti me 9 µs 2

Block Write Time 0.6 2.1 s Byte Write Mode

Block Write Time 0.3 1.0 s Word Write Mode Block Erase Time 0.8 10 s

(1)

WLWH

VALID

DVWH

WHAX

WHDX

WHWL

28F016SAT-16

MIN. MAX. UNITS TEST CONDITIONS NOTE

2 2 2

Full Chip Erase Time 25.6 s

VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C

SYMBOL PARAMETER TYP.

WHRH

Word/By te Wri te Ti me 6 µs 2

Block Write Time 0.4 2.1 s Byte Write Mode

Block Write Time 0.2 1.0 s Word Write Mode Block Erase Time 0.6 10 s Full Chip Erase Time 19.2 s

NOTES:

1. 25°C, VPP = 12.0 V Sampled.

2. Excludes System-Level Overhead.

(1)

MIN. MAX. UNITS TEST CONDITIONS NOTE

2 2 2 2

Page 35

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

56TSOP (TSOP056-P-1420)

0.18 [0.007]

0.08 [0.003]

20.30 [0.799]

19.70 [0.776]

18.60 [0.732]

18.20 [0.717]

19.30 [0.760]

18.70 [0.736]

0.50 [0.020] TYP.

0.28 [0.011]

0.12 [0.005]

0.13 [0.005]

0.49 [0.019]

0.39 [0.015]

0.22 [0.009]

0.02 [0.001]

1.10 [0.043]

0.90 [0.035]

1.19 [0.047] MAX.

14.20 [0.559]

13.80 [0.543]

PACKAGE BASE PLANE

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

ORDERING INFORMATION

LH28F016SA

Device TypeTPackage

Example: LH28F016SAT-70 (16M (1M x 16, 2M x 8) Flash Memory, 70 ns, 56-pin TSOP)

-70

Speed

70 Access Time (ns)

56-pin, 1.2 mm x 14 mm x 20 mm TSOP (Type I) (TSOP056-P-1420)

16M (1M x 16, 2M x 8) Flash Memory

56TSOP

28F016SAT-17

Page 36

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.

WARRANTY

SHARP

warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for 

a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair  or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. WARRANTIES OF EXCLUDED.

SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied.

NORTH AMERICA

SHARP Electronics Corporation Microelectronics Group 5700 NW Pacific Rim Blvd., M/S 20 Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpmeg.com

SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its

MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY

EUROPE

SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstraße 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Telex: 2161867 (HEEG D) Facsimile: (49) 40 2376-2232

ALL EXPRESS AND IMPLIED

ASIA

SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: (07436) 5-1321 Telex: LABOMETA-B J63428 Facsimile: (07436) 5-1532 

Datasheet LH28F016SAT-70 Datasheet (Sharp)

Specifications and Main Features

Frequently Asked Questions

User Manual