Datasheet LH28F016LLT-15, LH28F016LLT-12 Datasheet (Sharp)

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Page 1

LH28F016LL

16M (1M × 16, 2M × 8) Flash Memory

Figure 1. TSOP Configuration

FEATURES

• User-Configurable x8 or x16 Operation

• 3 V Write/Erase Operation (3 V V

)

– 2.7 - 3.6 V Write-Erase Operation

• 120 ns Maximum Access Time

= 3.0 V)

• 150 ns Maximum Access Time

= 2.7 V)

• 32 Independently Lockable Blocks (64K)

• 0.48 MB/sec Write Transf er Rate

• 100,000 Erase Cycles per Block

• Revolutionary Architecture

– Pipelined Command Execution – Write During Erase – Command Superset of

Sharp LH28F016SU

• 10 µA (MAX.) I

in CMOS Standby

• 5 µA (MAX.) Deep Power-Down

• State-of-the Art 0.6 µm ETOX™

Flash Technology

• 56-Pin, 1.2 mm × 14 mm × 20 mm TSOP

(Type I) Package

28F016LLT-1

TOP VIEW56-PIN TSOP

2 3

4 5

8 9

53 52 51 50



49 48

6 7A

47 46

RY/BY DQ

GND

55 54 OE

13 44 DQ

43 V

14 15 16 17 18 19 20

41 40

38 37

CX RP

VSSL

21 22 23

24 25 26 27 28

GND

34 DQ

35 DQ

33 32

30 29

BYTE NC NC

Page 2

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

Figure 2. LH28F016LL Block Diagram (Architectural Evolution Includes Page Buffers,

Queue Registers and Extended Status Registers)

OUTPUT BUFFER

INPUT

BUFFER

INPUT

BUFFER

DQ8 - DQ

DQ0 - DQ

ID

OUTPUT

MULTIPLEXER

CSR

ESRs

DATA

COMPARATOR

DATA

QUEUE

REGISTERS

PAGE

BUFFERS

I/O

LOGIC

CUI

WSM

64KB BLOCK 0

64KB BLOCK 1

64KB BLOCK 30

64KB BLOCK 31

. . .

Y GATING/SENSING

Y-DECODER

X-DECODER

OE WE WP RP

PROGRAM/

ERASE

VOLTAGE 

SWITCH

DC/DC

CONVERTER

BYTE

LX CX

GND

RY/BY

ADDRESS COUNTER

ADDRESS

QUEUE

LATCHES

INPUT

BUFFER

A0 - A

. . .

28F016LLT-2

Page 3

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

INPUT

BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8

mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A

input buffer is turned off when BYTE is high).

- A

INPUT

WORD-SELECT ADDRESSES: Select a word within one 64K block. A

- A

selects 1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are latched during Data Writes.

- A

INPUT

BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are

latched during Data Writes, Erase and Lock-Block operations.

- DQ7INPUT/OUTPUT

LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.

Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated when the chip is de-selected or the outputs are disabled.

- DQ15INPUT/OUTPUT

HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs

array, buffer or identifier data in the appropriate Read mode; not used for Status register reads. Floated when the chip is de-selected or the outputs are disabled.

, CE

INPUT

CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and

sense amplifiers. With either CE

or CE

high, the device is de-selected and power consumption reduces to Standby levels upon completion of any current Data-Write or Erase operations. Both CE

, CE

must be low to select the device. All timing

specifications are the same for both signals. Device Selection

occ

urs with the latter

falling edge of CE

or CE

. The first rising edge of CE

or CE

disables the device.

» INPUT

RESET/POWER-DOWN: RP

low places the device in a Deep Power-Down state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from Deep Power-Down, a recovery time of 5 ns is required to allow these circuits to power-up for Read mode, and another 395 ns is required to enter Program or Erase mode. W hen RP

» goes low, any current or pending WSM operation(s)

are terminated, and the device is reset. All Status registers return to ready (with all status flags cleared).

INPUT

OUTPUT ENABLE: Gates device data through the output buffers when low. The

outputs float to tri-state off when OE

» is high.

NOTE: CE

overrides OE

», and OE » overrides WE.

WE INPUT

WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers

and Address Queue Latches. WE is active low, and latches both address and data (command or array) on its rising edge.

»/BY

OPEN DRAIN OUTPUT

READY/BUSY: Indicates status of the internal WSM. When low, it ind icates that the

WSM is busy performing an operation. RY

»/BY » high indicates that the WSM is ready

for new operations (or WSM has completed all pending operations), or Erase is Suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE

» or CE

, CE

are high), except if a RY

»/BY

Pin Disable command is issued.

Page 4

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

PIN DESCRIPTION (Continued)

SYMBOL TYPE NAME AND FUNCTION

WP INPUT

WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for

each block. When WP is low, those locke d blocks as reflected by the B lock-Lock Status bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high, all blocks can be Written or Erased regardless of the state of the lock-bits. The WP input buffer is disabled when RP

» transitions low (deep power-down mode).

BYTE INPUT

BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or output

on DQ0 - DQ7, and DQ8 - DQ15 float. Address A0 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer. Address A1, then becomes the lowest order address.

LX INPUT

INPUT FROM OUTSIDE INDUCTOR: Input pin for outside inductor in DC/DC

converter circuit. Connect 1.8 (µH) inductor from VCC.

LC INPUT

INPUT FROM OUTSIDE CAPACITOR: Input pin for outside capacitor in DC/DC

converter circuit. Ground at 22000 (pF) capacitor.

SUPPLY DEVICE POWER SUPPLY 3.0 V (2.7 V to 3.6 V): Do not leave any power pins floating.

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.

NC NO CONNECT: No internal connection to die, lead may be driven or left floating.

VSSL GROUND

Page 5

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

INTRODUCTION

Sharp’s LH28F016LL 16M Flash Memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and communication products. With innovative capabilities, 3 V single voltage operation and very high read/write performance, the LH28F0166LL is also the ideal choice for designing embedded mass storage flash memory systems.

The LH28F016LL is very high density, highest performance non-volatile read/write solution for solid-state storage applications. Its symmetrically blocked architecture (100% compatible with the LH28F016SU 16M Flash memory), extended cycling, minimum power

2.7 V operation, very fast write and read performance and selective block locking provide a highly flexible memory component suitable for battery operation portable equipment such as digital still camera, PDA, cellular phone, and memory card. Its x8/x16 architecture allows the optimization of memory to processor interface. The flexible b lock loc king option enab les bundling of executable of executable application software in a Resident Flash Array or memory card. Manufactured on Sharp’s 0.6 µm ETOX™ process technology, the LH28F016LL is the most cost-effective, high-density 3 V single po wer oper ation flash memory.

DESCRIPTION

The LH28F016LL is a high performance 16M (16,777,216 bit) block erasable non-volatile random access memory organized as either 1M × 16 or 2M x 8. The LH28F016LL includes thirty-two 64K (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 3.

The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use.

Among the significant enhancements of the LH28F016LL:

• 3 V Write/Erase Operation (3 V V

)

• 3 V Low Power Capability

• Improved Write P erformance

• Dedicated Block Write/Erase Protection

The LH28F016LL will be available in a 56-pin,

1.2 mm thick × 14 mm × 20 mm TSOP (Type I) package. This f orm factor and pinout allow for v ery high board layout densities.

A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte/Word Writes and Block Erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the basic LH28F008SA command-set to achieve higher write performance and provide additional capabilities. These new commands and features include:

• Page Buffer Writes to Flash

• Command Queuing Capability

• Automatic Data Writes During Erase

• Software Locking of Memory Blocks

• T w o-Byte Successive Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed in either byte or word increments typically within 9 µs, a 15% improvement over the LH28F008SA.

Each block can be written and erased a minimum of 100,000 cycles. Systems can achie ve 1,000,000 Block Erase Cycles by providing wear-le veling algorithms and graceful block retirement. These techniques have already been employed in man y flash file systems and Hard Disk Drive designs.

The LH28F016LL incorporates two Page Buffers of 256 Bytes (128 W ords) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over pre vious flash memory devices.

All operations are started by a sequence of Wr ite commands to the device. Three Status Registers (described in detail later) and a RY»/BY» output pin provide information on the progress of the requested operation.

While the LH28F008SA requires an operation to complete before the next operation can be requested, the LH28F016LL allows queuing of the next operation while the memory executes the current operation. This eliminates system overhead when writing sev eral b ytes in a row to the array or erasing several blocks at the same time. The LH28F016LL can also perform write operations to one block of memory while performing erase of another block.

The LH28F016LL provides user-selectable block locking to protect code or data such as Device Driv ers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the LH28F016LL has a master Write Protect pin (WP

»

) which prevents any modifications to

memory blocks whose lock-bits are set.

Page 6

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

Figure 3. LH28F016LL Memory Map

MEMORY MAPThe LH28F016LL contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is 100%

compatible with the LH28F008SA Flash memory’s Status Register. This register , when used alone, provides a straightforward upgrade capability to the LH28F016LL from a LH28F008SA-based design.

• A Global Status Register (GSR) which informs

the system of command Queue status. Page Buffer status, and overall Write Status Machine (WSM) status.

• 32 Block Status Registers (BSRs) which provide

block-specific status inf ormation such as the bloc k lock-bit status.

The GSR and BSR memory maps for Byte-Wide and

Word-Wide modes are shown in Figures 4 and 5.

The LH28F016LL incorporates an open drain RY»/BY» output pin. This feature allows the user to ORtie many RY »/BY» pins together in a multiple memory configuration such as a Resident Flash Array.

The LH28F016LL also incorporates a dual chipenable function with two input pins, CE »0 and CE»1. These pins have e xactly the same functionality as the regulary chip-enable pin CE» on the LH28F008SA. F or minimum chip designs, CE»1 may be tied to ground and use CE»

as the chip enable input. The LH28F016LL uses the logical combination of these two signals to enable or disable the entire chip. Both CE»0 and CE»1 must be active low to enable the device and if either one becomes inactive, the chip will be disabled. This f eature, along with the open drain RY»/BY » pin, allo ws the system designer to reduce the number of control pins used in a large array of 16M de vices.

The BY»TE» pin allows either x8 or x16 read/writes to the LH28F016LL. BY »TE» at logic low selects 8-bit mode with address A0 selecting between low byte and high byte. On the other hand, BY »TE» at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don’t care). A device diagram is sho wn in Figure 1.

The LH28F016LL is specified for a maximum access time (t

ACC

)150 ns, in operating voltage 2.7 V to 3.6 V

and in operating temperature 0°C to +70°C.

The LH28F016LL incorporates an Automatic P ower Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (address not switching).

In APS mode, the typical I

current is 1 mA at 3.0 V.

A Deep Power-Down mode of operation is invoked when the RP» (called PWD on the LH28F008SA) pin transitions low . This mode brings the device power consumption to less than 5 µA typically , and pro vides additional write protection by acting as a device reset pin during power transitions. A reset time of 480 ns is required from RP» switching high until outputs are again valid. In the Deep Power-Down state , the WSM is reset

(any current operation will abort) and the CSR, GSR and BSR registers are cleared.

A CMOS Standby mode of operation is enabled when either CE»0 or CE»1 transitions high and RP» stays high with all input control pins at CMOS levels . In this mode , the device typically draws an I

standby current of

10 µA.

1F0000H

1FFFFFH

1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H

1BFFFFH

1B0000H

1AFFFFH

1A0000H

19FFFFH

190000H

18FFFFH

180000H

17FFFFH

170000H

16FFFFH

160000H

15FFFFH

150000H

14FFFFH

140000H

13FFFFH

130000H

12FFFFH

120000H

11FFFFH

110000H

10FFFFH

100000H

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

000000H

14 13 12 11 10

9 8 7 6 5 4 3 2

64KB BLOCK

16 64KB BLOCK

17 64KB BLOCK

18 64KB BLOCK

19 64KB BLOCK

20 64KB BLOCK

21 64KB BLOCK

22 64KB BLOCK

23 64KB BLOCK

24 64KB BLOCK

25 64KB BLOCK

26 64KB BLOCK

27 64KB BLOCK

28 64KB BLOCK

29 64KB BLOCK

30 64KB BLOCK

31 64KB BLOCK

64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK

64KB BLOCK

28F016LLT-3

Page 7

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Figure 4. Extended Status Register

Memory Map (Byte-Wide Mode)

Figure 5. Extended Status Register

Memory Map (Word-Wide Mode)

Extended Status Registers Memory Map

RESERVED

GSR

RESERVED

BSR31 RESERVED RESERVED

1F0006H 1F0005H 1F0004H 1F0003H 1F0002H 1F0001H 1F0000H

A[20:0]

x8 MODE

. . .

RESERVED

GSR

RESERVED

BSR0 RESERVED RESERVED

000006H 000005H 000004H 000003H 000002H 000001H 000000H

RESERVED

010002H

28F016LLT-4

RESERVED

GSR

RESERVED

BSR31 RESERVED RESERVED

F8003H

F8002H

F8001H

F8000H

A[20:1] (NOTE)

x16 MODE

. . .

RESERVED

GSR

RESERVED

BSR0 RESERVED RESERVED

00003H

00002H

00001H

00000H

RESERVED

08001H

28F016LLT-5

NOTE: In word-wide mode A0 don't care, address values  are ignored A0.

Page 8

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations for Word-Wide Mode (BY»TE» = VIH)

MODE RP

» CE »

» WE A

DQ0 - DQ

»/BY » NOTE

Read V

OUT

X1, 2

Output Disable V

X High-Z X 1, 6

Standby V

X X X High-Z X 1, 6

Deep Powe r-Down V

XXXXX High-Z VOH1, 3

Manufacturer ID V

00B0H V

Device ID V

6688H V

Writ e V

XDINX1, 5, 6

NOTES:

1. X can be VIH or VIL for address or control pins except for RY»/BY», which is either VOL or VOH.

2. RY»/BY» output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY»/BY» will be at VOH if it is tied to VCC through a resistor. When the RY»/BY» at VOH is independent of OE

»

while a WSM

operation is in progress.

3. RP» at GND ± 0.2 V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. All other addresses are set to zero. A0 and A1, at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero.

5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully completed when VPP = V

PPH

6. While the WSM is running, RY»/BY» in Level-Mode (default) stays at VOL until all operations are complete. RY»/BY» goes to VOH when the WSM is not busy or in erase suspend mode.

Bus Operations For Byte-Wide Mode (BY»TE» = VIL)

MODE RP

» CE »

» WE A

DQ0 - DQ

»/BY » NOTE

Read V

OUT

X1, 2

Output Disable V

X High-Z X 1, 6

Standby V

X X X High-Z X 1, 6

Deep Powe r-Down V

XXXXX High-Z VOH1, 3

Manufacturer ID V

B0H V

Device ID V

88H V

Writ e V

XDINX1, 5, 6

Page 9

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

COMMAND

FIRST BUS CYCLE SECOND BUS CYCLE

NOTE

OPER. ADDRESS DATA OPER. ADDRESS DATA

Read Array Write X FFH Read AA AD Intelligent Identifier Write X 90H Read IA ID 1 Read Compatible Status Register Write X 70H Read X CSRD 2 Clear Status Register Write X 50H 3 Word/Byte Write Write X 40H Write WA WD Alternate Word/Byte Write Write X 10H Write WA WD Block Erase/Confirm Write X 20H Write BA D0H Erase Suspend/Resume Write X B0H Write X D0H

ADDRESS DATA

AA = Array Address AD = Array Data BA = Block Address CSRD = CSR Data IA = Identifier Address ID = Identifier Data WA = Write Address WD = Write Data X = Don’t Care

NOTES:

1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.

3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.

4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WASM = 1), be sure to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed. When you use Erase Suspend/ Resume command, we recommend to issue serial Block Erase command (20H, D0H) and Resume command (D0H). (Refer to Performance Enhancement Command Bus Definitions.)

LH28F008SA-Compatible Mode Command Bus Definitions

Page 10

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

LH28F800SU Performance Enhancement Command Bus Definitions

COMMAND MODE

FIRST BUS CYCLE SECOND BUS CYCLE THIRD BUS CYCLE

NOTE

OPER. ADDR. DAT A OPE R. ADDR. DAT A OPE R. ADDR. DATA

Read Extended Status Register

Write X 71H Read RA

GSRD BSRD

Page Buffer Swap Write X 72H 7 Read Page Buffer Write X 75H Read PA PD Single Load to

Page Buffer

Writ e X 74H Wri te PA PD

Sequential Load to Page Buffer

x8 Wr ite X E 0H Wri te X BCL Wri te X BCH 4, 6, 1 0

x16 Writ e X E0H Wr it e X WCL Write X WC H

4, 5,

6, 10

Page Buffer Write to Flash

x8 Write X 0 CH Write A0

(L, H)

Write WA BC (H, L)

3, 4,

9, 10

x16 Writ e X 0CH Writ e X WC L Write WA WCH 4, 5, 10

Two-Byte Wri te x8 Write X FBH Write A0

(L, H)

Write WA WD (H , L) 3

Block Erase/Confirm

Write X 20H Write BA D0H Write X D0H 11

Lock Block/Confirm Write X 77H Write BA D0H Upload Status

Bits/Confirm

Writ e X 97H Writ e X D0H 2

Uploa d Devic e Information

Writ e X 99H Wr it e X D0H

Erase All Unlocked Blocks/Confirm

Writ e X A7 H Wr i te X D0H

»/BY » Enable to

Level-Mode

Write X 96H Write X 01H 8

»/BY » Pulse-On-

Writ e

Write X 96H Write X 02H 8

/BY

Pulse-On-

Erase

Write X 96H Write X 03H 8

»/BY » Disable Write X 96H Write X 04H 8

Sleep Write X F0H Abort Write X 80H

ADDRESS DATA

BA = Block Address AD = Array Data PA = Page Buffer Address PD = Page Buffer Data RA = Extended Register Address BSRD = BSR Data WA = Write Address GSRD = GSR Data X = Don’t Care WC (L, H) = Word Count (Low, High)

BC (L, H) = Byte Count (Low, High) WD (L, H) = Write Data (Low, High)

Page 11

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

NOTES:

1. RA can be the GSR address or any BSR address. See Figure 4.1 and 4.2 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the actual

lock-bit status.

3. A0 is automatically complemented to load second byte of data. BY»TE» must be at VIL. A0 value determines which WD/BC is supplied

first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer

contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.

5. In x16 mode, only the lower byte DQ0 - DQ7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.

6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure RY»/BY» output to one of two pulse-modes or enable and disable the RY »/BY» function.

9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the

LH28F016SU User’s Manual.

10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.

11. Unless you issue erase suspend command, it is not necessary to input D0H on third bus cycle.

WSMS ESS ES DWS VPPS R R R

76543210

CSR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready 0 = Busy

CSR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended 0 = Erase in Progress/Completed

CSR.5 = ERASE STATUS (ES)

1 = Error in Block Erasure 0 = Successful Block Erase

CSR.4 = DATA-WRITE STATUS (DWS)

1 = Error in Data Write 0 = Data Write Successful

CSR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort 0 = VPP OK

NOTES:

1. RY»/BY» output or WSMS bit must be checked to determine completion of an operation (Erase Suspend, Erase or Data Write) before the appropriate Status bit (ESS, ES or DWS) is checked for success.

2. If DWS and ES are set to ‘1’ during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again.

3. The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP’s level only after the Data-Write or Erase command sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between V

PPL

and V

PPH

4. CSR.2 - CSR.0 = Reserved for future enhancements. These bits are reserved for future use and should be masked out when polling the CSR.

Compatible Status Register

Page 12

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

WSMS OSS DOS DSS QS PBAS PBS PBSS

76543210

GSR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready 0 = Busy

GSR.6 = OPERATION SUSPEND STATUS (OSS)

1 = Operation Suspended 0 = Operation in Progress/Completed

GSR.5 = DEVICE OPERATION STATUS (DOS)

1 = Operation Unsuccessful 0 = Operation Successful or Currently Running

GSR.4 = DEVICE SLEEP STATUS(DSS)

1 = Device in Sleep 0 = Device Not in Sleep

MATRIX 5/4

00 = Operation Successful or Currently Running 01 = Device in Sleep Mode or Pending Sleep 10 = Operation Unsuccesful 11 = Operation Unsuccessful or Aborted

GSR.3 = QUEUE STATUS (QS)

1 = Queue Full 0 = Queue Available

GSR.2 = PAGE BUFFER AVAILABLE STATUS (PBAS)

1 = One or Two Page Buffers Available 0 = No Page Buffer Available

GSR.1 = PAGE BUFFER STATUS (PBS)

1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy

GSR.0 = PAGE BUFFER SELECT STATUS (PBSS)

1 = Page Buffer 1 Selected 0 = Page buffer 0 Selected

NOTES:

1. RY»/BY» output or WSMS bit must be checked to determine completion of an operation (Block Lock, Suspend, any RY»/ BY» reconfiguration, Upload Status Bits, Erase or Data Write) before the appropriate Status bit (OSS or DOS) is checked for success.

2. If operation currently running, then GSR.7 = 0.

3. If device pending sleep, then GSR.7 = 0.

4. Operation aborted: Unsucccessful due to Abort command.

5. The device contains two Page Buffers.

6. Selected Page Buffer is currently busy with WSM operation.

7. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.

GLOBAL STATUS REGISTER

Page 13

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

BS BLS BOS BOAS QS VPPS R R

76543210

BSR.7 = 1BLOCK STATUS (BS)

1 = Ready 0 = Busy

BSR.6 = BLOCK-LOCK STATUS (BLS)

1 = Block Unlocked for Write/Erase 0 = Block Locked for Write/Erase

BSR.5 = BLOCK OPERATION STATUS (BOS)

1 = Operation Unsuccessful 0 = Operation Successful or Currently Running

BSR.4 = BLOCK OPERATION ABORT STATUS (BOAS)

1 = Operation Aborted 0 = Operation Not Aborted

MATRIX 5/4

00 = Operation Successful or Currently Running 01 = Not a valid Combination 10 = Operation Unsuccessful 11 = Operation Aborted

BSR.3 = QUEUE STATUS (QS)

1 = Queue Full 0 = Queue Available

BSR.2 = V

STATUS (V

PPS

)

1 = V

Low Detect, Operation Abort

0 = V

NOTES:

1. RY»/BY» output or BS bit must be checked to determine completion of an operation (Block Lock, Suspend, Erase or Data Write) before the appropriate Status bits (BOS, BLS) is checked for success.

2. The BOAS bit will not be set until BSR.7 = 1.

3. Operation halted via Abort command.

4. BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs.

5. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.

BLOCK STATUS REGISTER

Page 14

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended e xposure beyond the “Operating Conditions” may affect device reliability.

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings*

Temperature under bias ......................... 0°C to +80°C

Storage temperature .........................-65°C to +125°C

= 3.3 V ±0.3 V Systems

SYMBOL PARAMETER MIN. MAX. UNITS TEST CONDITIONS NOTE

Operating Temperature, Commercial 0 70.0 °C Ambient Temperature 1

VCC with Respect to GND -0.2 7.0 V 2

VPP Supply Voltage with Respect to GND -0.2 7.0 V 2

Voltage on any Pin (Except VCC, VPP) with Respe ct t o GN D

-0.5 VCC + 0.5 V 2

I Current into any Non-Supply Pin ±30 mA

OUT

Output Short Circuit Current 100.0 mA 3

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Minimum °C voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum °C voltage on input/output pins is V

+ 0.5 V which, during transitions, may overshoot to V

+ 2.0 V for periods < 20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.

Capacitance For 3.3 V Systems

SYMBOL PARAMETER TYP. MAX. UNITS TEST CONDITIONS NOTE

Capacitance Looking into an Address/Control Pin

pF TA = 25°C, f = 1.0 MHz 1

OUT

Capacitance Looking into an Output Pin 8 12 pF TA = 25°C, f = 1.0 MHz 1

LOAD

Load Capacitance Driven by Outputs for Timing Specifications

50 pF For VCC = 3.3 V ±0.3 V 1

Equivalent Testing Load Circuit 2.5 ns 50

Ω transmission line delay

NOTE:

1. Sampled, not 100% tested.

Page 15

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Timing Nomenclature

All 3.3 V system timings are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC cross point definitions. Each timing par ameter consists of 5 characters. Some common e xamples are defined below:

CEtELQV

time (t) from CE» (E) going low (L) to the outputs (Q) becoming valid (V)

OEtGLQV

time (t) from OE

»

(G) going low (L) to the outputs (Q) becoming valid (V)

ACCtAVQV

time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)

AStAVWH

time (t) from address (A) valid (V) to WE

»

(W) going high (H)

DHtWHDX

time (t) from WE

»

(W) going high (H) to when the data (D) can become undefined (X)

PIN CHARACTERS PIN STATES

A Address Inputs H High D Data Inputs L Low Q Data Out puts V Valid ECE

(Chip Enable) X Driven, but not necessarily valid

GOE

» (Output Enable) Z High Impedance

W WE (Write Enable)

PRP

(Deep Power-Down Pin)

RRY

»/BY » (Ready/Busy)

V Any Voltage Level

3 V V

at 3.0 V Min.

Figure 6. Transient Input/Output

Reference Waveform (VCC = 3.3 V)

Figure 7. Transient Equivalent Testing

Load Circuit (VCC = 3.3 V)

INPUT

TEST POINTS

OUTPUT

3.0

0.0

1.5 1.5

28F016LLT-6

NOTE: AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a Logic '0'. Input timing begins and output timing ends at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.

2.5 ns OF 50 Ω TRANSMISSION LINE

TOTAL CAPACITANCE = 50 pF

FROM OUTPUT UNDER TEST

TEST

POINT

28F016LLT-7

Page 16

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

DC Characteristics

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C

SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITI ONS NOTE

Input Load Current ±1 µA VCC = VCC MAX., VIN = VCC or GND 1

Output Leakage Current ±10 µA VCC = VCC MAX., VIN = VCC or GND 1

CCS

VCC Standby Current

48µA

= VCC MAX.,

, CE

, RP

» = V

±0.2 V

BYTE, WP, 3/5

» = V

±0.2 V or

GND ±0.2 V

1, 4

14mA

= VCC MAX.,

, CE

, RP

» = V

BYTE, WP, 3/5

» = V

or V

CCD

VCC Deep Power-Down Current

15µARP

= GND ±0.2 V 1

CCR

VCC Read Current 30 35 mA

VCC = VCC MAX., CMOS: CE

, CE

= GND ±0.2 V BYTE = GND ±0.2 V or VCC ±0.2 V Inputs = GND ±0.2 V or VCC ±0.2 V

TTL: CE

, CE

= V

IL,

BYTE = VIL or V

Inputs = V

or V

f = 8 MHz, I

OUT

= 0 mA

1, 3, 4

CCR

VCC Read Current 15 20 mA

VCC = VCC MAX., CMOS: CE

, CE

= GND ±0.2 V BYTE = VCC ±0.2 V or GND ±0.2 V Inputs = GND ±0.2 V or VCC ±0.2 V TTL: CE

, CE

= V

IL,

BYTE = VIH or V

Inputs = V

or V

f = 4 MHz, I

OUT

= 0 mA

1, 3, 4

CCW

VCC Write Current 8 12 mA Word/Byte Write in Progress 1

CCE

VCC Block Erase Current 6 10 mA Block Erase in Progress 1

CCES

VCC Erase Suspend Current

36mA

, CE

= V

Block Erase Suspended

1, 2

PPS

VPP Standby Current 0.2 5 µA VPP ≤ V

PPD

VPP Deep Power-Down Current

0.2 5 µA RP

» = GND ±0.2 V 1

Page 17

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

DC Characteristics (Continued)

VCC = 3.3 V ± 0.3 V, T A = 0°C to +70°C

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC = VPP = 3.3 V, T = 25°C. All IPP stands for outside inductor's current.

2. I

CCES

is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of

CCES

and I

CCR

3. Automatic Power Saving (APS) reduces I

CCR

to less than 1 mA in Static operation.

**To be Determined

SYMBOL PARAMETER TYPE MIN. MAX. UNITS TEST CONDITIONS NOTE

PPR

VPP Read Current 5 µA VPP > V

PPW

VPP Write Current 50 ** mA

VPP = V

PPH

, Word/Byte

Write in Progress

PPE

VPP Erase Current 30 65 mA

VPP = V

PPH

Block Erase in Progress

PPES

VPP Erase Suspend Current

200 µA

VPP = V

PPH

Block Erase Suspended

Input Low Voltage -0.3 0.8 V

Input High Voltage 2.0 VCC + 0.3 V

Output Low Voltage 0.4 V

VCC = VCC MIN. and IOL = 4 mA

Output High Voltage

2.4 V

IOH = 2.0 mA VCC = VCC MIN.

- 0.2 V

IOH = 100 µA VCC = VCC MIN.

PPL

VPP during Normal Operations

0.0 5.5 V

PPH

VPP during Write/Erase Operations

5.0 4.5 5.5 V

LKO

VCC Erase/Write Lock Voltage

2.0 V

Figure 8. Transient Equivalent Testing

Load Circuit (VCC = 3.3 V)

28F016LLT-8

Page 18

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

AC Characteristics - Read Only Operations

VCC = 3.3 V, TA = 0°C to +70°C

SYMBOL PARAMETER

= 3.3 V ± 0.3 V

UNITS NOTE

MIN. MAX .

AVAV

Read Cycle Time

100

AVEL

Address Setup to CE

» Going Low 10

ns 3, 4

AVGL

Address Setup to OE

» Going Low 0 ns 3, 4

AVQV

Address to Output Delay

100

ELQV

» to Output Delay 100 ns

PHQV

High to Output Delay 620 ns

GLQV

» to Output Delay 45 ns

ELQX

» to Output in Low Z 0 ns 3

EHQZ

» to Output in High Z 50 ns 3

GLQX

» to Output in Low Z 0 ns 3

GHQZ

» to Output in High Z 30 ns 3

Output Hold from Address, CE

change, whichever occurs first

0ns3

LQV

FHQV

BYTE to Output Delay 120 ns 3

FLQZ

BYTE Low to Output in High Z 30 ns 3

ELFL

ELFH

» Low to BYTE High or Low

ns 3

NOTES:

1. See AC Input/Output Reference Waveforms for timing measurements.

2. OE

»

may be delayed up to t

ELQV

- t

GLQV

after the falling edge of CE» without impact on t

ELQV

3. Sampled, not 100% tested.

4. This timing parameter is used to latch the correct BSR data onto the outputs.

Page 19

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Figure 9. Read Timing Waveforms

28F016LLT-9

AVAV

NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.

ADDRESSES STABLE

CC

POWER-UP

STANDBY

DEVICE AND

ADDRESS 

SELECTION OUTPUTS ENABLED DATA VALID STANDBY

CC

POWER-DOWN

AVEL

ADDRESSES (A)

CEX (E) 

(NOTE)

AVGL

GLQV

ELQV

GLQX

ELQX

AVQV

PHQV

EHQZ

GHQZ

OE (G)

WE (W)

DATA (D/Q)

5.0 V GND

RP (P)

HIGH-Z HIGH-Z

VALID OUTPUT

. . . . . .

. . .

Page 20

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

Figure 10. BY»TE» Timing Wa veforms

28F016LLT-10

AVAV

NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.

ADDRESSES STABLE

AVEL

= t

ELFL

ADDRESSES (A)

CEX (E)

(NOTE)

EHQZ

OE (G)

DATA (DQ0 - DQ7)

HIGH-Z HIGH-Z

BYTE (F)

HIGH-Z HIGH-Z

DATA

OUTPUT

DATA

OUTPUT

DATA

OUTPUT

AVEL

AVGL

ELFL

FLQV

= t

AVQV

GLQV

GHQZ

ELQV

ELQX

GLQX

AVQV

FLQZ

DATA (DQ8 - DQ15)

. . . . . .

. . .

. . . . . .

Page 21

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Figure 11. VCC Power-Up and RP» Reset Waveforms

NOTES:

CE»0, CE»1 and OE

»

are switched low after Power-Up.

1. The power supply may start to switch concurrently with RP» going Low.

2. Refer to the AC Characteristics Read Only Operations for detail information. **To be Determined

SYMBOL PARAMETER MIN. MAX. UNIT NOTE

» Low to V

at 3.0 V Minimum 0 µs 1

AVQV

Address Valid to Data Valid for VCC = 2.7 V to 3.6 V ** ns 2

PHQV

» High to Data Valid for V

= 2.7 V to 3.6 V ** ns 2

28F016LLT-11

VALID

ADDRESS (A)

RP (P)

DATA (Q)

VALID

3.0 V

3.3 V

AVQV

PHQV

AVQV

POWER UP

0 V

3.3 V

Page 22

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

AC Characteristics for WE

»

- Controlled Command Write Operations

VCC = 3.3 V, TA = 0°C to +70°C

SYMBOL PARAMETER TYP. MIN. MAX. UNITS NOTE

AVAV

Write Cycle Time 100 ns

VPWH

VPP Setup to WE Going High 100 ns 3

PHEL

» Setup to CE » Going Low 480 ns

ELWL

» Setup to WE Going Low 10 ns

AVWH

Address Setup to WE Going High 65 ns 2, 6

DVWH

Data Setup to WE Going High 65 ns 2, 6

WLWH

WE Pulse Wi dth 75 ns

WHDX

Data Hold from WE High 10 ns 2

WHAX

Address Hold from WE High 10 ns 2

WHEH

» Hold from WE High 10 ns

WHWL

WE Pulse Width High 35 ns

GHWL

Read Recovery before Write 0 ns

WHRL

WE High to RY

/BY

Going Low 100 ns

RHPL

» Hold from Valid Status Register

(CSR, GSR, BSR) Data and RY

»/BY » High

0ns3

PHWL

» High Recovery to WE Going Low 1 µs

WHGL

Write Recovery before Read 95 ns

QVVL

VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY

»/BY » High

0µs

WHQV

Duration of Word/Byte Write Operation ** ** µs 4, 5

WHQV

Duration of Block Erase Operation ** s 4

NOTES:

CE» is defined as the latter of CE»»0 or CE»1 going Low or the first of CE»»0 or CE»1 going High.

1. Read timing during write and erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Write/Erase durations are measured to valid Status Register (CSR) Data.

5. Word/Byte write operations are typically performed with 1 Programming Pulse.

6. Address and Data are latched on the rising edge of CE» for all Command Write Operations. **To be Determined

Page 23

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Figure 12. AC Waveforms for Command Write Operations

ADDRESSES (A)

(NOTE 1)

A = RA

OUT

CEX (E)

(NOTE 4)

OE (G)

WE (W)

DATA (D/Q)

RY/BY (R)

RP (P)

AVAV

WHGL

WHWL

WLWH

DVWH

PHWL

RHPL

QVVL

ADDRESSES (A)

(NOTE 2)

AVWH

WHAX

AVWHtWHAX

ELWL

WHEH

WHQV 1, 2

GHWL

WHDX

WHRL

(NOTE 5)

VPWH

28F016LLT-12

(NOTE 3)

HIGH-Z

WRITE

DATA-WRITE

OR ERASE

SETUP COMMAND

DEEP

POWER-DOWN

WRITE VALID

ADDRESS AND DATA

(DATA-WRITE) OR ERASE CONFIRM

COMMAND

AUTOMATED

DATA-WRITE

OR ERASE

DELAY

WRITE READ

EXTENDED

COMMAND

READ

EXTENDED

STATUS

NOTES:

1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.

2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.

4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH. 

5. RP low transition is only to show t

RHPL

; not valid for above Read and Write cycles.

READ

COMPATIBLE

STATUS

(V)

PPH

PPL

Page 24

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

AC Characteristics for CE» - Controlled Command Write Operations

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C

SYMBOL PARAMETER TYP. MIN. MAX. UNITS NOTE

AVAV

Write Cycle Time 100 ns

PHWL

Setup to WE Going Low 480 ns 3

VPEH

VPP Set up to CE

» Going High 100 ns 3

WLEL

WE Setup to CE

» Going Low 0 ns

AVEH

Address Setup to CE

» Going High 75 ns 2, 6

DVEH

Data Setup to CE

» Going High 75 ns 2, 6

ELEH

Pulse Width 75 ns

EHDX

Data Hold from CE

» High 10 ns 2

EHAX

Address Hold from CE

» High 10 ns 2

EHWH

WE Hold f rom CE

» High 10 ns

EHEL

Pulse Width High 45 ns

GHEL

Read Recovery before Write 0 ns

EHRL

High to RY

/BY

Going Low 100 ns

RHPL

» Hold from Valid Status Register

(CSR, GSR, BSR) Data and RY

»/BY » High

0ns3

PHEL

» High Recovery t o CE » Going Low 1 µs

EHGL

Write Recovery before Read 95 ns

QVVL

VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY

»/BY » High

0µs

EHQV

Duration of Word/Byte Write Operation ** ** µs 4, 5

EHQV

Duration of Block Erase Operation ** s 4

NOTES:

CE» is defined as the latter of CE»0 or CE»1 going Low or the first of CE»0 or CE»1 going High.

1. Read timing during write and erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Write/Erase durations are measured to valid Status Register (CSR) Data.

5. Word/Byte write operations are typically performed with 1 Programming Pulse.

6. Address and Data are latched on the rising edge of CE» for all Command Write Operations. **To be Determined

Page 25

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Figure 13. AC Waveforms for Command Write Operations

ADDRESSES (A)

(NOTE 1)

A = RA

OUT

CEX (E)

(NOTE 4)

OE (G)

WE (W)

DATA (D/Q)

RY/BY (R)

RP (P)

AVAV

EHGL

EHEL

ELEH

DVEH

PHEL

RHPL

QVVL

ADDRESSES (A)

(NOTE 2)

AVEH

EHAX

AVEHtEHAX

WLEL

EHWH

EHQV 1, 2

GHEL

EHDX

EHRL

(NOTE 5)

VPEH

28F016LLT-13

(NOTE 3)

HIGH-Z

WRITE

DATA-WRITE

OR ERASE

SETUP COMMAND

DEEP

POWER-DOWN

WRITE VALID

ADDRESS AND DATA

(DATA-WRITE) OR

ERASE CONFIRM

COMMAND

AUTOMATED DATA-WRITE

OR ERASE

DELAY

WRITE READ

EXTENDED

COMMAND

NOTES:

1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.

2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.

4. CE

is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH. 

5. RP low transition is only to show t

RHPL

; not valid for above Read and Write cycles.

(V)

PPH

PPL

READ

EXTENDED

STATUS

READ

COMPATIBLE

STATUS

Page 26

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

AC Characteristics for Page Buffer Write Operations

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C

SYMBOL PARAMETER TYP. MIN. MAX. UNITS NOTE

AVAV

Write Cycle Time 120 ns

ELWL

» Setup to WE Going Low 10 ns

AVWL

Address Setup to WE Going Low 0 ns 3

DVWH

Data Setup to WE Going High 75 ns 2

WLWH

WE Pulse Wi dth 75 ns

WHDX

Data Hold from WE High 10 ns 2

WHAX

Address Hold from WE High 10 ns 2

WHEH

» Hold from WE High 10 ns

WHWL

WE Pulse Width High 45 ns

GHWL

Read Recovery before Write 0 ns

WHGL

Write Recovery before Read 95 ns

NOTES:

CE» is defined as the latter of CE»0 or CE»1 going Low or the first of CE»0 or CE»1 going High.

1. These are WE

»

controlled write timings, equivalent CE» controlled write timings apply.

2. Sampled, but not 100% tested.

3. Address must be valid during the entire WE

»

Low pulse.

Page 27

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Figure 14. Page Buffer Write Timing Waveforms

Erase and Word/Byte Write Performance

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C

SYMBOL PARAMETER TYP.

(1)

MIN. MAX. UNIT S TEST CONDITIONS NOTE

WHRH

Word/By te Wri te Ti me 12 µs 2

WHRH

Block Write Time 0.8 2.1 s Byte Write Mode

WHRH

Block Write Time 0.4 1.0 s Word Write Mode

Block Erase Time ** 10 s

Full Chip Erase Time ** s

NOTES:

1. 25°C, VPP = 3.3 V Sampled.

2. Excludes System-Level Overhead. **To be Determined

VALID

ADDRESSES

HIGH-Z

DVWH

DATA (D/Q)

CEX (E)

WE (W)

WHDX

AVWL

WLWH

WHWL

WHEH

ELWL

WHAX

28F016LLT-14

Page 28

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

ORDERING INFORMATION

0.50 [0.020] TYP.

PACKAGE BASE PLANE

0.28 [0.011]

0.12 [0.005]

20.30 [0.799]

19.70 [0.776]

18.60 [0.732]

18.20 [0.717]

19.30 [0.760]

18.70 [0.736]

0.49 [0.019]

0.39 [0.015]

0.22 [0.009]

0.02 [0.001]

1.10 [0.043]

0.90 [0.035]

1.19 [0.047] MAX.

0.13 [0.005]

0.18 [0.007]

0.08 [0.003]

14.20 [0.559]

13.80 [0.543]

56TSOP

56TSOP (TSOP056-P-1420)

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

56-pin, 1.2 mm x 14 mm x 20 mm TSOP (Type I) (TSOP056-P-1420)

LH28F016LL

Device TypeTPackage

28F016LLT-15

Example: LH28F016LLT-12 (16M (1M x 16, 2M x 8) Flash Memory, 120 ns, 56-pin TSOP)

16M (1M x 16, 2M x 8) Flash Memory

-##

Speed

12 120 15 150

Access Time (ns)

Page 29

SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied.

NORTH AMERICA

EUROPE

ASIA

SHARP Electronics Corporation Microelectronics Group 5700 NW Pacific Rim Blvd., M/S 20 Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpmeg.com

SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstraße 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Telex: 2161867 (HEEG D) Facsimile: (49) 40 2376-2232

LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.

SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: (07436) 5-1321 Telex: LABOMETA-B J63428 Facsimile: (07436) 5-1532 

WARRANTY

SHARP

warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for 

a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair  or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to

SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its

return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied.

ALL EXPRESS AND IMPLIED

WARRANTIES OF

MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY

EXCLUDED.

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

Datasheet LH28F016LLT-15, LH28F016LLT-12 Datasheet (Sharp)

Specifications and Main Features

Frequently Asked Questions

User Manual