Datasheet LH28F008SCR-L85 Datasheet (Sharp)

®

PRODUCT SPECIFICATIONS

Integrated Circuits Group

LH28F008SCR-L85

Flash Memory

8M (1M ×8)

(Model No.: LHF08CH2)

Spec No.: EL104029B

Issue Date: February 1, 1999

SHARP

l

Handle this document carefully for it contains material protected by international

copyright law. Any reproduction, full or in part, of this material is prohibited without the

express written permission of the company.

l

When using the products covered herein, please observe the conditions written herein

and the precautions outlined in the following paragraphs. In no event shall the company

be liable for any damages resulting from failure to strictly adhere to these conditions and

precautions.

(1) The products covered herein are designed and manufactured for the following

application areas. When using the products covered herein for the equipment listed
in Paragraph (Z), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).

*Office electronics

l

.Machine tools
@Audiovisual equipment
*Home appliance

l

LHF08CH2

instrumentation and measuring equipment

Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment

which demands hiah reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.

*Control and safety devices for airplanes, trains, automobiles, and other

transportation equipment

l

Mainframe computers

aTraffic control systems

@Gas leak detectors and automatic cutoff devices

6escue and
@Other safety devices and safety equipment,etc.

(3) Do not use the products covered herein for the following equipment which demands

extremelv hiqh performance in terms of functionality, reliability, or accuracy.

*Aerospace equipment
*Communications equipment for trunk lines

*Control equipment for the nuclear power industry

l

Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above

three Paragraphs to a sales representative of the company.

security equipment

*Please direct all queries regarding the products covered herein to a sales representative

of the company.

Rev.l.l

SHARP

LHFOSCH2

CONTENTS

PAGE

I .O INTRODUCTION ................................................... 3

1 .l New Features

1.2 Product Overview.. .............................................. 3

2.0 PRINCIPLES OF OPERATION.. ........................... 7

2.1 Data Protection ...................................................

3.0 BUS OPERATION

3.1 Read

3.2 Output Disable .................................................... 8

3.3 Standby..

3.4 Deep Power-Down

3.5 Read Identifier Codes Operation..

3.6 Write

1.0 COMMAND DEFINITIONS.

4.1 Read Array Command.. ..................................... 12

4.2 Read Identifier Codes Command ...................... 12

4.3 Read Status Register Command.. ..................... 12

4.4 Clear Status Register Command.. ..................... 12

4.5 Block Erase Command.. .................................... 12

4.6 Byte Write Command

4.7 Block Erase Suspend Command.. ..................... 13

4.8 Byte Write Suspend Command.. ....................... 14

4.9 Set Block and Master Lock-Bit Commands..

4.10 Clear Block Lock-Bits Command.. ................... 15

...................................................................

....................................................................

...................................................... 3

.................................................

.............................................................

..............................................

.......................

................................... 9

........................................ 13

.....

7

8
8

8
8
9
9

14

1

PAGE

5.0 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit

Configuration Polling ...........................................

5.3 Power Supply Decoupling.. ................................ 24

5.4 V,, Trace on Printed Circuit Boards..

5.5 v,,, v,,,

5.6 Power-Up/Down Protection

5.7 Power Dissipation

6.0 ELECTRICAL SPECIFICATIONS..

6.1 Absolute Maximum Ratings

6.2 Operating Conditions ......................................... 25

6.2.1 Capacitance ................................................. 25

6.2.2

AC Input/Output Test Conditions..

6.2.3 DC Characteristics

6.2.4 AC Characteristics - Read-Only Operations .2E

6.2.5 AC Characteristics - Write Operations..

6.2.6 Alternative CE#-Controlled Writes..

6.2.7 Reset Operations

6.2.8 Block Erase, Byte Write and Lock-Bit
Configuration Performance..

7.0 ADDITIONAL INFORMATION

7.1 Ordering Information .......................................... 40

8.0 PACKAGE AND PACKING SPECIFICATIONS ..4 1

RP# Transitions ................................. 24

.............................................

........................................

.............................

................................ .2?

...............

................................ 24

.....................

............................... 25

...............

........................................ 27

.............

........................

............................

.......

.2?

25

.2f

.24

.2E

.2E

.34
.3E
.3E

.3E

.40

Rev. 1.0

J

LHF08CH2 2

LH28F008SCR-L85

8-MBIT (1 MB x 8)

SmartVoltage Flash MEMORY

n SmartVoltage Technology n Enhanced Automated Suspend Options

-

2.7V(Read-Only), 3.3V or 5V VCC

-

3.3V, 5V or 12V Vpp

n High-Performance Read Access Time

-

85ns(5V-c0.25V), 90ns(5Vk0.5V),
120ns(3.3V=0.3V), 150ns(2.7V-3.6V) - Absolute Protection with Vpp=GND

n Operating Temperature

- 0°C to +7O”C

-

Byte Write Suspend to Read

-

Block Erase Suspend to Byte Write

-

Block Erase Suspend to Read

n Enhanced Data Protection Features

-

Flexible Block Locking

- Block Erase/Byte Write Lockout
during Power Transitions

n High-Density Symmetrically-Blocked

Architecture

-

Sixteen 64-Kbyte Erasable Blocks -

n Low Power Management

-

Deep Power-Down Mode -

-

Automatic Power Savings Mode
Decreases ICC in Static Mode

I Automated Byte Write and Block Erase

-

Command User Interface

n Extended Cycling Capability

-

100,000 Block Erase Cycles

1.6 Million Block Erase Cycles/Chip

n Industry-Standard Packaging

40-Lead TSOP (Reverse Bend)

n ETOXTM* Nonvolatile Flash Technology
n CMOS Process

(P-type silicon substrate)

- Status Register
n Not designed or rated as radiation

I SRAM-Compatible Write Interface

SHARP’s LH28F008SCFGL85 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile,
,ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
ind extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F008SCR-L85 offers three levels of protection: absolute protection with V,, at
;ND, selective hardware block locking, or flexible software block locking. These alternatives give designers
Jltimate control of their code security needs.

hardened

The LH28F008SCR-L85 is manufactured on SHARP’s 0.38um ETOXTM process technology. It come in
ndustry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA
architecture, the LH28F008SCR-L85 enables quick and easy upgrades for designs demanding the state-of-the-art.

ETOX is a trademark of Intel Corporation.

Rev.1.11

SHARf=@

LHF08CH2 3

1 INTRODUCTION

This datasheet contains LH28F008SCRL85
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SCRL85
Flash memory documentation also includes
application notes and design tools which are
referenced in Section 7.

1.1 New Features

The LH28F008SCRL85 SmartVoltage Flash memory
maintains backwards-compatibility with SHARP’s
?8F008SA. Key enhancements over the 28F008SA

nclude:

*SmartVoltage Technology
*Enhanced Suspend Capabilities
*In-System Block Locking

30th devices share a compatible pinout, status
,egister, and software command set. These
similarities enable a clean upgrade from the
!8F008SA to LH28F008SCR-L85. When upgrading,
t is important to note the following differences:

*Because of new feature support, the two devices

have different device codes. This allows for
software optimization.

l

VPPLK has been lowered from 69 to 1.5V to

support 3.3V and 5V block erase, byte write, and

lock-bit configuration operations. The V,, voltage
transitions to GND is recommended for designs
that switch V,, off during read operation.

*To take advantage of SmartVoltage technology,

allow V,, connection to 3.3V or 5V.

I .2 Product Overview

SmartVoltage technology provides a choice of V,,
and V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 2.7V
Vc, consumes approximately one-fifth the power of
5V Voo. But, 5V Voo provides the highest read
performance. V,, at 3.3V and 5V eliminates the need
for a separate 12V converter, while V,,=12V
maximizes block erase and byte write performance
In addition to flexible erase and program voltages

the dedicated V,, p in ives complete data protectior g

when V,, I VPPLK.

Table 1. V,, and VP, Voltage Combinations

>

NOTE:

1. Block erase, byte write and lock-bit configuratior
operations with Vcoc3.OV are not supported.

Internal
automatically configures the device for optimizec
read and write operations.

A Command User Interface (CUI) serves as the

interface between the system processor and interna

operation of the device. A valid command sequence
written to the CUI initiates device automation. Ar
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, byte write, and lock-bit configuratior
operations.

A block erase operation erases one of the device’s
64-Kbyte blocks typically within 0.3 s (5V V,,, 12V
V,,) independent of other blocks. Each block can be
independently erased 100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.

Vcc

and

VP,

detection Circuit4

‘he LH28F008SCR-L85 is a high-performance 8-Mbit
;martVoltage Flash memory organized as 1 Mbyte of
I bits. The 1 Mbyte of data is arranged in sixteen
ICKbyte blocks which are individually erasable,
jckable, and unlockable in-system. The memory
lap is shown in Figure 3.

Writing memory data is performed in byte increments
typically within 6 us (5V Voo, 12V VP,). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.

Rev. 1.2

SHAM=

LHF08CH2 4

Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase

and byte write operations, while the master lock-bit
gates block lock-bit modification. Lock-bit
configuration operations (Set Block Lock-Bit, Set

Master Lock-Bit, and Clear Block Lock-Bits
commands) set and cleared lock-bits.

The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY/BY# minimizes
both CPU overhead and system power consumption.

When low, RY/BY# indicates that the WSM is
oerforming a block erase, byte write, or lock-bit
zonfiguration. RY/BY#-high indicates that the WSM is
?eady for a new command, block erase is suspended
[and byte write is inactive), byte write is suspended,
or the device is in deep power-down mode.

The access time is 85 ns (t,.,,,*,,) over the commercia
temperature range (0°C to +70X) and Vco supply
voltage range of 4.75V-5.25V. At lower Vco voltages,

the access times are 90 ns (4.5V-5SV), 120 ns

(3.OV-3.6V) and 150 ns (2.7V-3.6V).
The Automatic Power Savings (APS) feature

substantially reduces active current when the device

is in static mode (addresses not switching). In APS
mode, the typical I,,, current is 1 mA at 5V Vcc.

When CE# and RP# pins are at Voc, the ICC CMOS
standby mode is enabled. When the RP# pin is al
GND, deep power-down mode is enabled which

minimizes power consumption and provides write
protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are

valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status

register is cleared.

The device is available in 40-lead TSOP (Thin Small
Outline Package, 1.2 mm thick, Reverse Bend).

Pinout is shown in Figure 2.

Rev.1.0

SHARP

r

LHF08CH2

.

.

3

+ * . . . . . . . . . . fff

5

CE#
\VE#
(X3

RPb’

NC
NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

vcc

GND
GND

DQ3

DQ2
DQl
DQo

2

A2
A3

Figure 1. Block Diagram

40-LEAD TSOP

STANDARD PINOUT

1 Omm x 20mm

TOP VIEW

Figure 2. TSOP 40-Lead Pinout (Reverse Bend)

49

A16
A17
Al6
A15
A14
A13
A12

CE#

vcc

VPP

RP#

41

40
A9
A6

A7
A6
A5
A4

Rev. 1 .ll

Sl-iARP

r

Symbol

A&

DQc-DQ,

RY/BY#

CE#

RP#

OE#

WE#

“PP

“CC

GND

NC

9

Type

INPUT

INPUT/

OUTPUT

INPUT

INPUT

INPUT
INPUT

OUTPUT

SUPPLY

SUPPLY

SUPPLY

LHF08CH2

Table 2. Pin Descriptions

Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.

DATA INPUT/OUTPUTS: Inputs data and commands durino CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits

write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at V,, enables setting of the

master lock-bit and enables configuration of block lock-bits when the master lock-bit is

set. RP#=V,, overrides block lock-bits thereby enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with VIH<RP#cVHH produce spurious results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is

suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is

deselected or data outputs are disabled.

BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY: For
erasing array blocks, writing bytes, or configuring lock-bits. With VppIVpp,k, memory
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an

invalid Vpp (see DC Characteristics) produce spurious results and should not be
attempted.
DEVICE POWER SUPPLY: Internal detection confioures the device for 2.7V, 3.3” or 5V

operation. To switch from one voltage to another, ramp V,, down to GND and then ramp
Vo, to the new voltage. Do not float any power pins. With VcorV,,,, all write attempts
to the flash memory are inhibited. Device operations at invalid Vcc voltage (see DC
Characteristics) produce spurious results and should not be attempted. Block erase, byte

write and lock-bit configuration operations with Vcr.<3.0V are not supported.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.

6

1

Rev. 1.0

LHF08CH2 7

2 PRINCIPLES OF OPERATION

The LH28F008SCR-L85 SmartVoltage Flash memory

includes an on-chip WSM to manage block erase,
byte write, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed power
supplies during block erasure, byte write, and lock-bit
configuration, and minimal processor overhead with

RAM-Like interface timings.
After initial device power-up or return from deep

power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.

Status register and identifier codes can be accessed
through the CUI independent of the V,, voltage. High
voltage on V,, enables successful block erasure,
byte writing, and lock-bit configuration. All functions
associated with altering memory contents-block
erase, byte write, Lock-bit configuration, status, and
identifier codes-are accessed via the CUI and
verified through the status register.

Commands

are
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
byte write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs

array data, accesses the identifier codes, or outputs
status register data.

nterface software that initiates and polls progress of

,lock erase, byte write, and lock-bit configuration can
Ie stored in any block. This code is copied to and
executed from system RAM during flash memory
Jpdates. After successful completion, reads are
igain possible via the Read Array command. Block
erase suspend allows system software to suspend a
Ilock erase to read or write data from any other
Ilock. Byte write suspend allows system software to
suspend a byte write to read data from any other

lash memory array location.

written using standard

FFFFF I

F0000

EFFFF

EOOOO

DFFFF

DO000

CFFFF

coooo

BFFFF

BOOW

AFFFF

AOODO

BFFFF

9Qooo

6FFFF

Kmo

7FFFF

70000

BFFFF

60000

SFFFF

sow0

4FFFF

40000

JFFFF

30000

PFFFF

2oooo

1 FFFF

1oocil

OFFFF

00000 ’

I

I

I

t

64-Kbyte Block

131

64-Kbyte Block 12

64-Kbyte Block

81

64-Kbyte Block 7
64-Kbyte Block

61

64-Kbyte Block 5

64-Kbyte Block

4

64-Kbyte Block 1
64-Kbyte Block 0

I

Hgure 3. Memory Map

1 Data Protection

2.’

Depending on the application, the system designer
may choose to make the V,, power supply
switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to VPPHIj2/s. The device
accommodates either design practice and
encourages optimization of the processor-memory
interface.

When Vp+VppLK,

memory contents cannot be

altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V,,. All write
functions are disabled when Vcc is below the write

lockout voltage VLKO or when RP# is at V,,. The
device’s block locking capability provides additional
protection from inadvertent code or data alteration by
gating erase and byte write operations.

Rev. 1.0

LHFOSCH2

a

3 BUS OPERATION

The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes, or status register independent of the V,,

voltage. RP# can be at either V,, or V,,.
The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes, or

Read Status Register) to the CUI. Upon initial device
power-up or after exit from deep power-down mode,
the device automatically resets to read array mode.

Four control pins dictate the data flow in and out of
the component: CE#, OE#, WE#, and RP#. CE# and
OE# must be driven active to obtain data at the
outputs. CE# is the device selection control, and
when active enables the selected memory device.
OE# is the data output (DQo-DQ,) control and when
active drives the selected memory data onto the I/O
bus. WE# must be at V,, and RP# must be at V,, or
V,,. Figure 15 illustrates a read cycle.

3.2 Output Disable

With OE# at a logic-high level (V,,), the device
outputs are disabled. Output pins DQc-DQ, are
3laced in a high-impedance state.

3.3 Standby

ZE# at a logic-high level (V,,) places the device in
standby mode which substantially reduces device
lower consumption. DQc-DQ, outputs are placed in
3 high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
:onfiguration, the device continues functioning, and

consuming active power until the operatior

completes.

3.4 Deep Power-Down

RP# at V,, initiates the deep power-down mode.

In read modes, RP#-low deselects the memory
places output drivers in a high-impedance state ant
turns off all internal circuits. RP# must be held low foi
a minimum of 100 ns. Time tPHQv is required after
return from power-down until initial memory access

outputs are valid. After this wake-up interval, norma
operation is restored. The CUI is reset to read array

mode and status register is set to 80H.
During block erase,

configuration
operation. RY/BY# remains low until the resei
operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP#
goes to logic-high (VI,) before another command can
be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash

memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array
data. SHARP’s flash memories allow proper CPU
initialization following a system reset through the use

of the RP# input. In this application, RP# is controlled
by the same RESET# signal that resets the system
CPU.

modes, - ’

~;~low~rit~~ll o;botck;;;

Rev. 1.0

LHF08CH2 9

5

Read Identifier Codes Operation

re read identifier codes operation outputs the
anufacturer code, device code, block lock
nfiguration codes for each block, and the master
:k configuration code (see Figure 4). Using the
anufacturer and device codes, the system CPU can
rtomatically match the device with its proper
gorithms. The block lock and master lock
nfiguration codes identify locked and unlocked
lcks and master lock-bit setting.

FOO02 1

FOOOI

FOOOO

Block 15 Lock Configuration Code

Reserved for

Future Implementation

(Blocks 2 through 14)

3.6 Write

Writing commands to the CUI enable reading o
device data and identifier codes. They also contra

inspection and clearing of the status register. Wher

VPP=VPPHt/2/3, the CUI additionally controls bloc1
erasure, byte write, and lock-bit configuration.

The Block Erase command requires appropriatt
command data and an address within the block to bc
erased. The Byte Write command requires the
command and address of the location to be written
Set Master and Block Lock-Bit commands require the
command and address within the device (Maste
Lock) or block within the device (Block Lock) to bc
locked. The Clear Block Lock-Bits command require:
the command and address within the device.

The CUI does not occupy an addressable memog
location. It is written when WE# and CE# are active
The address and data needed to execute a commanc
are latched on the rising edge of WE# or CEf
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled write operations.

4 COMMAND DEFINITIONS

1FFFF

10004
10003

100021

10001

10000

OFFFF

00004
00003
00002

00001

‘igure

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

.

Btock 1

Reserved for

Future Implementation

Master Lock Configuration Code
Block 0 Lock Configuration Code

______---____-----__~-------------~~~~
__-------_--------~--------~~~~~~~~~~

Device Code

Manufacturer Code

4. Device Identifier Code Memory Map

1

When the V,,

voltage I V,,,,, Read operation:
from the status register, identifier codes, or block:
are enabled. Placing VPPHlIti3 on V,, enable:

successful block erase, byte write and lock-bi

configuration operations.

Device operations are selected by writing specific
commands into the CUI. Table 4 defines the.%
commands.

Rev. 1.0

LHF08CH2

10

Table 3. Bus Operations

Mode Notes

Read
Output Disable
Standby

Deep Power-Down

Read Identifier Codes

Write

RP# CE# OE#

1,2,3,8

3
3

4
8

3,6,7,8 v$+ Or

V$H or

HH

‘1, Or

VHH

viH Or

VHH

V,, X X X

vlH Or

V#

HH

WE# Address Vpp

“IL “IL “I,

“IL “I,

“I,

“IL “IL

“IL “I, “IL

X X

“I,

“I,

X
X
X X

X X

See

Figure 4

X X

DQIL,

X

DOUT

X High Z

High Z X
High Z Vnl,

X

Note 5

DlN

RY/BY#

X
X

‘OH

X

UOTES:
I. Refer to DC Characteristics. When Vpp<VppLk,

memory contents can be read, but not altered.

?. X can be V,, or VI, for control pins and addresses, and VppLk or VppHt/tis for Vpp. See DC Characteristics for

“PPLK and VPPH1/2/3 vOitages.

3. RY/BY# is VoL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms.
It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write
suspend mode, or deep power-down mode.

t. RP# at GNDf0.2V ensures the lowest deep power-down current.

5. See Section 4.2 for read identifier code data.

3. Command writes involving block erase, write, or lock-bit configuration are reliably executed when Vpp=Vpp~t/2/3

and “CC=“CC2/3/4

spurious results and should not be attempted.

Block erase, byte Write?, or lock-bit COnfigUratiOn with vCC<3.0v or VIH<Rf%<VHH-prOdUCe

7. Refer to Table 4 for valid DIN during a write operation.

3. Don’t use the timing both OE# and WE# are VI,.

Rev. 1.0

LHF08CH2

Table 4. Command Definitions(g)

Bus Cycles

,

Read Array/Reset 1 1 Write 1 X 1 FFH 1

Command

Req’d. Notes Oper(l) 1 Add&*) 1 Data@) 1 Oper(l) 1 Addr(*) 1 Data(3)

First Bus Cycle

Read Identifier Codes 22 1 4 1 Write [ X ( 90H I Read 1 IA ID I
Read Status Register 2

Clear Status Register
Block Erase

2

1

5 Write BA 20H

Write X 70H Read
Write X 50H

40H

1 Byte Write

2 1 56 1 Write 1 WA 1 or I Write I WA I WD /I

I

10H

Block Erase and Byte Write
co ,.-..A”4

Block Eraseand Byte Write

/

rlC’3”I I Icz

Set Block Lock-Bit

1 / 5 / Write ( X ( DOH (

2 7 Write BA 60H

5 Write X BOH

Set Master Lock-Bit 2 7 Write X 60H
Clear Block Lock-Bits

2 8 Write X 60H

NOTES:

1. BUS operations are defined in Table 3.

2. X=Any valid address within the device.
IA=ldentifier Code Address: see Figure 4.
BA=Address within the block being erased or locked.

WA=Address of memory location to be written.

3. SRD=Data read from status register. See Table 7 for a description of the status register bits.

WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).

ID=Data read from identifier codes.

4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and

master lock codes. See Section 4.2 for read identifier code data.

5. If the block is locked, RP# must be at V,, to enable block erase or byte write operations. Attempts to issue a

block erase or byte write to a locked block while RP# is VI,.

6. Either 40H or 10H are recognized by the WSM as the byte write setup.

7. If the master lock-bit is set, RP# must be at V,,

to set a block lock-bit. RP# must be at V,, to set the master

lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VI,.

8. If the master lock-bit is set, RP# must be at V,, to clear block lock-bits. The clear block lock-bits operation

simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can
be done while RP# is V,,.

9. Commands other than

those shown above are reserved by SHARP for future device implementations and

should not be used.

Second Bus Cycle

X SRD

Write BA DOH

Write BA OlH
Write X FlH
Write X DOH

Rev. 1 .O

LHF08CH2

12

4.1 Read Array Command

Upon initial device power-up and after exit from deep
oower-down mode, the device defaults to read array
node. This operation is also initiated by writing the
Read Array command. The device remains enabled

‘or reads until another command is written. Once the

nternal WSM has started a block erase, byte write or
ock-bit configuration, the device will not recognize

:he Read Array command until the WSM completes

ts operation unless the WSM is suspended via an
Erase Suspend or Byte Write Suspend command.
The Read Array command functions independently of
:he V,, voltage and RP# can be V,, or V,,.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the
qead Identifier Codes command. Following the

:ommand write, read cycles from addresses shown in
‘igure 4 retrieve the manufacturer, device, block lock
:onfiguration and master lock configuration codes

see Table 5 for identifier code values). To terminate

he operation, write another valid command. Like the
?ead Array command, the Read Identifier Codes
:ommand functions independently of the V,, voltage
%nd RP# can be V,, or V,,. Following the Read
dentifier Codes command, the following information
:an be read:

Table 5. Ideni

Code

Manufacture Code

Device Code
Block Lock Configuration
*Block is Unlocked

*Block is Locked
*Reserved for Future Use

Master Lock Configuration
@Device is Unlocked
*Device is Locked
*Reserved for Future Use

30TE:

. X selects the specific block lock configuration

code to be read. See Figure 4 for the device

identifier code memory map.

ier Codes tifi

1

4.3 Read Status Register Command

The status register may be read to determine when i
block erase, byte write, or lock-bit configuration is
complete and whether the operation completec
successfully. It may be read at any time by writing the

Read Status Register command. After writing this
command, all subsequent read operations outpu’
data from the status register until another valic
command is written. The status register contents arc
latched on the falling edge of OE# or CE#, whichevel

occurs. OE# or CE# must toggle to V,, before further

reads to update the status register latch. The Reac
Status Register command functions independently o

the V,, voltage. RP# can be V,, or V,,.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.l are
set to “1 “s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 7). By allowing
system software to reset these bits, several
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence)
may be performed. The status register may be polled

to determine if an error occurre during the sequence.
To clear the status register, the Clear Status Register

command (50H) is written. It functions independently
of the applied V,,

This command is not functional during block erase or
byte write suspend modes.

Voltage. RP# can be V,, or V,,.

4.5 Block Erase Command

Erase is executed one block at a time and initiated by
a two-cycle command. A block erase setup is first
written, followed by an block erase confirm. This
command sequence requires appropriate sequencing
and an address within the block to be erased (erase
changes all
preconditioning, erase, and verify are handled

internally by the WSM (invisible to the system). After
the two-cycle block erase sequence is written, the
device automatically outputs status register data
when read (see Figure 5). The CPU can detect block
erase completion by analyzing the output data of the

RY/BY# pin or status register bit SR.7.

block data to FFH). Block

Rev. 1.0

LHF08CH2 13

When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI

remains in read status register mode until a new
command is issued.

This two-step command sequence of set-up followed

by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to “1 ‘I. Also, reliable block erasure
can only occur when
v,,=v

PPi+l2/3*

block contents are protected against erasure. If block
erase is attempted while Vpp&,,,k, SR.3 and SR.5
will be set to “1”. Successful block erase requires that
the corresponding block lock-bit be cleared or, if set,

that RP#=V,,.
corresponding block lock-bit is set and RP#=V,,,
SR.l and SR.5 will be set to “1”. Block erase
operations with V,,cRP#cVH, produce spurious
results and should not be attempted.

In the absence of this high voltage,

If block erase is attempted when the

vCC=vCC2/314

and

4.6 Byte Write Command

Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the

-ising edge of WE#). The WSM then takes over,
controlling the byte write and write verify algorithms

nternally. After the byte write sequence is written, the
device automatically outputs status register data

Nhen read (see Figure 6). The CPU can detect the
zompletion of the byte write event by analyzing the
?Y/BY# pin or status register bit SR.7.

Nhen byte write is complete, status register bit SR.4
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1 “s that do not
juccessfully write to “0”s. The CUI remains in read
status register mode until it receives another
:ommand.

qeliable byte writes can only occur when
Jcc=Vcc2/3,4 and VPrz~VPPr+t/2/3. In the absence of

his high voltage, memory contents are protected
against byte writes. If byte write is attempted while

/+V,,,,, status register bits SR.3 and SR.4 will be
ret to “1 ‘I. Successful byte write requires that the

corresponding block lock-bit be cleared or, if set, tha

RP#=V,,. If byte write is attempted when the
corresponding block lock-bit is set and RP#=V,,
SR.1 and SR.4 will be set to “1”. Byte write
operations with V,,cRP#cVHH produce spurious
results and should not be attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows
block-erase interruption to read or byte-write data ir
another block of memory. Once the block-erase
process starts, writing the Block Erase Suspenc
command requests that the WSM suspend the block
erase sequence at a predetermined point in the
algorithm. The device outputs status register data
when read after the Block Erase Suspend commanc
is written. Polling status register bits SR.7 and SR.E
can determine when the block erase operation has
been suspended (both will be set to “1”). RY/BY# will
also transition to V,,. Specification twHRH2 defines

the block erase suspend latency.
At this point, a Read Array command can be written

to read data from blocks other than that which is
suspended. A Byte Write command sequence can
also be issued during erase suspend to program data
in other blocks. Using the Byte Write Suspend
command (see Section 4.8), a byte write operation
can also be suspended. During a byte write operation
with block erase suspended, status register bit SR.7
will return to “0” and the RY/BY# output will transition

to V,,. However, SR.6 will remain “1” to indicate

block erase suspend status.

The only other valid commands while block erase is
suspended are Read Status Register and Block

Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically clear and

RY/BY# will return to VOL. After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 7). V,,
must remain at V,PH1,2,3 (the same V,, level used

for block erase) while block erase is suspended. RP#

must also remain at V,, or V,, (the same RP# level
used for block erase). Block erase cannot resume
until byte write operations initiated during block erase

suspend have completed.

Rev.

1.0

LHF08CH2

14

4.8 Byte Write Suspend Command

The Byte Write Suspend command allows byte write
interruption to read data in other flash memory
locations. Once the byte write process starts, writing

the Byte Write Suspend command requests that the

WSM suspend the byte write sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.

Polling status register bits SR.7 and SFi.2 can
determine when the byte write operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to VOH. Specification tWHRHl defines the
byte write suspend latency.

At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
byte write is suspended are Read Status Register
and Byte Write Resume. After Byte Write Resume

command is written to the flash memory, the WSM
will continue the byte write process. Status register
bits SR.2 and SR.7 will automatically clear and

RY/BY# will return to V,,. After the Byte Write
Resume command is written, the device

automatically outputs status register data when read
(see Figure 8). V,,
same V,, level used for byte write) while in byte write
suspend mode. RP# must also remain at V,, or V,,
(the same RP# level used for byte write).

must remain at VPPH1,2,3 (the

the RP# pin. See Table 6 for a summary of hardwar’

1

and software write protection options.
Set block lock-bit and master lock-bit are executed b

a two-cycle command sequence. The set block c
master lock-bit setup along with appropriate block c
device address is written followed by either the SE
block lock-bit confirm (and an address within thl
block to be locked) or the set master lock-bit confirr

(and any device address). The WSM then control
the set lock-bit algorithm. After the sequence i
written, the device automatically outputs statu
register data when read (see Figure 9). The CPU car
detect the completion of the set lock-bit event b
analyzing the RY/BY# pin output or status register bi
SR.7.

When the set lock-bit operation is complete, statu:
register bit SR.4 should be checked. If an error i:

detected, the status register should be cleared. The
CUI will remain in read status register mode until :
new command is issued.

This two-step sequence of set-up followed b!
execution ensures that lock-bits are not accidentall!
set. An invalid Set Block or Master Lock-B/
command will result in status register bits SR.4 ant
SR.5 being set to “1”. Also, reliable operations occu
only when Vcc=Vcc2,3,4 and VPP=VPPH,,2,3. In tht

absence of this high voltage, lock-bit contents arc

protected against alteration.

4.9 Set Block and Master Lock-Bit
Commands

4 flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program and
erase operations while the master lock-bit gates
3lock-lock bit modification. With the master lock-bit
lot set, individual block lock-bits can be set using the
Set Block Lock-Bit command. The Set Master

-ock-Bit command, in conjunction with RP#=V,,,

jets the master lock-bit. After the master lock-bit is
jet, subsequent setting of block lock-bits requires
10th the Set Block Lock-Bit command and V,, on

A successful set block lock-bit operation requires tha
the master lock-bit be cleared or, if the maste
lock-bit is set, that RP#=V,,. If it is attempted wit1
the master lock-bit set and RP#=V,,, SR.l and SR.l
will be set to “1” and the operation will fail. Set block
lock-bit operations while VIH<RP#cVHH produce
spurious results and should not be attempted. P
successful set master lock-bit operation requires tha,
RP#=V,,. If it is attempted with RP#=V,,, SR.l ant

SR.4 will be set to “1” and the operation will fail. Se

master lock-bit operations with V,,cRP#cV,,
produce spurious results and should not be
attempted.

Rev. 1.0

LHF08CH2

15

l.10 Clear Block Lock-Bits Command

411 set block lock-bits are cleared in parallel via the
Zlear Block Lock-Bits command. With the master
ock-bit not set, block lock-bits can be cleared using
)nly the Clear Block Lock-Bits command. If the
naster lock-bit is set, clearing block lock-bits requires
10th the Clear Block Lock-Bits command and V,, on
he RP# pin. See Table 6 for a summary of hardware
md software write protection options.

Zlear block lock-bits operation is executed by a
wo-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
vhen read (see Figure 10). The CPU can detect
:ompletion of the clear block lock-bits event by
analyzing the RYIBY# Pin output or status register bit
SR.7.

Yhen the operation is complete, status register bit
jR.5 should be checked. If a clear block lock-bit error
s detected, the status register should be cleared.
‘he CUI will remain in read status register mode until
nother command is issued.

This two-step sequence of set-up followed b\

execution ensures that block lock-bits are no

accidentally cleared. An invalid Clear Block Lock-Bit:

command sequence will result in status register bit:

SR.4 and SR.5 being set to “1”. Also, a reliable clea

block lock-bits operation can only occur wher

Vcc=Vcc2/3,4 and VPP=VPPHI12/s. If a clear bloc1

lock-bits operation is attempted while V,,rV,,,,

SR.3 and SR.5 will be set to “1”. In the absence o

this high voltage, the block lock-bits content arc

protected against alteration. A successful clear bloc1

lock-bits operation requires that the master lock-bit i:

not set or, if the master lock-bit is set, that RP#=V,,

If it is attempted with the master lock-bit set ant

RP#=V,,, SR.1 and SR.5 will be set to “1” and the
operation will fail. A clear block lock-bits operatior
with V,,cRP#cV,, p reduce spurious results ant
should not be attempted.

If a clear block lock-bits operation is aborted due tc
V,, or Vc, transitioning out of valid range or RP#
active transition, block lock-bit values are left in ar
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents tc
known values. Once the master lock-bit is set, ii

cannot be cleared.

Table 6. Write Protection Alternatives

1 Master 1 Block 1

Operation 1 Lock-Bit 1 L
Block Erase or
Byte Write

Set Block

Lock-Bit

Set Master 1 X 1 X V,H
Lock-Bit
Clear Block
Lock-Bits

X

0

1

0 X

1 X

X VI,, or VWH Set Block Lock-Bit Enabled
X V,H Master Lock-Bit is Set. Set Block Lock-Bit Disabled

I \I

“HH

VHH
V

V 0rV

V

B

\I

“HH

Effect
Block Erase and Byte Write Enabled
Block is Locked. Block Erase and Byte Write Disabled

1 Block Lock-Bit Override. Block Erase and Bvte Write

Enabled

1 Master Lock-Bit Override. Set Block Lock-Bit Ena bled
1 Set Master Lock-Bit Disabled

Set Master Lock-Bit Enabled
Clear Block Lock-Bits Enabled

Master Lock-Bit is Set. Clear Block Lock-Bits Disabled

Master Lock-Bit Override. Clear Block Lock-Bits

1 Enabled

Rev. 1 .O

SHARP

LHF08CH2

Table 7. Status Register Definition

WSMS / ESS

7 6 5 4 3 2

SR.7 = WRITE STATE MACHINE STATUS Check RY/BY# or SR.7 to determine block erase, byte

1 = Ready write, or lock-bit configuration completion.

0 = Busy SR.6-0 are invalid while SR.7=“0”.

SR.6 = ERASE SUSPEND STATUS If both SR.5 and SR.4 are “1”s after a block erase or

1 = Block Erase Suspended lock-bit configuration attempt, an improper command

0 = Block Erase in Progress/Completed sequence was entered.

SR.5 = ERASE AND CLEAR LOCK-BITS STATUS SR.3 does not provide a continuous indication of V,,

1 = Error in Block Erasure or Clear Lock-Bits level. The WSM interrogates and indicates the V,, level

0 = Successful Block Erase or Clear Lock-Bits

SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS SR.3 is not guaranteed to reports accurate feedback

1 = Error in Byte Write or Set Master/Block Lock-Bit

0 = Successful Byte Write or Set Master/Block

Lock-Bit

SR.3 = V,, STATUS

1 = V,, Low Detect, Operation Abort

O=V,,OK

SR.2 = BYTE WRITE SUSPEND STATUS

1 = Byte Write Suspended

0 = Byte Write in Progress/Completed

SR.l = DEVICE PROTECT STATUS

1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock SR.0 is reserved for future use and should be masked

Detected, Operation Abort

0 = Unlock

1 ECLBS 1 BWSLBS 1 VPPS 1 BWSS 1 DPS R

1 0

NOTES:

only after Block Erase, Byte Write, Set Block/Master
Lock-Bit, or Clear Block Lock-Bits command sequences.

only

when V,,#V,,,,,~,,.

SR.l does not provide a continuous indication of master
and block lock-bit values. The WSM interrogates the
master lock-bit, block lock-bit, and RP# only after Block
Erase, Byte Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set, master
lock-bit is set, and/or RP# is not V,,. Reading the block
lock and master lock configuration codes after writing
the Read Identifier Codes command indicates master
and block lock-bit status.

out when polling the status register.

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS

LHF08CH2

Check if Desired

FULLSTATUSCHECKPROCEDURE

Command

/ write 1 EraseSetup 1 Data=20H

write

Read

Standby

Full status check can be done after each block erase or after a sequence of

block erasures.

Wnte FFH after the last operation to place device in read array mode.

BUS

Operation

Command

I

Addr=Wlthin Block to be Erased

Data-DOH

Addr=Withm Block to be Erased

Status Rqster Data

Check SR.7
,=WSM Ready

O=WSM Busy

Comments

Comments

Block Erase Successful

Standby

Standby

;R.5,SR.4.SR.3 and SR., are only cleared by the Clear Status

Register Command in casas where multiple blocks are erased
before full status is checked.

error is detected. clear the Status Register before attempting

retry or other error recovery.

Block Erase Error

Figure 5. Automated Block Erase Flowchart

Check SR.3

l=Vpp Error Detect

Check SR. 1

l=Device Protect Detect

RP#=V,,+Block Lock-Bit is Set

Only required for systems

implementing lock-bit configuration

Check SR.4,5

Both t=Command Sequence Error

Check SR.5

l=Block Erase Error

Rev. 1.0

SHARI=

Suspend Byte

write Loop

LHF08CH2

Command Comments

write Setup Byte Write

Wnte Byte Wnte

Read

Standby

Repeat for subsequent byte writes.
SR full status check can be done after each byte write. or after a sequence of

byte writes.

Wnte FFH after the last byte write operation to

read array mode.

DatedOH
AddkLwabon to Be Wlitten

Data=Data to Be Written
Addr=Lccation to Be Written

Status Register Data

Check SR.7
l=WSM Ready
O=WSM Busy

place

device III

18

FULL STATUS CHECK PROCEDURE

Byte Wnte Successful

Device Protect Error

Figure 6. Automated Byte Write Flowchart

Command

Standby

Standby

Standby

57.4.SR.3 and SR. 7 are only cleared by the Clear Status Regtster
command in cases where multiple locations are written before
full status is checked.

I

f error is detected, clear the Status Register before attempting

retry or other error reco”ely.

Check SR.3
1+,x Error Detect

Check SR. 1

l=Devse Protect Detect
RP#=VIH,Block Lock-Bit is Set
Only required for systems
Implementing lock-btt configuration

Check SR.4
l=Data Wnte Error

Comments

Rev. 1 .O

LHF08CH2

start

Write BOH

Status Register

Bus

Operation

write

Command

El-&%

Resume Addr=X

I

Check 533.7
1 =WSM Reacty

o=WSM Busy

Check SR.6
l=Block Erase Suspended
O=Block Erase Completed

Data=DOH

Comments

I

Figure 7. Block Erase Suspend/Resume Flowchart

Rev. 1.0

r

LHF08CH2

Bus

Operation

write

Read

standby

SR.7=

i:t

0

standby

1

Command

Byte Write

Suspend

Read Army

I

Data=BOH
Addr=X

status Regster Data

Addr=X

Check SR.7
1 =WSM Ready

O=WSM Busy

Check SR.2
l=Byte Write Suspended

o=Byte Write Completed

Data=FFH
Addr=X

Figure 8. Byte Write Suspend/Resume Flowchart

Rev. 1.0

SHARP

Write OIHIFIH,

Check If Desired

LHF08CH2

Bus

Operation

write

write

Read

Standby

Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-btt set oper’dtion

or after a sequence of lock-bit set operations.

Wnte FFH after the last lock-bit set operation to place device I”

read army mode.

Command

set

Block/Master

Lock-Bit Sehrp

set

Block or Master

Lock-Bit Confirm

21

Commenb

Data=6OH
Addr=Block Address(Block),

Dewca Address(Master)

Data=OlH(Block),

FlH(Master)

Addr=Blcck Address(Block),

Device Address(Master)

Status Register Data

Check SR.7

l=WSM Ready

O=WSM Busy

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

Set Lock-Bit Successful

Device Protect Error

Set Lock-Bit Error

BUS

Operation

Standby

Standby

Standby

Standby

SR.5.SR.4,SR.3 and SR.1 are only cleared by the Clear Status

Register command I” cases where multiple lock-bits are set before
full status is checked.

If error IS detected, clear the Status Register before attempting

retry or other error recovery.

Command

Check SR.3

t=VpP Error Detect

Check SR.1

I=Dewce Protect Detect

RP#+,

RP#=VIH, Master Lock-Bit is Set

Check SR.4,5
Both l=Command

Sequence Error

Check SR.4

l=Set Lock-Bit Error

Comment3

(Set Master Lock-Blt Operation)

(Set Block Lock-Blt Operation)

Figure 9. Set Block and Master Lock-Bit Flowchart

Rev. 1.0

LHF08CH2

22

Start

write 60H

x

SR.7=

+

Check If Desired

FULL STATUS CHECK PROCEDURE

0

1

BUS

Operation

WI-Its

Write

Read Status Register Data

Standby

\ Nrite FFH after the Clear Block Lock-Bits operation to

hate device in read array mode.

F

BUS

Operation

Standby

Command Comments

Clear Block

Lock-Bits Setup

Clear Block

Lock-Bits Confirm

Command

Data=M)H
Addr=X

Data=DOH

Addr=X

Check SA.7

l=WSM Ready

O=WSM Busy

Check SR.3

l=Vpp Error Detect

Comments

Device Protect Error

Figure 10. Clear Block Lock-Bits Flowchart

Standby

Standby

Standby

SR.5.SR.4.SR.3 and SR. 1 are only cleared by the Clear Status

Register command.

f error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR. 1

MJevice Pmtect Detect

RP#=V,H, Master Lock-Bit is Set

Check SR.4,5
Both l=Command

Sequence Error

Check SR.5

l&tear Block Lock-Bits Error

Rev. 1.0

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

LHFOSCH2 23

1

RY/BY# is also VOH when the device is in block eras
suspend (with byte write inactive), byte write suspenc
or deep power-down modes.

The device will often be used in large memory arrays.

SHARP provides three control inputs to
accommodate multiple memory connections.
Three-line control provides for:

a. Lowest possible memory power dissipation.

b. Complete assurance that data bus contention will

not occur.

To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected

memory

deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.

devices have active outputs while

5.2 RY/BY# and Block Erase, Byte Write,

and Lock-Bit Configuration Polling

RY/BY# is a full CMOS output that provides a
lardware method of detecting block erase, byte write
snd lock-bit configuration completion. It transitions
ow after block erase, byte write, or lock-bit
:onfiguration commands and returns to V,, when

he WSM has finished executing the internal
algorithm.

3Y/BY# can be connected to an interrupt input of the

;yStf?m

CPU or controller. It is active at all times.

5.3 Power Supply Decoupling

Flash memory power switching characteristics require
careful device decoupling. System designers arc

interested in three supply current issues; standb
current levels, active current levels and transien
peaks produced by falling and rising edges of CEI
and OE#. Transient current magnitudes depend OI
the device outputs’ capacitive and inductive loading
Two-line control and proper decoupling capacito
selection will suppress transient voltage peaks. Eacl
device should have a 0.1 uF ceramic capacito

connected between its Voo and GND and between it:
V,, and GND. These high-frequency, low inductance
capacitors should be placed as close as possible tc
package leads. Additionally, for every eight devices

a 4.7 uF electrolytic capacitor should be placed at the

array’s power supply connection between V,, ant

GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.

5.4 Vpp Trace on Printed Circuit Boards

Updating flash memories that reside in the targe

system requires that the printed circuit boarc
designer pay attention to the V,, Power supply trace
The V,, pin supplies the memory cell current for by&
writing and block erasing. Use similar trace width:
and layout considerations given to the Voc powel
bus. Adequate V,, supply traces and decoupling wil
decrease V,, voltage spikes and overshoots.

Rev. 1.0

LHF08CH2 24

5.5 Vcc, Vpp, RP# Transitions

Block erase, byte write and lock-bit configuration are
not guaranteed if V,n falls outside of a valid V,,,,,,,
range, Vcc falls outside of a valid Vcc2,3,4 range, or
RP#&,,, or V,,. If V,, error is detected, status

register bit SR.3 is set to “1” along with SR.4 or SR.5,
depending on the attempted operation. If RP#
transitions to V,, during block erase, byte write, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-down.
The aborted operation may leave data partially
altered. Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to V,, clear the status
register.

The CUI latches commands issued by system
software and is not altered by V,, or CE# transitions
or WSM actions. Its state is read array mode upon
sower-up, after exit from deep power-down or after
Vcc transitions below VLKO.

After block erase, byte write, or lock-bit configuration,
3ven after V,, transitions down to VpPLK, the CUI
nust be placed in read array mode via the Read
Array command if subsequent access to the memory
array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against
3ccidental block erasure, byte writing, or lock-bit
:onfiguration during power transitions. Upon
lower-up, the device is indifferent as to which power

supply (V,, or Vcc) powers-up first. Internal circuitr

1

resets the CUI to read array mode at power-up.
A system designer must guard against spuriou:

writes for Vcc voltages above VLKO when V,, i!
active. Since both WE# and CE# must be low for i
command write, driving either to VI, will inhibit writes
The CUl’s two-step command sequence architecturt
provides added level of protection against datr

alteration.

In-system block lock and unlock capability prevent:
inadvertent data alteration. The device is disablec

while RP#=V,, regardless of its control inputs state. ’

5.7 Power Dissipation

When designing portable systems, designers mus
consider battery power consumption not only durin!
device operation, but also for data retention during

system idle time. Flash memory’s nonvolatilih

increases usable battery life because data is retainec

when system power is removed.

In addition, deep power-down mode ensure:
extremely low power consumption even when systen
power is applied. For example, portable computing
products and other power sensitive applications tha
use an array of devices for solid-state storage car
consume negligible power by lowering RP# to VI,
standby or sleep modes. If access is again needed

the devices can be read following the tpHav ant
tPHWL wake-up cycles required after RP# is firs

raised to V,,. See AC Characteristics- Read Only

and Write Operations and Figures 15, 16 and 17 fol
more information.

Rev. 1.0

LHF08CH2 25

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings*

Operating Temperature

During Read, Block Erase, Byte Write

and Lock-Bit Configuration . . . . . . . . . ..O”C to +7O”C(1)

Temperature under Bias . . . . . . . . . . . . . . . -10°C to +8O”C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125”C

Voltage On Any Pin

(except Vcc, VP,,

V,, Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -2.ov to +7.0@)

V,, Update Voltage during

Block Erase, Byte Write and

Lock-Bit Configuration . . . . . . . . . . . -2.OV to +14.OV(2J)

RP# Voltage with Respect to

GND during Lock-Bit

Configuration Operations . . . . . . -2.OV to +14.0V(2J)

Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . 1 00mAc4)

and RP#) . . .._.. -2.OV to +7.OV@)

*WARNING: Stressing the device beyond the

“Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only. Operation
beyond the
recommended and extended exposure beyond the

“Operating Conditions” may affect device reliability.

NOTES:

1. Operating temperature is for commercial

temperature product defined by this specification.

2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on V,, and V,, pins. During

transitions, this level may undershoot to -2.OV for

periods <20ns.
input/output pins and Voc is Vcc+O.SI which,

during transitions, may overshoot to Vcc+2.OV for

periods c20ns.

3. Maximum DC voltage on V,, and RP# may

overshoot to +14.OV for periods <20ns.

4. Output shorted for no more than one second. No
more than one output shorted at a time.

“Operating Conditions ” is not

Maximum DC voltage on

6.2 Operating Conditions

Temperature and Vcc Operating Conditions

Symbol 1 Parameter 1 Notes Min. 1 Max. 1 Unit 1 Test Condition
T, ( Operating Temperature
Van, Vcc Supply Voltage (2.7V-3.6V) 1 2.7 3.6 V
Vr-c, Vnn Supply Voltage (3.3V+O.3V)
Voo2 Vnr. Supply Voltage (5V+O.25V) 4.75 5.25 V
V,, Vnn Supply Voltage (5V+O5V)

NOTE:

1. Block erase, byte write and lock-bit configuration operations with Vo,<3.OV should not be attempted.

6.2.1 CAPACITANCE(‘)
T,=+25”C, f=l MHz

Symbol Parameter
C,N Input Capacitance
Ca,T Output Capacitance

NOTE:

1. Sampled, not 100% tested.

Typ. Max.

6
8 12

4.50

1 +70 I “C I Ambient Temperature

0

3.0 3.6

5.50 V

8

V

Unit Condition

pF
pF v(-y ,J-=O.OV

v,,=o.ov

Rev. 1.11

LHF08CH2

1.2.2 AC INPUT/OUTPUT TEST CONDITIONS

1:; -T--,j(Z2~+--Y

AC test inputs are driven at 2.7V for a Logic “1” and O.OV for a Logic “0.” input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <IO ns.

Figure 11. Transient Input/Output Reference Waveform for Vcc=2.7V-3.6V

~~~~;~~~

AC test inputs are driven at 3.OV for a Logic “1” and O.OV for a Logic “0.” Input timing begins, and output timing ends, at 1.W.
Input rise and fall times (10% to 90%) <IO ns.

Figure 12. Transient Input/Output Reference Waveform for VcC=3.3V*0.3V and VcC=5V+0.25V

(High Speed Testing Configuration)

AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and V~L (0.45 V~L) for a Logic “0.” Input timing begins at VIH
(2.0 VmL) and VIL (0.8 V&. Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) ~10 ns.

Figure 13. Transient Input/Output Reference Waveform for Vcc=SV*O.SV

(Standard Testing Configuration)

Test Confi uration Ca acitance Loadin Value

1

DEVICE

UNDER 0 OUT

TEST

CL Includes Jig

Capacitance

Figure 14. Transient Equivalent Testing

Load Circuit

Rev. 1.2

L2.3 DC CHARACTERISTICS

LHF08CH2

27

Sym.

‘Li

‘LO

‘cc,

CCD

CCR

ccw

CCE

:cws
lxxs.
‘PS

TEL...­‘PD

‘PW

‘PE

‘PWS
9xS-

Parameter Votes

Input Load Current 1
Output Leakage Current 1
V,, Standby Current

Vcc Deep Power-Down
Current
dcc Read Current

ticc Byte Write or
Set Lock-Bit Current

dcc Block Erase or
Zlear Block Lock-Bits
Zurrent

I,, Byte Write or Block
irase Suspend Current

Ipp Standby or Read
hrrent

I,, Deep Power-Down
hrrent
fpp Byte Write or Set

.ock-Bit Current

Ipp Block Erase or
Zlear Lock-Bit Current

Ipp Byte Write or Block
:rase Suspend Current

1,3,6

1

133

I,7

1,7

v---

~

DC Ch

Vcc=2.7V

Typ. 1 Max.

I

*

20 100

kO.5
kO.5

racteristics al

-

Vcr
Lre,

20

100 25 100

=lx

0.1 2

I

0.2

7

12 17 35

l-l-

7 18 8 18 20 50

- -

I I

17 I - I -

- -

- -

- -

- -

- -

s

- ­_+2 *15

10 200

0.1 5

- -

- -

- -

- -’

- -

- -

A2

10

0.1 RP#=GND*0.2V

10

6 1 1 1 10 mA CE#=V,,, 1

40 - ­40 40

15 15
20 - ­20 20

15 15

200 10 200

_

Uni

IJA

CIA

IJA

Vcc=VccMax.

mA

CE#=RP#=V,,.,

RP#=GND*0.2V

PA

b, ,,(RY/BY#)=OmA

CMOS Inputs
Vcc=VCCMax.
CE#=GND

mA

f=5MHz(3.3V, 2.7V),

8MHz(5V)

In, ,T=OmA
TTL Inputs
V,,=V,,Max.
CE#=GND

mA

f=5MHz(3.3V, 2.7V),

8MHz(5V)

In, ,T=OmA
vDo=3.3v*o.3V

mA
mA

mA
mA

mA

mA

vpp_<v,,

&

\Ipp>Vcc.

CIA

IJA

mA

Vpp=3.3V~0.3V

dpp=5.0V+0.5V

mA
mA

Vpp=12.0V+0.6V

vpp=3.3v~o.3v

mA
mA

vpp=5.0v+o.5v

mA

VP,=1 2.OV&O.6V

Rev. 1.2

SHARP

Sym.

V,, Input Low Voltage 7

4,

VOL

I

VoHl Output High Voltage

VOH2 Output High Voltage

Parameter Notes

Input High Voltage

Output Low Voltage 3,7

V-J

(CMOS)

7

3,7

3,7

LHFOBCH2 28

:h ,aracteristics Continued

DCC

=;

&-.&

0.85

Yc.cL

!.7V Vcc=3.3V 1 Vc.,dV

Min.

Max. Min. Max. Min.

-0.5

2.0

0.8 -0.5 0.8 -0.5

Vcc

+0.5 2.0 vcc

2.4

I I

1 0.85 1 0.85

vcc

-0.4

+0.5

Test

2.0

Max.

0.8

VCC

+0.5

Unit

V
V

Conditions

Vcc=VccMin.

0.45

V

IO

loL=2.0mA

,=5.8mA(Vcc=5V),

(Vnn=3.3V, 2.7V)
Vcc=VcoMin.
loH=-2.%lA(vCc=5v),

V

lo,=-2.0mA(vcc=3.3v)

I

In,,=-1 .5mA(Vr.,=2.7V)

V
V

In!+=-1 OOuA

1.5

V

-

-

V

Lock-Bit Operations

V,,r+ V,, during Byte Write,

Block Erase or

-

5.5

V

Lock-Bit Operations

V,,Hs V,, during Byte Write,

Block Erase or

-

12.6

V

Lock-Bit Operations

V, kr, Vcr: Lockout Voltage

vHH

f?P# Unlock Voltage 8,9

2.0

-

- j 11.4 / 12.6 / 11.4 12.6

V

Set master lock-bit

V

Override master and
block lock-bit

IOTES:

. All currents are in RMS unless otherwise noted. Typical values at nominal Voc voltage and T,=+25”C. These

currents are valid for all product versions (packages and speeds).

. ‘CCWS and ‘CCES

are specified with the device de-selected. If read or byte written while in erase suspend mode,

the device’s current draw is the sum of lccws or IocEs and lCCR or I,,,, respectively.

‘. Includes RY/BY#.

. Block erases, byte writes, and lock-bit configurations are inhibited when V&J,,,,, and not guaranteed in the

range between VppLk(max.) and VppHt(min.), between Vnr+n(max.) and Vpp&min.), between Vpp&max.)
and VppHs(min.), and above VppHs(max.).

. Automatic Power Savings (APS) reduces typical I,,, to 1 mA at 5V Vcc and 3mA at 2.7V and 3.3V Voc in static

operation.
. CMOS inputs are either Vco- +0.2V or GNDk0.2V. TTL inputs are either V,, or Vi,.
. Sampled, not 100% tested.
. Master lock-bit set operations are inhibited when RP#=V,,. Block lock-bit configuration operations are inhibited

when the master lock-bit is set and RP#=VrH. Block erases and byte writes are inhibited when the corresponding
block-lock bit is set and RP#=VrH. Block erase, byte write, and lock-bit configuration operations are not
guaranteed with Vcc

<3.OV or VrH<RP#<VHH

and should not be attempted.

. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.

Rev. 1.2

LHFOSCH2

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(‘)

I

Versiond4)

Sym. 1

Parameter

tr,, nx OE# to Outr

GHC)7

LH

OE# High to Output in High Z
Output Hold from Address, CE# ot
Whichever Occurs First

NOTE:

See 5.OV V,, Read-Only Operations for notes 1 through 4.

Vc,,=2.7V-3.6V,

T,pO”C to +7O”C

LH28F008SGL150

1 Notes 1 Min.

3 0

.--

29

1

Max. 1 Unit 11

ns

Vc:,=3.3V+0.3V, Tg

Versiond4)

Sym.

tJ”A”

ta”n”

Read Cyc& Time
Addre:

Parameter

tF, (-Jv
tpwnv 1 RP# Hiqh to Output Delay

t

NOTE:
See 5.OV V,, Read-Only Operations for notes 1 through 4.

-0°C to +7O”C

1 Notes Min.

. ..------SC-L,20
LH28FO08

120

Max.

Unit

ns
ns

Rev. 1.0

SI-IARP

LHF08CH2 30

Vcc=5Vdl.5V,

Sym.
t*“n”
t*“n” Address to C

tpHn” RP# High to

k, nx OE#to Output in Low Z

NOTES:

1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.

2. OE# may be delayed up to tELQV-tGLQv

3. Sampled, not 100% tested.

4. See Ordering Information for device speeds (valid operational combinations).

5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed
Configuration) for testing characteristics.

6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.

Read Cycle
CE# to Outp
OE# to Outp

CE# to Outp
CE# High to VUhc/UL ,,,

Output Hold from Address,
Change, Whichever Occurs

after the falling edge of CE# without impact on tELQv.

5VkO.25V, T,=O”C to +70X

Vcc=5V+0.25Vj LH28FO08Sc-L=(5) 1

I

Rev. 1.11

SHARP

VIH

CE#(E)

VIL

VIH

OE#(G)

WL

VIH

WE#(W)

VIL

VOH

DATA(D/Q)

(DQo-DQ7)

VOL

Device

Address Selection

t

Address Stable

r

c

LHF08CH2

Data Valid

31

.I.,....,,

tOH,--+

,1,,,,,,,,

vcc

RP#(P)

VIH

VIL

Figure 15. AC Waveform for Read Operations

L

Rev. 1.0

SHARP

LHF08CH2

6.2.5 AC CHARACTERISTICS - WRITE OPERA
Vc.=2.7V-3.6V, TA=O”C to +7O”C

Versiond5)

Parameter

tA”A” Write Cycle Time

tPl-!Wl

RP# High Recovery to WE# Going Low

NOTE:
See 5.OV V,, WE#-Controlled Writes for notes 1 through 5.

Vcc=3.3V+0.3V, T‘,=O”C to +70X

Versiond5)

Svm. I

t

d\,A\l

1 Write Cvcle Time

tpuw, RP# High Recovery tc
fF, w,

tWl WH

CE# Setup to

WE#P- -- ~~

ulse Width

& 1 RP# VHH Setup

tvpWCl 1 Vpp Setup to WE
t*,,-,,,,,, [ Address Setup to WE
tnvw,, [ Data Setup to WE# G
twwnx 1 Data Hold fron

tWHAX

) Address Hold
tWHFH CE# Hold from V
bacHw, WE# Pulse Width
twHR, WE# High to RY/

Parameter 1 Notes 1

I WE# Going Low

WE# Going Low

to WE# Going High
!# Going High

# Going High
oing High

I

WE# High

From WE# Hiah

VE# High

I High

BY# Going Low
bur,, Write Recovery before Read
tn”v, Vpp Hold from Valid SRD, RY/BY# High
tn”pH

RP# V,,,, Hold from Valid SRD, RY/BY# High
IOTE:
;ee 5V V,, AC Characteristics - Write Operations for Notes 1 through 5.

ATION

-

Notes Min. 1 Max.

2 1

2 1

2 100
2
3 50
3 50

2,4
2,4

LH28F008SGL150

Unit

150

LH28F008SC-L120

Min. Max.

Unit

--..-

120

0

70

100 ns

5 ns
5

0 ns

25 ns

100
0 ns
0
0 ns

ns
IJS

ns
p3

ns

“C

I._
ns

ns
ns

nc

I *u

ns
ns

32

Rev. 1.2

LHFOSCH2

UOTES:
I. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as

during read-onry operations. Refer to AC Characteristics for read-only operations.

!. Sampled, not 100% tested.

3. Refer to Table 4 for valid A,, and D,, for block erase, byte write, or lock-bit configuration.

1. V,, should be held at VPPH1,2,3 (
byte write, or lock-bit configuration success (SR.1/3/4/5=0).

5. See Ordering Information for device speeds (valid operational combinations).

5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.

7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.

and

if necessary RP# should be held at V,,) until determination of block erase,

Rev. 1.2

SHARP

ADDRESSES(A)

CE#(E)

LHFOBCH2

1 2 3 4 5 6

rcs-----

VIH

OE#(G)

WE#(W)

DATA( D/Q)

RY/BY#(R)

RP#(P)

NOTES:

1. Vcc power-up and standby.

2. Write block erase or byte write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

VIH

VIL

VIH

VIL

VIH

VOH

tWHGL

Figure 16. AC Waveform for WE#-Controlled Write Operations

Rev. 1 .O

LHF08CH2

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES(‘)
Vc:,=2.7V-3.6V, T,=O”C to +7O”C

Versiond5)

Parameter 1 Notes

2

3 50
3 50

EE

See 5.OV V,, Alternative CE#-Controlled Writes for notes 1 through 5.

Vbc=3.3V+0.3V, T,=O”C to +70X

Versiond5)

Sym. . .a.-...---.
t*“n” Write Cycle Time
tp&p,
tw, F,
tp, FH CE# Pulse Width
t

RP# High Recovery to CE#

WE# Setup to CE# p-‘-- ’

RP# V,, Setup to Ccw

Parameater

: Going Low 2 1

uullly

LOW 0

3

LH28F008SGL150

Min. Max.

150

1

0

70

5
5
0

25

f-l

”

I

LH28F008SC-L120

I

Min.

.--

-7n

i---c--

35

Unit

ns
ns

Max.

t

Unit

p.S

ns
nc

I I.2

I

ns

tfq&, CE# Pulse Width High
tp)+q
ffzHr,, Write Recovery before Read

hNl

w?OVPH
NOTE:

See 5V Vc, Alternative CE#-Controlled Writes for Notes 1 through 5.

CE# High to RY/BY# Going Low
Vpp Hold from Valid SRD, RY/BY# High

RP# VHH Hold from Valid SRD, RY/BY# High

2,4
2,4

25

0
0
0

100

ns
ns
ns
ns
ns

Rev. 1.0

LHF08CH2

etuo to Cl

7” 7” II> II>

40 40

5 5 ns ns
5 5 ns ns
0 0

-! -!

9r; 9r;

NOTES:

1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and
inactive WE# times should be measured relative to the CE# waveform.

2. Sampled, not 100% tested.

3. Refer to Table 4 for valid A,, and DIN for block erase, byte write, or lock-bit config.uration.

4. V,, should be held at VPPHl12,s (
byte write, or lock-bit configuration success (SR.1/3/4/5=0).

5. See Ordering Information for device speeds (valid operational combinations).

6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.

7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.

and if necessary RP# should be held at V,,) until determination of block erase

ns ns

ns ns

-A -A

Rev. 1 .ll

ADDRESSES(A)

LHF08CH2

1 2 3 4 5

A----

VIH

VIL

37

A

WE#(W)

OE#(G)

CE#(E)

DATA( D/Q)

RY/BY#(R)

RP#(P)

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VHH

VIH

VIL -

J

NOTES:

1. Vcc power-up and standby.

2. Write block erase or byte write setup.

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. Write Read Array command.

Figure 17. AC Waveform for CE#-Controlled Write Operations

Rev. 1.0

SHARP

2.7 RESET OPERATIONS

LHF08CH2

RY/BY#(R)

FlP#(P)

RY/BY#(R)

RP#(P)

vcc

RP#(P)

VOH

VOL

VIH

VIL

(A)Reset During Read Array Mode

VOH

VOL

VIH

VIL

2.7Vi3.3Vi5V

ML

VIH

VIL

p tPLAH

(B)Reset During Block Erase, Byte Write, or Lock-Bit Configuretion

L

- b35VPH -

I

7-

(C)RP# rising Timing

Figure 18. AC Waveform for Reset Operation

Reset AC Specifications(‘)

V~+iV

Sym. Parameter

Vr.,=2.7V Vn,=3.3V

Notes Min. Max. Min.

Max. Min. Max. Unit

RP# Pulse Low Time

‘LPH

(If RP# is tied to Vcc, this 100 100

100 ns

specification is not applicable)

RP# Low to Reset during

‘LRH

Block Erase, Byte Write or

2,3

-

20

12

P

Lock-Bit Configuration

V,, 2.7V to RP# High

35VPH

V,, 3.OV to RP# High
Vco 4.5V to RP# High

4 100

100

100

ns

ITES:

These specifications are valid for all product versions (packages and speeds).

If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset
will complete within 1 OOns.

A reset time, tPHQV,

is required from the latter of RY/BY# or RP# going high until outputs are valid.

When the device power-up, holding RP# low minimum 1OOns is required after Vcc has been in predefined range

and also has been in stable there.

Rev. 1.0

LHF08CH2

6.2.8 BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE(3~4~5)

:wHQv4 Clear Block Lock-Bits Time 2 1.1 5

FHOVA

tWHRH, Byte Write Suspend Latency Time to
tF,,RH,

)“HnHz Erase Suspend Latency Time to Read 9.4 13.1

FHRH7

Read

5.6 7 5.2 7.5

1 4

9.8 12.6

NOTES:

1. Typical values measured at TA=+25”C and nominal voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Sampled but not 100% tested.

5. Block erase, byte write and lock-bit configuration operations with Vccc3.OV and/or VPP<3.0V are not
guaranteed.

S

P
IJS

Rev. 1.3

SHARP

ADDITIONAL INFORMATION

1 Ordering Information

LHF08CH2

Product line designator for all SHARP Flash products

I

I

I

~L~H12/81F~O~018/SICi(H~Rl- lLl815j

Device Density

008 = 8-Mbit

Architecture
S = Regular Block

Power Supply Type

C = SmartVoltage Technology

Operating Temperature

‘Blank = 0°C - +7O”C -

H = -40°C - +85”C

)ption Order Code

LH28FOO8SCFbL85 LH28F008SC-L150 LH28F008SC-L120 LH28F008SC-L90 LH28F008SC-L85

1

F

~

_

V,,=2.7-3.6V

5OpF load,

1.35V I/O Levels 1.5V I/O Levels

ul

Valid Operational Combinations

v,,=3.3*0.3v vc+.o*o.5v

5OpF load,

w

Access Speed (ns)
85:85ns(5V,30pF), 90ns(5V),

120ns(3.3V), 150ns(2.7V)

12:120ns(5V), 150ns(3.3V)

170ns(2.7V)

Pat kage

T = 40-Lead TSOP
R = 40-Lead TSOP(Reverse Bend)
N = 44-Lead PSOP

B = 42 or 48-Ball CSP

Vcc=5.0~0.25V

1 OOpF load,

TTL l/O Levels

3OpF load,

1.5V I/O Levels

Rev. 1.0

SHARP

________________________________________~~-~~~~---~~~---~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~~~.~~~~~~~~.~~~~~.~~~~~~~~~~~~~~~~~~~~~~~--~~~~~~~~~~~-~~~~~~~~~~~~~~

________________________________________~~.--~~..--~~~--~~~~~---~~~~.--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~-~~~~~~-~~~~~--~~~~-~~~~~~~~~~.~-~~~~~~~~.

,____________.______~~~~~..~~~~..~~~~~~.~~~~~~~~~~.~.~~~~~~.~~~~~~.~~~~~~~.~~~~~~~~~~.~.~~~~~~...~~~~...~~~~~.~.~~~~.~~~~~~.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.

LHF08CH2

8 Package and packing specification 1

­1

1. Package Outline Specification
Refer to drawing No.AA 1 1 12

2. Markings
2 - 1. Marking contents

( 1) Product name : LH28F008SCR-L85
( 2 ) Company name : SHARP
(3) Date code

(Example) Y Y WW

xxx Indicates the product was manufactured

(4) The marking of “JAPAN” indicates the country of origin.

2 - 2. Marking layout

Refer drawing No.AAl 1 1 2

(This layout does not define the dimensions of marking character

(Lower two digits of the year.)

and mark ing position.)

3. Pack ing Specification (Dry packing for surface mount packages)
Dry packing is used for the purpose of maintaining IC quality after mounting
packages on the PCB (Printed Circuit Board),
When the epoxy resin which is used for plastic packages is stored at high
humidity, it may absorb 0.15% or more of its weight in moisture. If the surface

mount type package for a relatively large chip absorbs a large amount of moisture

between the epoxy resin and insert material (e.g. chip,lead frame) this moisture

may suddenly vaporize into steam when the entire package is heated during the

soldering process (e.g. VPS). This causes expansion and results in separation
between the resin and insert material, and sometimes cracking of the package.

This dry packing is designed to prevent the above problem from occurring in

surface mount packages.

- 1. Packing Materials
Material Name Material Specificaiton Purpose
Tray

_____________.__________________________--~-----~~---~~~----~------~-~----~~-----~~~~-~-----~~~~---~~~~--..----~.----~------.---------------------- _ _ _ _ _ _ _ _

Upper cover tray Conductive plast ic (ltray/case) Fixing of device

________________________________________---------.---------------------------------------------------- ___--____-____-_________________________---- _ _ _ _ _ _ _. _.

Laminated aluminum bag Aluminum polyethylene (lbag/case) Drying of device

________________________________________-------------------------------------------------------------------------------------------------------------------.

Desiccant Silica gel Drying of device

._______________________________________~~~~~~~~~.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Conductive plastic (50devices/tray) Fixing of device

__._____________________________________---.---------.

P P band Polypropylene (3pcs/case) Fixing of tray

Inner case Card board (500devices/case) Packaging of device

Label Paper Indicates part number,quantit]

and date of manufacture
Outer case
Devices shall be placed into a tray in the same direction.)

(

Card board

Cuter packing of tray

SHARP

LHF08CH2

3 - 2. Outline dimension of tray

Refer to attached drawing

Storage and Opening of Dry Packing

4.

4-l. Store under conditions shown below before opening the dry packing

( 1) Temperature range : 5-40°C
(2) Humidity : 80% RH or less

4 - 2. Notes on opening the dry packing

(1) Before opening the dry packing, prepare a working table

grounded against ESD and use a grounding strap.

(2) The tray has been treated to be conductive or anti-stat i

device is transferred to another tray, use a equivalent

4-3. Storage after opening the dry packing

Perform the following to prevent absorption of moisture after

(1) After opening the dry packing, store the ICs in an environment with a

temperature of 5-25°C and a relative humidity of 60% or less and

mount ICs within 72 hours after opening dry packing.

42

which is

c. If the
tray.

opening.

4 -4. Baking (drying) before mounting

( 1) Baking is necessary

(A) If the humidity indicator in the desiccant becomes pink

(B) If the procedure in section 4-3 could not be performed

( 2) Recommended baking conditions

If the above conditions (A) and (B) are applicable, bake it before
mounting, The recommended conditions are 16-24 hours at 120°C.
Heat resistance tray is used for shipping tray.

5. Surface Mount Conditions
Please perform the following conditions when mounting ICs not to deteriorate IC
quality.

5-l .Soldering conditions(Tbe following conditions are valid only for one time soldering.)

Mounting Method

Reflow soldering Peak temperature of 230°C or less, IC package

(air) duration of less than 15 seconds. surface

_______.__________._____________________-------------------.-------------------------------------------------------. ___________________._____________

Manual soldering 260°C or less, duration of less IC outer lead

(soldering iron) than 10 seconds. surface

Temperature and Duration Measurement Point

200°C or over,duration of less than 40 seconds.

Temperature increase rate of l--4’Vsecond

5 - 2. Cond

(1)
(2)
(3)

itions for removal of residua

Ultrasonic washing power
Washing time

Solvent temperature

1

flux

: 25 Watts/liter or less
: Total 1 minute maximum
: 15-40°C

SHARP

LHF08CH2

L

H28F008SCR-

L8 X 5

JAPAN

YYWW xx

\r.

0

.

h)
ul

It

t-

SEE DETAIL A

20. 0+-o. 3

18. 4&O. 2

ASE PLANE

DETAIL A

;I% j

4ME $SOP40-P-lOZO(R LEAD FINISH j PLATING NOTE Plastic body dimensions do not include burr

MAWING NO. i AA1112

!J-FttJz [ TIN-LEAC Ikii* ‘1S~f~9);~b-'iM~~,t18~~ll~\bq)lff3.

#{Z j
UNIT ! mm

of resin.

SHARP

LHF08CH2

44

mq

qAME\TSOP40-1020TCM-RH

qqiL j

DRAWING NO. j CV644 UNIT 1 mm

tlw

NOTE

SHARF,

Flash memory LHFXXCXX family Data Protection

LHF708CH2 45

Noises having a level exceeding the limit specified in the spec
generated under specific operating conditions on some systems.
Such noises, when induced onto WESt signal or power supply, may be interpreted as false
commands, causing undesired memory updating.
To protect the data stored in the flash memory against unwanted overwriting, systems
operating with the flash memory should have the following write protect designs, as
appropriate:

1) Protecting data in specific block
When a lock bit is set, the corresponding block is protected against overwriting. By
using this feature,
section(locked section) and data section(unlocked section). The master lock bit can
be used to prevent false block bit setting.

By controlling RI%, desired blocks can be locked/unlocked through the software.
For further information on setting/resetting block bit and control

to the specification. (See chapter 4.9 and 4.10)

the flash memory space can be divided into the program

ificat on may be

ing of RP#, refer

2) Data protection through Vpp

When the level of Vpp is lower than VPPLK (lockout voltage), write operation on the

flashmemory is disabled. All blocks are lockedandthedata intheblocksarecompletely
write protected.
For the lockout voltage, refer to the specification. (See chapter 6.2.3. )

3) Data protect ion through RP#
When the RP$ is kept low during power up and power down sequence such as vo 1 tage

transition, write operation on the flash memory is disabled, write protecting all

blocks.

For the detai 1s of RPB control, refer to the specification. (See chapter 5.6 and6.2.7.)

Rev 1.3