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1
DESCRIPTION
The LH1691 is a 240-output TFT-LCD gate driver
IC.
FEATURES
• Number of LCD drive outputs : 240
• LCD drive output sequence :
Output shift direction can be selected
OG
1/OG240 or OG240/OG1
• Cascade connection :
Max. 2 cascades (internal counting system)
• Usable with both positive/negative power supplies
• Output mode selection
– Normal mode (1-pulse scanning)
– Continuous 2-pulse mode (2-pulse scanning)
– Jumping 2-pulse mode (2-pulse scanning)
• LCD drive voltage : +16.0 to +33.0 V
• Operating temperature : –30 to +85 ˚C
• Package : 258-pin TCP (Tape Carrier Package)
PIN CONNECTIONS
LH1691
LH1691
240-output TFT-LCD Gate Driver IC
OG238
OG239
OG240
238
239
240
OG
1
OG2
OG3
1
2
3
CHIP SURFACE
VDD
VEE
VSS
VCC
VLS
TEST1
TEST2
CKV
SPV
CE
R/L
MODE1
MODE2
V
LS
VCC
VSS
VEE
VDD
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
258-PIN TCP
TOP VIEW
NOTE :
Doesn't prescribe TCP outline.
2
LH1691
PIN DESCRIPTION
BLOCK DIAGRAM
PIN NO. SYMBOL I/O DESCRIPTION
1 to 240 OG
1-OG240 O LCD drive output pins
241, 258 V
DD – Power supply pins for LCD drive
242, 257 VEE – Power supply pins for LCD drive
243, 256 V
SS – Power supply pins for logic system
244, 255 VCC – Power supply pins for logic system
245, 254 V
LS – Power supply pins for input level shifter
249 CE I Cascade sequence setting pin
250 SPV I Vertical scanning start pulse input pin
251 CKV I Vertical shift clock input pin
252, 253 TEST
2, TEST1 I IC test pins
241
V
DD
246
247
MODE
2
MODE1
R/L
CE
SPV
CKV
TEST
2
TEST1
248
249
250
251
252
253
V
DD
258 245
V
LS VLS
254 244
V
CC VCC
255 242
V
EE VEE
257 243
V
SS VSS
256
OG
1
1
OG
240
240
OUTPUT CIRCUIT
LEVEL SHIFTER
BI-DIRECTIONAL SHIFT
REGISTER
CONTROL
LOGIC
1 240
1 240
1 240
Pin for selecting bi-directional shift register and setting cascade
sequence
IR/L248
Output mode selection pinsI
MODE2, MODE
1
246, 247
LH1691
3
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK FUNCTION
Control Logic
Used to create signals necessary for mode selecting signal, cascade sequence setting
signal and for operation of bi-directional shift register.
Bi-directional Shift
Register
Used as transfer circuit of LCD drive output start signal. It is possible to set LCD drive
output sequence of OG
1/OG240 direction or OG240/OG1 direction.
Level Shifter
Used as circuit which shifts LCD drive output signals transferred by bi-directional shift
register to V
DD-VEE level.
Output Circuit Configured with output buffers to output VDD-VEE level.
INPUT/OUTPUT CIRCUITS
I
V
LS
Level Shifter
(V
LS-0 V/VCC-VSS)
Internal Logic
(VCC-VSS)
V
SS
To Internal Circuit
Fig. 1 Input Circuit
¿Applicable pins¡
CKV, SPV, CE, R/L,
MODE
1, MODE2,
TEST
1, TEST2
O
V
DD
(VDD-VEE)
V
EE
From Internal Circuit
Fig. 2 Output Circuit
¿Applicable pins¡
OG
1-OG240
4
LH1691
FUNCTIONAL DESCRIPTION
Pin Functions
SYMBOL FUNCTION
V
DD Used as power supply pin for high level LCD drive.
V
LS Used as power supply pin for input level shifters.
VCC Used as power supply pin for logic system, normally connected to VSS + 5.0 V.
V
EE Used as power supply pin for low level LCD drive.
VSS Used as logic system power supply pin.
CKV Used as vertical shift clock pulse input pin.
SPV
Used as vertical scanning start pulse input pin. (At least, input one cycle of CKV during "L"
period of SPV.)
MODE
1
MODE2
Used as input pins for selecting output mode.
Output mode is set as shown in the table below by setting MODE1 pin and MODE2 pin.
R/L
Used as input pin for selecting the shift direction of bi-directional shift register and for
setting the sequence of cascade connection.
LCD drive outputs shift from OG
1 to OG240 when set to "H". LCD drive outputs shift from
OG
240 to OG1 when set to "L". At the same time, cascade sequence is set as shown in
the table below.
CE
Used as input pin for setting of chip cascade sequence. (Max. 2 cascades)
With above setting, sets the cascade sequence signal inside the IC.
TEST
1
TEST2
Used as input pins for IC testing.
Must be set to "H".
OG
1-OG240
Used as output pins for LCD drive output, and which output data at 2 levels.
• Selecting data is output at V
DD level .
• Non-selecting data is output at V
EE level .
MODE
1 MODE2 Output mode
H H Normal mode (1-pulse scanning)
L H Continuous 2-pulse mode
H L Jumping 2-pulse mode
L L Set all outputs to V
EE level.
CE
Cascade sequence
R/L = "H"
1st
2nd
R/L = "L"
2nd
1st
H
L
LH1691
5
Functional Operations
(1) Example of Cascade Sequence
TFT-LCD Panel
Scanning Direction When R/L = "L".
Scanning Direction When R/L = "H".
OG
1
CE = "H"
CE = "L"
OG
240
OG1
OG240
At this time, normal mode (scanning with 1 pulse) is set when MODE1 = "H" and MODE2 = "H",
jumping 2-pulse mode (scanning with 2 pulses) is set when MODE
1 = "H" and MODE2 = "L",
continuous 2-pulse mode (scanning with 2 pulses) is set when MODE
1 = "L" and MODE2 = "H", and
output V
EE level is set when MODE1 = "L" and MODE2 = "L".
*
LH1691
6
(2) Example of Input/Output Timing (For 1st Cascade Sequence)
CKV
SPV
OG
240OG1
OG239OG2
OG238OG3
OG240OG1
OG239OG2
OG238OG3
OG240OG1
OG239OG2
OG238OG3
R/L = "H" R/L = "L"
(1-pulse Mode)
(Jumping 2-pulse Mode)
(Continuous 2-pulse Mode)
7
LH1691
PRECAUTIONS
Precautions when connecting or disconnecting
the power supply
This IC has a high-voltage LCD driver, so it may be
permanently damaged by a high current which may
flow if voltage is supplied to the LCD drive power
supply while the logic system power supply is
floating. Therefore, when connecting the power
supply, observe the following sequence.
Logic system power supply (V
LS) or internal
logic system power supply (V
SS, VCC; VCC >
V
SS) / logic input / LCD drive power supply
(V
EE, VDD)
It is possible to set voltage V
EE to the same as
V
SS. When connecting the power supply when VEE
= VSS, observe the following sequence and the
recommended sequence figure shown below.
Logic system power supply (V
LS), internal logic
system power supply (V
SS, VCC; VCC > VSS)
and low-level LCD drive power supply (V
EE) /
logic input / high-level LCD drive power supply
(V
DD)
When disconnecting the power supply, follow the
reverse sequence.
Since the logic state of the internal circuit is
unstable immediately after the logic system power
is supplied, input CKV and SPV while initializing the
internal circuit (minimum input clock number is 240
CKV).
MODE
1 and MODE2 should be set to "L" during
the initializing period for setting the LCD drive
output to V
EE level.
VDD
VLS
VCC
VSS, VEE
0 V
Input
Input pin setting
Input pins other than CKV and SPV must be set to
"H" or "L" level.
Maximum ratings
When connecting or disconnecting the power, this
IC must be used within the range of the absolute
maximum ratings.
8
LH1691
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL APPLICABLE PINS RATING UNIT NOTE
Supply voltage
V
DD VDD –0.3 to +35.0 V
1, 2
V
LS VLS –0.3 to +7.0 V
VCC – VSS VCC, VSS –0.3 to +7.0 V
V
EE – VSS VEE, VSS –0.3 to +35.0 V
VDD – VEE
(VSS)
V
DD, VEE, VSS –0.3 to +35.0 V
Input voltage V
IN
CKV, SPV, CE, R/L, MODE1,
MODE2, TEST
1
, TEST
2
–0.3 to VLS + 0.3 V
Storage temperature T
STG –45 to +125 ˚C
NOTES :
1. TA = +25 ˚C
2. The maximum applicable voltage on any pin with respect to 0 V.
NOTES :
1. The applicable voltage on any pin with respect to 0 V.
2. Ensure that voltages are set as follows.
V
SS, VEE ≤ 0 V
V
CC – VSS = VLS±0.2 V (For 3.3 V specifications)
V
CC – VSS = VLS±0.3 V (For 5.0 V specifications)
V
CC ≤ VLS
PARAMETER SYMBOL MAX. UNIT NOTE
Supply voltage
V
DD +33.0 V
1, 2
Input voltage V
IN VLS V
Operating temperature T
OPR +85 ˚C
MIN. TYP.
+5.5 +9.0
0
–30
V
LS
VCC – VSS
VEE – VSS
VDD – VEE
(VSS)
+3.0
+3.0
0
+16.0
+5.0
+5.0
+25.0
+5.5 V
+5.5 V
+11.0 V
+33.0 V
LH1691
9
When power supply pins are set as shown below,
the LH1691 can output positive voltage and
negative voltage to LCD drive output.
Example 1 : For Positive Voltage Output
Input
V
LS, VCC
VDD
VSS, VEE (0 V)
Internal Logic
LCD Drive Output
Example 2 : For Negative Voltage Output
VDD, VLS
0 V
V
CC
V
SS, VEE
Input
LCD Drive Output
Internal Logic
10
LH1691
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VLS = +3.3±0.3 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
NOTES :
1. All input pins : 3.3 V
2. CKV : Frequency = 31 kHz, "L" period width t
WL = 16.2 µs
SPV : Frequency = 60 Hz
Other input pins : 3.3 V
All output pins are opened.
3. CKV : Frequency = 31 kHz, "L" period width t
WL = 16.2 µs
SPV : Frequency = 60 Hz
MODE
2 : 0 V
Other input pins : 3.3 V
All output pins are opened.
4. CKV : Frequency = 31 kHz, "L" period width t
WL = 16.2 µs
SPV : Frequency = 60 Hz
MODE
1 : 0 V
Other input pins : 3.3 V
All output pins are opened.
PARAMETER
SYMBOL
CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE
Input "Low" voltage V
IL CKV, SPV, MODE1,
MODE
2, CE, R/L
0.2V
LS V
Input "High" voltage V
IH 0.8VLS V
Output "Low" voltage VOL IOL = 0.4 mA
V
EE
+ 0.4
V
Output "High" voltage V
OH IOH = –0.4 mA
VDD – 0.4
V
Input "Low" current IIL VI = 0 V 5.0 µA
Input "High" current I
IH VI = VLS 5.0 µA 1
Supply current (1)
I
DD
For
1-pulse mode
50 µA
2
ILS 100 µA
I
CC 50 µA
IEE 40 µA
Supply current (2)
I
DD
For jumping
2-pulse mode
100 µA
3
I
LS 200 µA
ICC 60 µA
I
EE 40 µA
Supply current (3)
IDD
For continuous
2-pulse mode
100 µA
4
ILS 200 µA
I
CC 60 µA
IEE 40 µA
OG1-OG240
CKV, SPV, MODE1,
MODE
2, CE, R/L
LH1691
11
PARAMETER
SYMBOL
CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE
Input "Low" voltage V
IL CKV, SPV, MODE1,
MODE
2, CE, R/L
0.2V
LS V
Input "High" voltage V
IH 0.8VLS V
Output "Low" voltage VOL IOL = 0.4 mA
VEE + 0.4
V
Output "High" voltage V
OH IOH = –0.4 mA
VDD – 0.4
V
Input "Low" current IIL VI = 0 V 5.0 µA
Input "High" current I
IH VI = VLS 5.0 µA
Supply current (1)
IDD
For
1-pulse mode
50 µA
2
ILS 150 µA
I
CC 80 µA
IEE 40 µA
Supply current (2)
I
DD
For jumping
2-pulse mode
100 µA
3
ILS 300 µA
I
CC 100 µA
I
EE 40 µA
Supply current (3)
IDD
For continuous
2-pulse mode
100 µA
4
ILS 300 µA
ICC 100 µA
I
EE 40 µA
OG1-OG240
CKV, SPV, MODE1,
MODE
2, CE, R/L 1
NOTES :
1. All input pins : 5 V
2. CKV : Frequency = 31 kHz, "L" period width t
WL = 16.2 µs
SPV : Frequency = 60 Hz
Other input pins : 5 V
All output pins are opened.
3. CKV : Frequency = 31 kHz, "L" period width t
WL = 16.2 µs
SPV : Frequency = 60 Hz
MODE
2 : 0 V
Other input pins : 5 V
All output pins are opened.
4. CKV : Frequency = 31 kHz, "L" period width t
WL = 16.2 µs
SPV : Frequency = 60 Hz
MODE
1 : 0 V
Other input pins : 5 V
All output pins are opened.
(VLS = +5.0±0.5 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
(VLS = +5.0±0.5 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
AC Characteristics (VLS = +3.3±0.3 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
PARAMETER
SYMBOL
CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT
Clock frequency f
CKV
CKV
100 kHz
"L" clock pulse width t
WL 0.5 µs
Clock rise time tRCKV 100 ns
Clock fall time t
FCKV 100 ns
Data setup time tSU
CKV, SPV
100 ns
Data hold time t
H 300 ns
Pulse rise time t
RSPV 100 ns
Pulse fall time tFSPV 100 ns
Output transfer delay
time
t
D
CL = 500 pF OG1-OG240
3.0 µs
Output rise time t
R 1.0 µs
Output fall time t
F 1.0 µs
SPV
PARAMETER
SYMBOL
CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT
Clock frequency f
CKV
CKV
100 kHz
"L" clock pulse width t
WL 0.5 µs
Clock rise time tRCKV 100 ns
Clock fall time t
FCKV 100 ns
Data setup time tSU
CKV, SPV
100 ns
Data hold time t
H 300 ns
Pulse rise time t
RSPV 100 ns
Pulse fall time tFSPV 100 ns
Output transfer delay
time
t
D
CL = 500 pF OG1-OG240
2.0 µs
Output rise time t
R 1.0 µs
Output fall time t
F 1.0 µs
SPV
LH1691
12
LH1691
13
Timing Chart
tSU tH
tFSPV
tWL
tRSPV
tFCKV
90%90%
10%
90%
10%
10%
90%
10%
tRCKV
50% 50%
50% 50% 50%
90% 90%
50%
50% 50%
50%
10% 10%
50%
t
D tD
tD tD
tD tD
tR tF
50% 50%
CKV
SPV
OG
1-OG240
(1-pulse Mode)
OG
1-OG240
(Continuous 2-pulse Mode)
OG
1-OG240
(Jumping 2-pulse Mode)
PACKAGES FOR LCD DRIVERS
14
Tape width
ø Tape Specification ø Tape Material
70 mm
Tape type
Wide
Perforation pitch
4 pitches
Substrate UPILEX S75
Adhesive #7100
Cu foil [thickness]
SLP 18 µm
Solder resist Epoxy resin
COM4
VDD
VEE
VSS
VCC
VLS
MODE2
MODE1
R/L
CE
SPV
CKV
TEST2
VLS
VCC
VSS
VEE
VDD
COM3
COM2
COM1
COM1
COM4
DUMMY
DUMMY
OG240
OG239
OG238
OG3
OG2
OG1
COM2
COM1
COM1
COM3
COM4
COM4
2-Ø2.7 (Cu)
Ø2.0
(Good device hole)
2-Ø1.9 (PI)
2-Ø1.5 (Cu hole)
21.8 (SL)21.8 (SL)0.9 (SL) 0.9 (SL)
21.4 (SR)21.4 (SR)
1.981
±0.05
1.981
±0.05
4.75
±0.05
0.3
MAX.
Pattern side
0.75
MAX.
Backside
1.2
MAX.
Total
0.095
0.05
[0.15]
5.5
[5.0 (E.L.)]
[14.2 (E.L.)]
[9.2 (E.L.)]
[3.5
TYP.
(3.2
MIN.
)]5.7 (SR)
3.5 (SL)
2.5 (SL)
0.083 (SL)
8.5 (SL)
2.2 (SR)
2.0 (SL)
5.0
±0.7
7.7
±0.05
0.6
±0.02
0.6
±0.02
0.4
±0.02
0.4
±0.02
26.75
±0.7
45˚
Device center
Film center
Chip
center
Sprocket
center
(Resin area)
4.7
MAX.
P1.20 x (23 – 1) = 26.4
±0.05
W0.40
±0.02
28.0 (SL)
[34.0 (E.L.)]
36.0
±0.06
63.949
±0.12
19.1
MAX.
(Resin area)
(47.0)
[44.0 (E.L.)]
42.9
±0.08
(Mark)
P0.17 x (248 – 1) = 41.99
±0.08
W0.095
±0.02
LH1691F
UPILEX is a trademark of UBE INDUSTRIES, LTD..
PACKAGE (Unit : mm)
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