Datasheet LH168A Datasheet (Sharp)

Page 1
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1

DESCRIPTION

The LH168A is a 384-output TFT-LCD source driver IC which can simultaneously display 262 144 colors in 64 gray scales.
• Number of LCD drive outputs : 384
• Built-in 6-bit digital input DAC
• 2-port input for each circuit of data inputs R, G and B, and it is possible to sample and hold display data of two pixels at the same time
• Possible to display 262 144 colors in 64 gray scales with reference voltage input of 10 gray scales : This reference voltage input corresponds to ‹ correction and intermediate reference voltage input can be abbreviated
• Cascade connection
• Sampling sequence : Output shift direction can be selected XO
1, YO1, ZO1/XO128, YO128, ZO128 or
ZO
128, YO128, XO128/ZO1, YO1, XO1
• Shift clock frequency : 55 MHz (MAX.)
• Supply voltages –V
CC (for logic system) : +2.7 to +3.6 V
–V
LS (for LCD drive system) : +3.0 to +5.5 V
• Package : 444-pin TCP (Tape Carrier Package)

PIN CONNECTIONS

LH168A
LH168A
384-output TFT-LCD Source Driver IC
XO128 YO128 ZO128
382 383 384
XO
1
YO1 ZO1
1 2 3
CHIP SURFACE
GNDA VLS TESTB XA5
XA0 YA5
YA0 ZA5
ZA0 SPOI GNDL POL1 POL2 CK VCC V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 SPIO XB5
XB0 YB5
YB0 ZB5
ZB0 LS LBR VLS GNDA
444 443 442 441
436 435
430 429
424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406
401 400
395 394
389 388 387 386 385
444-PIN TCP
TOP VIEW
NOTE :
Doesn't prescribe TCP outline.
Page 2
2
LH168A

PIN DESCRIPTION

PIN NO. SYMBOL I/O DESCRIPTION
1 to 384 XO
1-ZO128 O LCD drive output pins
385, 444 GNDA Ground pins for analog circuit 386, 443 V
LS Power supply pins for analog circuit
387 LBR I Shift direction selection input pin 388 LS I Latch input pin
389 to 394 ZB
0-ZB5 I Data input pins
395 to 400 YB0-YB5 I Data input pins 401 to 406 XB
0-XB5 I Data input pins
407 SPIO I/O Start pulse input/cascade output pin
408 to 417 V
10-V1 I Reference voltage input pins
418 V
CC Power supply pin for digital circuit
419 CK I Shift clock input pin
420, 421 POL
2, POL1 I Input data polarity exchange input pins
422 GNDL Ground pin for digital circuit 423 SPOI I/O Start pulse input/cascade output pin
IC test pinITESTB442
Data input pinsIXA
0-XA5436 to 441
Data input pinsIYA
0-YA5430 to 435
Data input pinsIZA0-ZA5424 to 429
Page 3
LH168A
3

BLOCK DIAGRAM

POL1 421
CK 419
395
406
401
YA0 430
LS
POL
2
441
XA0 XB0
XB5 YB0
YB5 ZB0
ZB5
436
SPIO 407
LBR 387
V4 414
V3 415
V
2 416
V
1 417
V7 411
V6 412
V
5 413
V10 408
1
V
9 409
V
8 410
389
400
ZA0 424
YA5 435
394ZA5 429
388
420
382
386
423
422418
444385
SPOI
442 TESTB
V
LS
443 VLS
XO12YO13ZO1 XO128
383
YO128
384
ZO128
6 x 2
6 x 2
6 x 2
6 x 2
6 x 2
6 x 2
64
6 x 2
6 x 2
6 x 2
6 x 2
6421
6 x 2
6 x 2
V
CC GNDL GNDA GNDA
SHIFT REGISTER
SAMPLING MEMORY
HOLD MEMORY
DATA
LATCH
REFERENCE
VOLTAGE
GENERATION
CIRCUIT
LEVEL SHIFTER
DA CONVERTER
OUTPUT CIRCUIT
XA5
Page 4

FUNCTIONAL OPERATIONS OF EACH BLOCK

BLOCK FUNCTION
Shift Register
Used as a bi-directional shift register which performs the shifting operation by CK and
selects bits for data sampling. Data Latch Used to temporary latch the input data which is sent to the sampling memory. Sampling Memory Used to sample the data to be entered by time sharing. Hold Memory Used for temporary latch processing of data in the sampling memory by LS input.
Level Shifter
Used to shift the data in the hold memory to the power supply level of the analog circuit
unit and sends the shifted data to DA converter. Reference Voltage Generation Circuit
Used to generate a gamma-corrected 64-level voltage by the resistor dividing circuit.
DA Converter
Used to generate an analog signal according to the display data and sends the signal to
the output circuit.
Output Circuit
Used as a voltage follower, configured with an operational amplifier and an output buffer,
which outputs analog signals of 64 gray scales to LCD drive output pin.

INPUT/OUTPUT CIRCUITS

I
V
CC
GNDL
To Internal Circuit
Fig. 1 Input Circuit (1)
¿Applicable pins¡ CK, LS, LBR, XA
0-XA5, XB0-XB5,
YA
0-YA5, YB0-YB5,
ZA
0-ZA5, ZB0-ZB5
I
V
CC
GNDL GNDL
To Internal Circuit
Fig. 2 Input Circuit (2)
¿Applicable pins¡ POL
1, POL2
LH168A
4
Page 5
LH168A
5
I
V
CC VCC
GNDL
To Internal Circuit
Fig. 3 Input Circuit (3)
¿Applicable pin¡ TESTB
O
V
LS
GNDA
From Internal Circuit
Operational Amplifier
+ –
Fig. 5 Output Circuit
¿Applicable pins¡ XO
1-XO128,
YO
1-YO128,
ZO
1-ZO128
VCC
GNDL
Nch Tr
Output Signal
Output Control Signal
VCC
GNDL
To Internal Circuit
I
O
Pch Tr
Fig. 4 Input/Output Circuit
¿Applicable pins¡ SPIO, SPOI
Page 6
LH168A
6

FUNCTIONAL DESCRIPTION

Pin Functions
SYMBOL FUNCTIONS
V
CC Used as power supply pin for digital circuit, connected to +2.7 to +3.6 V.
V
LS Used as power supply pin for analog circuit, connected to +3.0 to +5.5 V.
GNDL Used as ground pin for logic circuit, connected to 0 V. GNDA Used as ground pin for LCD drive circuit, connected to 0 V.
SPIO
SPOI
Used as input pins of start pulse and also used as output pins for cascade connection.
When "H" is input into start pulse input pin, data sampling is started. On completion of
sampling, "H" pulse is output to output pin for cascade connection. Pin functions are
selected by LBR. For selecting, refer to "Functional Operations".
LBR
Used as input pin for selecting the shift register direction. For selecting, refer to
"Functional Operations".
LS
Used as input pin for parallel transfer from sampling memory to hold memory. Data is
transferred at the rising edge and output from LCD drive output pin.
CK
Used as shift clock input pin. Data is latched into sampling memory from data input pin at
the rising edge.
V
1-V10
Used as reference voltage input pins. Hold the reference voltage fixed during the period of
LCD drive output. For relation between input data and output voltage values, refer to
"Output Voltage Value". For internal gamma correction, refer to "Gamma Correction
Value".
XA
0-XA5, YA0-YA5
ZA0-ZA5, XB0-XB5 YB0-YB5, ZB0-ZB5
Used as data input pins of R, G, and B colors. 6-bit x 2-pixel data are input from data pins
at the rising edge of CK. For relation between input data and output voltage values, refer
to "Functional Operations" and "Output Voltage Value". Select the data to be entered
into X, Y, and Z according to picture element arrays of the panel.
XO
1-XO128,
YO
1-YO128,
ZO
1-ZO128
Used as LCD drive output pins which output the voltage corresponding to the input of data
input pins (XA
0 to XA5, XB0 to XB5, YA0 to YA5, YB0 to YB5, ZA0 to ZA5, ZB0 to ZB5).
Data of XO1 to XO128 correspond to XA0 to XA5 and XB0 to XB5. Data of YO1 to YO128
correspond to YA0 to YA5 and YB0 to YB5, and data of ZO1 to ZO128 correspond to ZA0 to
ZA5 and ZB0 to ZB5. For relation between input data and output voltage values, refer to
"Functional Operations" and "Output Voltage Value".
POL
1
POL2
Used as input pins for input data polarity exchange. When "L" is entered, display data
becomes normal mode. When "H" is entered, input data becomes polarity exchange mode
(POL
1 = A system, POL2 = B system). For relation between input data and output voltage
values, refer to "Output Voltage Value". Must be connected to 0 V or opened.
TESTB Used as pin for IC testing. Must be connected to V
CC or opened.
Page 7
7
LH168A
Functional Operations
The following describes the relation between data input pin and output direction.
The following describes the relation between LBR pin, SPOI pin, SPIO pin and output direction.
Data input pin
XA0-XA5 YA0-YA5 ZA0-ZA5 XB0-XB5 YB0-YB5 ZB0-ZB5 πππ XB0-XB5 YB0-YB5 ZB0-ZB5
Output
direction
XO
1 YO1 ZO1 XO2 YO2 ZO2 πππ XO128 YO128 ZO128
PIN
OUTPUT DIRECTION
LBR H L SPOI Input Output SPIO Output Input
NOTE :
Color data corresponding to X, Y, and Z vary depending on the output direction.
LEFT SHIFT (ZO128, YO128, XO128/ZO1, YO1, XO1)RIGHT SHIFT (XO1, YO1, ZO1/XO128, YO128, ZO128)
Page 8
LH168A
8
Output Voltage Value
Two voltages are selected from all of the reference voltages (V
1-V10) by the upper 3-bit data (D5, D4
and D3) of the 6-bit input data (D5, D4, D3, D2, D1 and D0) taken by time sharing, and intermediate
value is determined by the lower 3-bit data (D
2, D1
and D0). Relation between input data and output voltage values is shown below.
INPUT
DATA
OUTPUT VOLTAGE INPUT
DATA
OUTPUT VOLTAGE
POL
1, POL2 = "L" POL1, POL2 = "H" POL1, POL2 = "L" POL1, POL2 = "H"
0V
1 V10 20 V6 + (V5 – V6) x 7/8 V5
1V2+ (V1 – V2) x 6/7 V9 21 V6 + (V5 – V6) x 6/8 V5 + (V4 – V5) x 1/8 2V
2+ (V1 – V2) x 5/7 V9 + (V8 – V9) x 1/7 22 V6 + (V5 – V6) x 5/8 V5 + (V4 – V5) x 2/8
3V2+ (V1 – V2) x 4/7 V9 + (V8 – V9) x 2/7 23 V6 + (V5 – V6) x 4/8 V5 + (V4 – V5) x 3/8 4V
2+ (V1 – V2) x 3/7 V9 + (V8 – V9) x 3/7 24 V6 + (V5 – V6) x 3/8 V5 + (V4 – V5) x 4/8
5V2+ (V1 – V2) x 2/7 V9 + (V8 – V9) x 4/7 25 V6 + (V5 – V6) x 2/8 V5 + (V4 – V5) x 5/8 6V
2+ (V1 – V2) x 1/7 V9 + (V8 – V9) x 5/7 26 V6 + (V5 – V6) x 1/8 V5 + (V4 – V5) x 6/8
7V
2 V9+ (V8 – V9) x 6/7 27 V6 V5 + (V4 – V5) x 7/8
8V3+ (V2 – V3) x 7/8 V8 28 V7 + (V6 – V7) x 7/8 V4 9V3+ (V2 – V3) x 6/8 V8 + (V7 – V8) x 1/8 29 V7 + (V6 – V7) x 6/8 V4 + (V3 – V4) x 1/8 AV3+ (V2 – V3) x 5/8 V8 + (V7 – V8) x 2/8 2A V7 + (V6 – V7) x 5/8 V4 + (V3 – V4) x 2/8 BV
3+ (V2 – V3) x 4/8 V8 + (V7 – V8) x 3/8 2B V7 + (V6 – V7) x 4/8 V4 + (V3 – V4) x 3/8
CV
3+ (V2 – V3) x 3/8 V8 + (V7 – V8) x 4/8 2C V7 + (V6 – V7) x 3/8 V4 + (V3 – V4) x 4/8
DV3+ (V2 – V3) x 2/8 V8 + (V7 – V8) x 5/8 2D V7 + (V6 – V7) x 2/8 V4 + (V3 – V4) x 5/8 EV
3+ (V2 – V3) x 1/8 V8 + (V7 – V8) x 6/8 2E V7 + (V6 – V7) x 1/8 V4 + (V3 – V4) x 6/8
FV3 V8+ (V7 – V8) x 7/8 2F V7 V4 + (V3 – V4) x 7/8
10 V
4 + (V3 – V4) x 7/8 V7 30 V8 + (V7 – V8) x 7/8 V3
11 V4 + (V3 – V4) x 6/8 V7 + (V6 – V7) x 1/8 31 V8 + (V7 – V8) x 6/8 V3 + (V2 – V3) x 1/8 12 V4 + (V3 – V4) x 5/8 V7 + (V6 – V7) x 2/8 32 V8 + (V7 – V8) x 5/8 V3 + (V2 – V3) x 2/8 13 V
4 + (V3 – V4) x 4/8 V7 + (V6 – V7) x 3/8 33 V8 + (V7 – V8) x 4/8 V3 + (V2 – V3) x 3/8
14 V4 + (V3 – V4) x 3/8 V7 + (V6 – V7) x 4/8 34 V8 + (V7 – V8) x 3/8 V3 + (V2 – V3) x 4/8 15 V
4 + (V3 – V4) x 2/8 V7 + (V6 – V7) x 5/8 35 V8 + (V7 – V8) x 2/8 V3 + (V2 – V3) x 5/8
16 V4 + (V3 – V4) x 1/8 V7 + (V6 – V7) x 6/8 36 V8 + (V7 – V8) x 1/8 V3 + (V2 – V3) x 6/8 17 V
4 V7 + (V6 – V7) x 7/8 37 V8 V3 + (V2 – V3) x 7/8
18 V
5 + (V4 – V5) x 7/8 V6 38 V9 + (V8 – V9) x 6/7 V2
19 V5 + (V4 – V5) x 6/8 V6 + (V5 – V6) x 1/8 39 V9 + (V8 – V9) x 5/7 V2 + (V1 – V2) x 1/7
1A V
5 + (V4 – V5) x 5/8 V6 + (V5 – V6) x 2/8 3A V9 + (V8 – V9) x 4/7 V2 + (V1 – V2) x 2/7
1B V5 + (V4 – V5) x 4/8 V6 + (V5 – V6) x 3/8 3B V9 + (V8 – V9) x 3/7 V2 + (V1 – V2) x 3/7 1C V
5 + (V4 – V5) x 3/8 V6 + (V5 – V6) x 4/8 3C V9 + (V8 – V9) x 2/7 V2 + (V1 – V2) x 4/7
1D V
5 + (V4 – V5) x 2/8 V6 + (V5 – V6) x 5/8 3D V9 + (V8 – V9) x 1/7 V2 + (V1 – V2) x 5/7
1E V5 + (V4 – V5) x 1/8 V6 + (V5 – V6) x 6/8 3E V9 V2 + (V1 – V2) x 6/7
1F V
5 V6 + (V5 – V6) x 7/8 3F V10 V1
Page 9
9
LH168A
‹ (gamma) Correction Value
Between reference voltage input pins, 7 or 8 resistors of the same resistance value are connected in series. When the resistance ratio between respective
reference voltage input pins matches the reference voltages (V
2 to V9) for ‹ correction of LCD panel,
the external power supply of the intermediate voltages (for V
2 to V9 pins) is not required.
V1
V2
R1
V3
R2
V4
R3
V5
R4
V6
R5
V7
R6
V8
R7
V9
R8
V10
R9
7 equal parts
8 equal parts
8 equal parts
8 equal parts
8 equal parts
8 equal parts
8 equal parts
7 equal parts
LH168A
External Reference Voltage
R9 7.85
R
8 1.98
R7 1.32
R
6 0.99
R
5 0.91
R4 1.24
R
3 1.08
R2 2.15
R
1 2.48
The following shows the ratio of ‹ correction resistance.
Page 10
10
LH168A

PRECAUTIONS

Precautions when connecting or disconnecting the power supply
This IC has some power supply pins, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence.
V
CC / logic input / VLS, V1-V10
When disconnecting the power supply, follow the reverse sequence.
Reference voltage input
The relation of the reference voltage input is shown here.
GNDA < V
1 ≤ V2 ≤ π ≤ V9 ≤ V10 < VLS or
V
LS > V1 ≥ V2 ≥ π ≥ V9 ≥ V10 > GNDA
Maximum ratings
When connecting or disconnecting the power supply, this IC must be used within the range of the absolute maximum ratings.
Target output load
This IC is designed for a 70 pF output load capacity. When using this IC for other than 70 pF panels, confirm the device is having no problem before using it.

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL APPLICABLE PINS RATING UNIT NOTE
Supply voltage
V
CC VCC –0.3 to +7.0 V
1, 2
V
LS VLS –0.3 to +7.0 V
Input voltage
V
I V1-V10 –0.3 to VLS + 0.3 V
Storage temperature T
STG –45 to +125 ˚C
V
I
SPIO, SPOI, CK, LS, LBR, POL
1
, POL2, TESTB, XA0-XA5,
XB
0
-XB5, YA0-YA5, YB0-YB5,
ZA
0
-ZA5, ZB0-ZB
5
–0.3 to VCC + 0.3 V
V–0.3 to V
LS + 0.3
XO1-ZO
128
VO
V–0.3 to VCC + 0.3SPIO, SPOIVO
Output voltage

RECOMMENDED OPERATING CONDITIONS

NOTES :
1. TA = +25 ˚C
2. The maximum applicable voltage on any pin with respect to GNDL and GNDA (0 V).
NOTE :
1. The applicable voltage on any pin with respect to GNDL and GNDA (0 V).
PARAMETER SYMBOL MAX. UNIT NOTE
Supply voltage
V
CC
1
Reference voltage input V
1-V10 VLS V
Clock frequency f
CK 55 MHz
MIN. TYP.
+2.7
0
V
LS
+3.6 V
+3.0 +5.5 V
–20 ˚C+75T
OPROperating temperature
pF70C
L
LCD drive output load capacity
Page 11
LH168A
11

ELECTRICAL CHARACTERISTICS

DC Characteristics
(VCC = +2.7 to +3.6 V, VLS = +3.0 to +5.5 V, TOPR = –20 to +75 ˚C)
PARAMETER
SYMBOL
CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE
Input "Low" voltage V
IL
XA0-XA5, YA0-YA5, ZA0-ZA5, XB
0
-XB5, YB0-YB5, ZB0-ZB5,
SPIO, SPOI, CK, LS, LBR
GNDL 0.3VCC V
V
IH 0.7VCC VCC V
Input "High" current
I
ILH1
XA0-XA5, YA0-YA5, ZA0-ZA5, XB
0
-XB5, YB0-YB5, ZB0-ZB5,
SPIO, SPOI, CK, LS, LBR
A
Supply current (In operation mode)
I
CC1
fCK = 55 MHz
f
LS = 50 kHz
(Data sampling state)
VCC-GNDL 12 mA
Supply current (In standby mode)
I
CC2
fCK = 55 MHz
f
LS = 50 kHz
SPI = GND is fixed.
(Standby state)
V
CC-GNDL 4 mA
Supply current (In operation mode)
I
LS1
fCK = 55 MHz
f
LS = 50 kHz
(Data sampling state)
VLS-GNDA
Output voltage range V
OUT
XO1-ZO128
GNDA + 0.1
VLS – 0.1
V
1Deviations between
output voltage pins
V
OD –20 20 mV
Output current I
O1, IO2 20 50 µA 2
Resistance between reference voltage input pins
RGMA V1-V10 10 30 k$
µA1
XA0-XA5, YA0-YA5, ZA0-ZA5, XB
0
-XB5, YB0-YB5, ZB0-ZB5, SPIO, SPOI, CK, LS, LBR, POL
1
, POL
2
IILLInput "Low" current
VV
CC
VCC – 0.4
IOH = –0.3 mAVOH
V
GNDL + 0.4
GNDL
SPIO, SPOI
IOL = 0.3 mAVOLOutput "Low" voltage
Input "High" voltage
Output "High" voltage
10 mA
mA9V
LS-GNDA
f
CK = 55 MHz
f
LS = 50 kHz
SPI = GND is fixed.
(Standby state)
I
LS2
Supply current (In standby mode)
I
ILH2 POL1, POL2 400 µA
NOTES :
1. Criterion of evaluating voltage deviations. (a) Between output voltage pins Measuring values : Output voltage value at the time after
10 µs at the rising edge of LS.
(Average of several times) (Conditions) Output load capacity is 70 pF. In a state when the reference voltage is fixed.
Expecting values : Calculated following these specifications.
(Conditions) In a state when the reference voltage is fixed.
(b) Between LCD drivers Measuring values : Applicable to (a).
(Conditions) Applicable to (a).
Expecting values : Applicable to (a).
(Conditions) Applicable to (a). Each input voltage between the LCD drivers must be made perfectly equal by connecting corresponding reference voltage input pins.
2. I
O1 : Applied voltage = 3.0 V for output pins XO1 to ZO128.
Output voltage = 2.5 V for output pins XO
1 to ZO128.
V
LS = 5.0 V
I
O2 : Applied voltage = 2.0 V for output pins XO1 to ZO128.
Output voltage = 2.5 V for output pins XO
1 to ZO128.
V
LS = 5.0 V
Page 12
LH168A
12
AC Characteristics (VCC = +2.7 to +3.6 V, VLS = +3.0 to +5.5 V, TOPR = –20 to +75 ˚C)
PARAMETER
SYMBOL
CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT
Clock frequency f
CK
CK
55 MHz
"H" level pulse width tCWH 4ns
Input rise time t
CR 4ns
Input fall time tCF 4ns Data setup time t
SUD
XA0-XA5, YA0-YA5, ZA0-ZA5, XB0-XB5, YB0-YB5, ZB0-ZB5, POL
1, POL2
4ns
Data hold time t
HD 0ns
Start pulse setup time t
SUSP 4ns
Start pulse hold time tHSP 0ns
Start pulse output delay time
t
DSP CL = 10 pF 12 ns
LCD drive output delay time 1
t
DO1 s
LCD drive output delay time 2
t
DO2 10 µs
SPIO, SPOI
ns4tCWL"L" level pulse width
ns
1
-------­f
CK
tWSPStart pulse width
ns9t
HLS
LS signal-CK signal hold time
ns
1
-------­f
CK
tLSSP
LS signal-SPI signal set up time
C
L = 70 pF
C
L = 70 pF
XO1-ZO128
LS
LS signal "H" level width
t
WLS
1
-------­f
CK
ns
Page 13
LH168A
13
Timing Chart
CK
SPIO Input (SPOI)
SPIO Output (SPOI)
tHSP
tSUD tHD
tWSP
tDSP
tHLS tWLS
tLSSP
tDO1
Target voltage ±(VLS x 0.1)
Target voltage (6-bit accuracy)
tDO2
tSUSP tHSP
LAST – 1 LAST
tCR
tCWH tCWL
12
12
tCFtSUSP
1
f
CK
XA0-XA5 XB
0-XB5
YA0-YA5 YB
0-YB5
ZA0-ZA5 ZB
0-ZB5
POL1 POL2
CK
LS
SPIO Input (SPOI)
XO
1-ZO128
Page 14
PACKAGES FOR LCD DRIVERS
14
Tape width
ø Tape Specification ø Tape Material
48 mm
Tape type
Super wide
Perforation pitch
5 pitches
Substrate UPILEX S75
Adhesive #7100
Cu foil [thickness]
USLP 18 µm
Solder resist Epoxy resin/Polyimide
NC
Pattern side
Backside
Total
XO128
YO128
ZO128
COM4
COM4
COM4
COM3 COM3 COM3
NC
NC
NC
NC
COM1 COM1
COM1
NC
NC
NC
NC
XO1
YO1
ZO1
COM2
COM2 COM2
GNDA
GNDL
GNDA
VLS
LBR
LS ZB0 ZB1 ZB2 ZB3 ZB4 ZB5 YB0 YB1 YB2 YB3 YB4 YB5 XB0 XB1 XB2 XB3 XB4 XB5
SPIO
V10
V9
V8
V7
V6
V5
V2
V1
VCC
CK POL2 POL1
SPOI
ZA0 ZA1 ZA2 ZA3 ZA4 ZA5 YA0 YA1 YA2 YA3 YA4 YA5 XA0
XA2
XA1 XA3
XA4 XA5 VLS
COM2 COM1
COM4 COM3
NC
NC
Flexible slit
Flexible slit
2-Ø1.0 (PI)
[2.8
TYP.
(2.5
MIN.
)]
2.8 (SL)
3.4 (SL)
2.1 (SL)
6.9 (SR)
7.2 (SL)
[10.0]
10.875 (SL)
0.8 (SL)
1.5 (SL)
0.8 (SL)
1.5 (SL)
4.8 (SR)
8.3 (SR)
0.6 (SL)
0.20
±0.03
5.0 (SL) 5.0 (SL)
5.6 (SL)9.5 (SL) 9.5 (SL)5.6 (SL)
13.6 (SR)
1.0 (SL) 14.0 (SL) 1.0 (SL)14.0 (SL)
13.6 (SR)
13.7 (SR)
1.42
±0.05
4.75
±0.05
1.42
±0.05
1.1
MAX.
0.2
MAX.
0.75
MAX.
0.40
±0.02
0.40
±0.02
0.60
±0.02
0.60
±0.02
[0.60]
2-R0.8 (SR)
0.20
±0.03
0.35
±0.03
0.20
[0.80]
[0.80]
4.5
MAX.
(Resin area)
2.1
MAX.
(Resin area)
2.4
MAX.
(Resin area)
0.35
±0.03
0.20
0.20
±0.03
1.4 (Backside PI coating)
1.4 (Backside PI coating)
17.0
±0.7
5.35
±0.05
(Hole)
3.1
1.8
5.0
±0.7
6.6
±0.05
(Mark)
[9.2 (E.L.)]
[7.6 (E.L.)]
13.7 (SR)
Device center
Film center
Chip center
Sprocket center
GNDA
COM4 COM3
NC
[31.0]
27.1 (SL)
27.0 (SL)
48.175
±0.2
44.86 [28.6 (E.L.)]
27.6 (Backside PI coating)
[P0.090 x (296 – 1) = 26.55 W0.045]
V4 V3
10.0 (SL)
P0.40 x (64 – 1) = 25.2
±0.04
W0.020
±0.03
25.6
±0.05
(Holes)
20.4
MAX.
(Resin area)
[28.6 (E.L.)]
27.6 (Backside PI coating)
27.2
±0.04
(Mark)
27.0 (SL)
[P0.065 x (410 – 1) = 26.585
±0.04
W0.032]
P0.065 x (404 – 1) = 26.195
±0.04
W0.032
[31.0]
Ø2.0 (Good device hole)
GNDA
COM2
COM1
NC
4.3 (SL)
[16.8 (E.L.)]
LH168AF
UPILEX is a trademark of UBE INDUSTRIES, LTD..

PACKAGE (Unit : mm)

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