Page 1
Ultra Fast FET-Input
Operational Amplifier
LH0032 / LH0032C
FEATURES
500V/µs Slew Rate
••
70MHz Bandwidt h
••
1012Ω Input Impedanc e
••
As Low as 2mV Max Input Offset Voltage
••
FET Inpu t
••
Offset Null with Single Pot
••
No Compensa tion fo r Gains Above 50
••
Peak Out put Current to 100mA
••
CORPORATION
GENERAL DESCRIPTION
The LH0032 is a FET input, high sl ew rate amplifier capable
of driving up to 100m A current.
With wide bandwidth, high slew rate, high input impedance
and high current drive capability, LH0032 is an ideal choice for
many applications that includes high speed integrator, video
amplifier, summing amplifier, high speed D/A co nverters, etc.
ORDERING INFORMAT ION
Part Package Temperature Range
o
LH0032G H12A (TO8 -1 2 Lead ) -55
LH0032CG H12A (TO8-12 Lead) -25
C to +125oC
o
C to +85oC
CONNECTION DIAGRAMS
BALANCE/
COMPENSATION
INV
INPUT
NON-INV
INPUT
OUTPUT
COMPENSATION
4
5
6
NC
-
+
789
NC
Top View
H12A
NC
NC
V
V
+
OUT
-
123
12
11
10
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 2
CORPORATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Input Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
IN
Different ial Inp ut V o ltag e. . . . . . . . . . . . . . . . . . ±30V or± 2V
Power Dissipation, P
D
TA = 25oC. . . . . . . . . . . . . 1.5W, derate 100oC/W to 125oC
T
= 25oC. . . . . . . . . . . . . 2.2W, derate 70oC/W to 125oC
C
LH0032 / LH0032C
Operating Temper atur e R a nge, T
LH0032G . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
S
LH0032CG. . . . . . . . . . . . . . . . . . . . . . . . . -25
S
Operating J unct ion Temper atur e, T
Storage Temperat ure R ange. . . . . . . . . . . . -65
Lead Temp. (Soldering, 10 seconds). . . . . . . . . . . . . . 300
A
. . . . . . . . . . . . . . 175oC
J
o
C to +85oC
o
C to +150oC
o
C
DC ELECTRICAL CHARACTERISTICS V
SYMBOL PARAMETER
= ±15V , T
S
MIN
≤ TA ≤ T
LH0032 LH0032C
unless otherwise noted (Note 1) (TA = Tj)
MAX
MIN TYP MAX MIN TYP MAX
V
OS
Input Offset Voltage
25
10
215
20
∆VOS/∆T Average Offset Voltage Drift 15 50 15 50 µV/
I
OS
I
B
V
INCM
CMRR
Input Offset Current
250
25
100
25
Input Bias Current
1
50
Input Vo ltage Range ±10 ±12 ±10 ±12 V Note 6
Common Mode Rejection
Ratio
50 60 50 60 dB ∆V
50
500
5
500
5
15
60 70 60 70 dB V
A
VOL
Open-Loop Voltage Gain
57 57
V
O
Output Voltage Swing ±10 ±13.5 ±10 ±13 V RL = 1kΩ
UNITS TEST CONDITIONS
mV
o
C (Note 4)
V
pA
= 0
IN
pA
= TJ = 25oC (Note 3)
T
A
= 25oC (Note 2)
T
J
T
= 25oC (Note 3)
A
nA
pA
nA
= 25oC (Note 2)
T
J
T
= 25oC (Note 3)
A
nA
= ±10V
IN
= ±10V,
O
= 25oC
T
J
f = 1kHz
R
= 1kΩ
L
(Note 7)
T
= 25oC,
I
S
PSRR
Power Supply Current 18 20 20 22 mA
Power Supply Rejection
Ratio
50 60 50 60 dB
A
I
= 0 (Note 3)
O
∆V
= 10V
S
(±5 to ±15V)
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 3
LH0032 / LH0032C
CORPORATION
AC ELECTRICAL CHARACTERISTICS V
= ±15V, RL = 1kΩ, TJ = 25oC (Note 5)
S
SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS
S
R
t
s
t
s
t
R
t
D
Note 1. LH00 32 G/CG are 100% productio n teste d as specifie d at 25
Slew Rate 350 500 V/µsAV = +1
Settling Time to 1% of Final Value 100
AV = -1
Settling Time to 0.1% of Final Value 300 ns
Small Signal Rise Time 8 20
= +1, ∆VIN = 1V
A
V
Small Signal Dela y Time 10 25
o
C, Specifications at temperature extremes are verified by testing, periodic
characterizatio n, or correlation.
o
Note 2. Specification is at 25
temperature will exceed the value at T
ambient, and more under load conditions. Accordingly, V
warm-up. Refer to I
and IOS vs. temperature graph for expected value s.
B
C junction temperature due to requirements of high-speed automatic testing. Actual values at operating
= 25oC. When supply voltages are ±15V, no-loa d op era ting junction temp erature may rise 40-60oC above
J
may change one to several mV, and IB and IOS will change significantly during
OS
Note 3. Measured in still air 7 minutes after application of power. Guaranteed thru correlated automatic pulse testing.
Note 4. ∆V
/∆T is the average value calculated from measurements at 25oC and T
OS
, specifications at temperature are verified by testing,
MAX
periodic characterization, or correlation.
Note 5. Not 100% production tested; verified by testing, periodic characterization, or correlation.
Note 6. Guaranteed by CMRR test condition.
Note 7. Guaranteed thru correlated pulse testing at T
= 25oC.
j
AUXILIARY CIRCUIT S
∆V
= 20V
IN
INPUTS
6
5
+
LH0032
-
Offset Null
10k
12
4
10
-
V
Output Short Circ uit Prot ect ion
+
V
3
11
OUTPUT
6
5
+
V
+
LH0032
-
12
LM113
2
11
62Ω
10
-
V
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 4
CORPORATION
TYPICAL PERFORMANCE CHARACTERI STI CS
LH0032 / LH0032C
MAXIMUM POWER
DISSIPATION
INFINITE HEAT SINK
NO HEAT SINK
θ = 100˚C/W
JA
7525 50
TEMPERATURE (˚C)
θ
= 70˚C/W
JC
100 125 150
POWER DISSIPATION (W)
2.5
2.0
1.5
1.0
0.5
0
0
INPUT VOLTAGE RANGE AND OUTPUT
VOLTAGE vs. SUPPLY VOLTAGE
20
R
= 1k
L
TC= 25˚C
15
(±V)
OUT
10
, V
INCM
V
5
0
010
SUPPLY VOLTAGE (±V)
V
OUT
V
IN
520
15
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
24
22
20
18
16
14
SUPPLY CURRENT (mA)
12
10
510
SUPPLY VOLTAGE (±V)
(UNCOMPENSATED)
0
10k
VOLTAGE GAIN (dB)
80
60
40
20
T = -55˚C
A
TC= 25˚C
T = +125˚C
A
BODE PLOT
GAIN
FREQUENCY (Hz)
15 20
V
= ±15V
S
PHASE
100M
10M1M100k
0
45
90
135
180
225
270
PHASE (DEGREES)
VOLTAGE GAIN (dB)
BODE PLOT (UNITY GAIN
80
60
40
20
0
10k
COMPENSATED)
PHASE
GAIN
FREQUENCY (Hz)
V
10M1M100k
= ±15V
S
100M
PHASE (DEGREES)
0
45
90
135
VOLTAGE GAIN (dB)
26
24
22
20
18
16
14
12
10
8
6
10
LARGE SIGNAL
FREQUENCY RESPONSE
AV= +10
= +1
A
V
V
= ±15V
S
R
= 1k
L
= +25˚C
T
C
FREQUENCY (Hz)
100M10M1M100
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 5
LH0032 / LH0032C
TYPICAL PERFORMANCE CHARACTERI STI CS ( Cont inued )
CORPORATION
COMMON MODE REJECTION
RATIO vs. FREQUENCY
90
80
70
60
50
40
30
20
10
0
COMMON-MODE REJECTION RATIO (dB)
10k
FREQUENCY (Hz)
LARGE SIGNAL
PULSE RESPONSE
10
5
0
V
= ±15V
S
RL= 1k
VS= ±15V
= +10
A
V
= 1k
R
L
LARGE SIGNAL
PULSE RESPONSE
+10
+5
0
-5
OUTPUT VOLTAGE (V)
-10
100M10M1M100k
0 100 200 300 400 500
TIME (ns)
VS= ±15V
= +1
A
V
= 1k
R
L
NORMALIZED INPUT BIAS AND OFFSET
CURRENT vs. JUNCTION TEMPERATURE
4
10
3
10
= 25˚CTO CURRENT AT T
J
2
10
-5
OUTPUT VOLTAGE (V)
-10
0 100 200 300 400 500
TIME (ns)
NORMALIZED INPUT BIAS
CURRENT DURING WARM-UP
100
VS= ±15V
= 25˚C
T
A
10
TO CURRENT AT TIME = 0
CURRENT – NORMALIZED
1
0624
TIME FROM POWER TURN-ON (MINUTES)
1
10
CURRENT – NORMALIZED
0
10
25 8545 65
JUNCTION TEMPERATURE (˚C)
810
105 125 165145
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 6
CORPORATION
*Use polystyrene dielectric for minimum drift
V
-
V
+
LOGIC
CONTROL
LH0032
-
+
1/2 DH0034
V
+
1N914
V
IN
2N4391
100
Ω
2N2222
2N3907
S
C
= 1000pF
V
OUT
100
Ω
10k
V
-
1k
TYPICAL APPLI CA T IONS
LH0032 / LH0032C
INPUT
Unity Gain Amplifier
8pF - 10pF
-
V
12
2k
6
+
LH0032
5
10
-
V
100
100X Buffer Amplifier
+
V
INPUT
6
5
100
+
LH0032
-
12
10
-
V
10X Buffer Ampl ifier
5pF
-
V
12
2
3
11
OUTPUT
INPUT
4
6
5
+
LH0032
-
2
3
11
10
OUTPUT
9k
100pF
-
1k
V
Non-Compensated Unity Gain Inverter
+
-
LH0032
+
V
+
12
11
10
-
V
+
OUTPUT
10k
10k
11
INPUT
10k
270
0.01
5
6
High Speed Sample and Hold
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 7
LH0032 / LH0032C
TYPICAL APPLI C ATIONS (Continued)
CORPORATION
High Speed C ur ren t Mod e MU X
3.8pF
A1
A2
A3
A4
R1
5.1k
R2
5.1k
R3
5.1k
R4
5.1k
4
V
2
6
9
13
10
12
3
5
AM9710
G1
1
G2
7
G3
8
G4
14
11
5
-
LH0032
6
+
V
R5
5
12
10
-
18µF
2
6
3
11
V
OUT
APPLICATION INFORMATION:
Power Supply D ecoupling
The LH0032, like most high speed circuits, is sensitive to
layout and stray capacitance. Power supplies should be
bypassed as near to pins 10 and 12 as practicable with low
inductance capacitors such as 0.01µF disc ceramics.
Compensation components should also be located close to
the appropriate pins to minimize stray reac ta nces .
Input Curren t
Because the input devices are FETs, the input bias current
may be expected to double for each 11
o
C junction
temperature rise. This characteristic is plotted in the typical
performance characteri stics graphs. The device wil l self-heat
due to internal power dissipation after application of power
thus raising the FET junction temperature 40-60
o
C above
free-air ambient temperature when supplies are ±15V. The
device temperature will stabilize within 5-10 minutes after
application of power, and the input bias currents measured at
that time will be indicative of normal operating currents. An
additional rise would occur as power is delivered to a load due
to additional internal power dissipation .
There is an additional effect on input bias current as the input
voltage is changed. The effect, common to all FETs, is an
avalanche-like increase in gate current as the FET
gate-to-drain voltage is increased above a critical value
depending on FET geometry and doping levels. This effect
will be noted as the input voltage of the LH0032 is taken
below ground potential when the supplies are ±15V. All of the
effects described here may be minimized by operating the
device with V
≤ ±15V.
S
These effec ts are indicat ed in th e typical per for m ance curves.
Input Capacitance
The input capacitance to the LH0032/LH0032C is typically
5pF and thus may form a significant time constant with high
value resistors. For optimum performance, the input
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 8
CORPORATION
LH0032 / LH0032C
capacitance to the inverting input should be compensated by
a small capacitor across the feedback resistor. The value is
strongly dependent on layout and closed loop gain, but will
typically be in the neighbor hood of several picof arad s.
In the non-inverting configura tion, it may be advantageous to
bootstrap the case and/or a guard conductor to the inverting
input. This serves both to divert leakage currents away from
the non-inverting input and to reduce the effective input
capacitance. A unity gain follower so treated will have an
input capacitance under a picofarad .
Figure 1. LH0032 Frequency Comp ensa tion Circui t
+15V
INPUT
R2
R1
R3
5
_
LH0032
6
+
-15V
0.01µF
12
C
A
4
11
3
2
C
10
C
0.01µF
OUTPUT
Compensation
Two compensation schemes may be used, depending on the
designer’s specific n e eds.
The first technique is shown in
Figure 1.
It offers the best
0.1% settling time for a ±10V square wave input. The
compensation capacitors C
Figure 2
for various closed-loop gains.
and CA should be selected from
C
Figure 3
shows how
the LH0032 frequency response is modified for different value
compensation capacitors.
Figure 2. Recommended Va lu e of Compensa tion
Capacitor vs Closed-L oop Gain f or Optim um
Settling T ime
COMPENSATION CAPACITANCE C (pF)
C
10
5
C
0
COMPENSATION CAPACITANCE C (pF)
1 100010 100
C
C
A
CLOSED LOOP GAIN
100
75
50
25
A
0
Figur e 3. The Eff e c t of Various Com pe n sation
Capacitors on LH0032 O pe n Loop Frequenc y
Response
VOLTAGE GAIN (dB)
80
60
40
20
0
-20
10k
C
= 5pF
C
C
C
VS= ±15V
R
= 1k
L
T
= 25˚C
A
A
VOL
= 10pF
CC= 0pF
C
C
PHASE
C
= 1pF
C
C
C
= 1pF
C
C
= 0pF
= 5pF
10M1M100k
C = 10pF
C
100M
PHASE SHIFT (DEGREES)
0
-45
-90
-135
-180
Figure 4. LH0032 Unity Gai n Non-I nvert ing Lar ge
Signal Pulse Response:
T
= 25oC, CC = 10pF, CA = 100pF
A
10V
10V 100nS
FREQUENCY (Hz)
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
Page 9
LH0032 / LH0032C
CORPORATION
Although this approach offers the shortest settling time, the
falling edge exhibits overshoot up to 30% lasting 200 to
300ns.
Figure 4
shows the typical pulse response.
If obtaining minimum ringing at the falling edge is the prima ry
objective, a slight modification to the above is recommended.
It is based on the sam e circuit as tha t of
Figure 1.
The values of the unity gain compensation capacitors CC and
should be modified to 5pF and 1000pF, respectively.
C
A
Figure 5
shows the suitable capacitance to use for various
closed-loop gains. The resulting unity gain pulse response
Figure 5. Recommended Va lu e of Compensa tion
Capacitor vs Closed-L oop Gai n for Optim um Sle w Rate
5
C
4
3
C
2
C
A
1
C
COMPENSATION CAPACITANCE C (pF)
1000
500
A
waveform is shown in
Figure 6.
The settli ng t ime to 1% final
value is actually superior to the first method of compensation.
However, the LH0032 suffers slow settling thereafter to 0.1%
accuracy at the falling edge, and nearly four times as much at
the rising edge, compared to the previous scheme. Note,
however, that the falling edge ringing is considerably r educ ed.
Furthermore , the slew rate is consistently superior using this
compensation because of the smaller value of Miller
capacitance C
required.
C
The second compensation scheme works well with both
inverting or non-inverting modes.
Figure 7
shows the circuit
schematic, in which a 270ohm re sist or and a 0.0 1 µF capacit or
are shunted across the inputs of the device. This lag
compensation introduces a zero in the loop modifying the
response such that adequate phase margin is preserved at
unity gain crossover frequency. Note that the circuit requires
no additional compen sation.
Heat Sinki ng
While the LH0032 is specified for operation without any
explicit heat sink, internal power dissipation does cause a
significant temperature rise. Improved bias current
performance can thus be obtained by l imiting this t em p er at ur e
rise with a small heat sink such as the Therm alloy No. 2241 or
equivalent. The case of the device has no internal
connection, so it may be electrically connected to the sink if
this is advantageous. However, that this will affect the stray
capacitance to all pins and may thus require adjustment of
circuit compensation values.
0
COMPENSATION CAPACITANCE C (pF)
1 100010 100
CLOSED LOOP GAIN
0
Figure 6. LH0032 Unity Gai n Non-I nvert ing Lar ge
Signal Pulse Response: C
10V
10V 50nS
= 5pF, CA = 1000pF
C
Figure 7. LH0032 Non-Co mp ensa ted Uni ty Gain
Compensation
+15V
INPUT
1k
1k
0.01µF
1k
270
5
_
6
+
LH0032
-15V
0.01µF
12
11
10
0.01µF
OUTPUT
CALOGIC CORPORATION, 237 Wh itney Place, Fremont , California 94539, Telephone: 510 - 656-2900, FAX: 510-6 51 - 10 76
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