• Component Color Standards
Translations (RGB, YIQ, YUV)
• Color-Temperature Conversion
• Image Capturing and Manipulation
• Composite Color Encoding/
Decoding
• Three-Dimensional Perspective
Translation
❑❑
❑ Replaces TRW/Raytheon/Fairchild
❑❑
TMC2272
❑❑
❑ 120-pin PQFP
❑❑
DESCRIPTION
The LF2272 is a high-speed digital
colorspace converter/corrector
consisting of three simultaneous 12-bit
input and output channels for functionality up to 64 Giga (236) colors.
Some of the applications the LF2272
can be used for include phosphor
colorimetry correction, image capturing and manipulation, composite color
encoding/decoding, color matching,
and composite color standards
conversion/transcoding.
The 3 x 3 matrix multiplier (triple dot
product) allows users to easily perform three-dimensional perspective
translations or video format conversions at real-time video rates. By
using the LF2272, conversions can be
made from the RGB (color component) format to the YIQ (quadrature
encoded chrominance) or YUV (color
difference) formats and vice versa
(YIQ or YUV to RGB). Differing signal
formats in each stage of a system can
be disregarded. For example, using
an LF2272 at each format interface
allows each stage of a system to
operate on the data while in the
appropriate format.
All inputs and outputs, as well as all
control lines, are registered on the
rising edge of clock. The LF2272
operates at clock rates up to 50 MHz
over the full commercial temperature
and supply voltage ranges. A narrower data path can be used to allow
the LF2272 to work with many
different imaging applications.
DETAILS OF OPERATION
All three input ports (A, B, C) and all
three output ports (X, Y, Z) are
utilized to implement a 3 x 3 matrix
multiplication (triple dot product).
Each truncated 12-bit output is the
sum of all three input words multiplied by the appropriate coefficients
(Table 1). The pipeline latency is five
clock cycles. Therefore, the sum of
LF2272 BLOCK DIAGRAM
CLK
1-0
CWEL
A
11-0
DATA
INPUTS
COEFFICIENT
INPUTS
{
{
B
C
KA
KB
KC
11-0
11-0
9-0
9-0
9-0
10
10
10
12
12
12
2
12
12
12
X
Y
Z
11-0
11-0
11-0
{
DATA
OUTPUTS
9-MULTIPLIER
ARRAY
Video Imaging Products
1
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DEVICES INCORPORATED
LF2272
Colorspace Converter/
Corrector (3 x 12-bits)
products will be output five clock
cycles after the input data has been
registered. New output data is
subsequently available every clock
cycle thereafter.
DATA FORMATTING
The data input ports (A, B, C) and
data output ports (X, Y, Z) are 12-bit
integer two’s complement format.
The coefficient input ports (KA, KB,
KC) are 10-bit fractional two’s
complement format. Refer to
Figures 1a and 1b.
BIT WEIGHTING
The internal sum of products of the
LF2272 can grow to 23 bits. However,
in order to keep the output format
identical to the input format, the X, Y,
and Z outputs are rounded to 12-bit
integer words. The rounding is done
only at the final output stage to allow
accuracy, with correct rounding and
overflow, for applications requiring
less than 12-bit integer words. The
user may adjust the bit weighting by
applying an identical scaling correction factor to both the input and
output data streams.
Because the LF2272’s matched input
and output data formats accommodate unity gain (0 dB), input conditions that could lead to numeric
overflow may exist. To ensure that no
overflow conditions occur, the user
must be aware of the maximum input
data and coefficient word sizes
allowable for each specific algorithm
being performed.
FIGURE 1A.INPUT FORMATS
Data Input
11 10 9654873210
1121029
–2
(Sign)
7
282
Coefficient Input
SYSTEMS SMALLER THAN 12-BITS
Using a data path less than 12-bits
requires the input data to be right
justified and sign extended to 12-bits
because the LF2272 carries out all
calculations to full precision. Since all
least-significant bits are used, the
desired X, Y, and Z outputs are
rounded correctly and upper-order
output bits are used for overflow.
26252
4
2322212
0
9874326510
02–12–2
–2
(Sign)
20 19 18321170
1121029
–2
(Sign)
FIGURE 1B.OUTPUT FORMAT
11 10 9654873210
1121029
–2
(Sign)
2
282
–4
2–32
2–52–62
Internal Sum
8
2
2–62–72
Result
7
26252
Video Imaging Products
–7
2–82
–8
2
4
2322212
–9
–9
0
08/16/2000–LDS.2272-I
Page 3
DEVICES INCORPORATED
LF2272
Colorspace Converter/
Corrector (3 x 12-bits)
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers. All timing specifications are referenced to the rising
edge of CLK.
Inputs
A11-0, B11-0, C11-0 — Data Inputs
A, B, and C are the 12-bit registered
data input ports. Data presented to
these ports is latched into the multiplier input registers.
KA, KB, and KC are the 10-bit registered coefficient input ports. Data
presented to these ports is latched into
the corresponding internal coefficient
register set defined by CWEL1-0
(Table 3) on the next rising edge of
CLK. Table 2 shows which coefficient
registers are available for each coefficient input port.
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08/16/2000–LDS.2272-I
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DEVICES INCORPORATED
FIGURE 2.DETAILED FUNCTIONAL DIAGRAM
12
A
KA1KA2KA3
10
KA
12
B
LF2272
Colorspace Converter/
Corrector (3 x 12-bits)
212121
KB
KC
CWEL
KB3KB2KB1
10
212121
12
C
KC1KC2KC3
10
212121
2
12 (MSB) 12 (MSB) 12 (MSB)
XYZ
Video Imaging Products
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08/16/2000–LDS.2272-I
Page 5
DEVICES INCORPORATED
LF2272
Colorspace Converter/
Corrector (3 x 12-bits)
MAXIMUM RATINGS
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V
Input signal with respect to ground ............................................................................... –0.5V to VCC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C4.75 V ≤VCC≤ 5.25 V
Active Operation, Military –55°C to +125°C4.50 V ≤VCC≤ 5.50 V
ELECTRICAL CHARACTERISTICS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. Input levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOHmin and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCCand Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
FIGURE B. THRESHOLD LEVELS
4. Actual test conditions may vary from
those designated but operation is guaranteed as specified.
5. Supply current for a given application can be accurately approximated by:
2
NCV F
where
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCCor Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
b. Ground and VCCsupply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.