Datasheet LD4100 Datasheet (LDIC)

LD4100

EEPR4 Read/Write Controller

version 2.1

DESCRIPTION

The LD4100 is a high performance BiCMOS read channel IC that provides all of the functions needed to implement an entire EEPR4 1,7 code read channel for zoned recording hard disk drive systems with data rates from 34 to 120 Mbit/s.

Functional blocks include AGC, programmable filter, Maximum Likelihood (ML) Detector, 1,7 ENDEC, data synchronizer, time base generator, servo data detector, and 4-burst servo.

Programmable functions such as data rate, filter cutoff, filter boost, etc. are controlled by writing to the serial port registers so no external component changes are required to change zones.

1,7 RLL code operation is used to reduce the magnetic media flux transitions per inch and the write current rise time requirements.

GENERAL FEATURES

• Register programmable data rates from 34 to

120 Mbit/s

• Sampled data read channel with maximum

likelihood (ML) detector

• Programmable filter with asymmetrical zeros

to compensate pulse asymmetry

• 1,7 RLL ENDEC

• Data scrambler/descrambler

• Low operating power (0.95 W typical at 5

V)

• Register programmable power management

(<5mW power-down mode)

• Dual bit NRZ data interface

• Serial interface port for access to internal

program storage registers

• Single power supply (5 V ± 10%)

• Small footprint 100-Lead TQFP package to

internal

AUTOMATIC GAIN CONTROL

• Dual mode AGC, continuous time during

acquisition, sampled during data reads

• Separate AGC level storage pins for data and

servo

• Dual rate attack and decay charge pump for

rapid AGC recovery

• Programmable, symmetric, charge pump

currents for data reads

• Charge pump currents track programmable

data rate during data reads

• Low drift AGC hold circuitry

• Automatic AGC fast recovery and input

Low-Z modes with programmable time durations

• Wide bandwidth, precision full-wave rectifier

• 3-bit DAC to control AGC voltage in servo

mode between 0.8 and 1.5 V

LD4100

EEPR4 Read/Write Controller

Page 2 version 2.1

FILTER / EQUALIZER

Programmable, 7-pole, continuous time filter with asymmetrical zeros provides:

• Channel filter and pulse slimming

equalization for equalization to EEPR4

• Programmable cutoff frequency from 6 to 38

MHz

• Programmable boost/equalization of 0 to 17

dB

• Programmable asymmetrical zeros

equalization to correct pulse shape asymmetry

• Low-Z switch for fast offset recovery at the

filter output

• Internal AC coupling

PULSE QUALIFICATION

• Sampled Maximum Likelihood data detector

with fixed EEPR4 target detection

• With white gaussian noise, within 0.5 dB of

ideal Viterbi detector at user density of 2

• Register programmable qualification

thresholds for servo reads

• Selectable hysteresis or window qualification

modes for servo reads

TIME BASE GENERATOR

• Better than 1% frequency resolution

• Up to 180 MHz frequency output

• Independent M and N divide-by registers

DATA SEPARATOR

• Fully integrated data separator includes data

synchronizer and 1,7 RLL ENDEC

• Register programmable to 120 Mbits

operation

• Fast acquisition, zero phase restart, sampled

data phase lock loop

• Decision directed clock recovery from data

samples

• Programmable damping ratio for data

synchronizer PLL is constant for all data rates

• Data scrambler/descrambler to reduce fixed

pattern effects

• 2-bit NRZ data interface

• Data rate tracking, programmable write

precompensation for non-linear transition shift

• Differential PECL write data output with

power reduction

• Integrated dual byte sync detection

• Programmable offset to compensate for MR

head asymmetry

SERVO

• 4-burst servo capture with A, B, C, D

outputs

• Internal hold capacitors

• "Soft Landing" charge pump architecture

with programmable charge pump current

• Separate, automatically selected, registers for

servo Fc, boost, and threshold

• Wide bandwidth, precision full-wave rectifier

with programmable offset to compensate for MR head asymmetry.

• RDS and PPOL outputs for servo timing

support

LD4100

EEPR4 Read/Write Controller

Page 3 version 2.1

PROGRAMMABLE 7th

ORDER LOW-PASS

FILTER

ASYMMETRIC 0's

DC OFFSET

CANCEL

LEVEL OR

HYSTERISIS

PULSE QUAL

TPE MUX

TPD

MUX

TPC

MUX

VIA

VIA~

3

4

OD+

OD-

ON+

ON-

CPCNDP

DN

SFWR

LOWZ

FASTREC

UFDC

RX

TPD

TPD~

TPC

TPC~

TPE

87 86 93

92

85

90

SAMPLE &

HOLD

EEPR4

DETECTOR

TEST POINT

MUX

EN

LOWZ

SFC

DSCLK

RDS/RDS~

PPOL

TPA~

TPA

TPB

TPB~

RDS

71 72 65 64 63 62 13

VNS

VNP

VNF VNC

VNT

VND

VNA

60 58 46 40 16 20 34 91

VPS

VPP

VPF VPC

VPT

VPD

VPA

61 59 56 42 14 17 35 89

CODE WORD

BOUNDARY

DETECTOR

SERIAL TO

PARALLEL

SYNC

FIELD

COUNTER

1,7

DECODER

1,7

ENCODER

DESCRAMBLER

SCRAMBLER

SFC

CWBD

DUAL BIT

INTERFACE

RCLK

WCLK

NRZ0-1

SBD~

31

32-33

38

MUXMUX

PARALLEL

TO SERIAL

WRITE

PRECOMP

T

FLIP_FLOP

WD~

WD

22

21

FULL WAVE

RECTIFIER

FULL WAVE

RECTIFIER

DAC

AGC

CHARGE

PUMP

SAMPLED

AGC

CHARGE

PUMP

AGC CONTROL

LOGIC

FASTREC

LOWZ

SQUELCH

UFDC

LOWZ

FASTREC

6

8

SERIAL

PORT &

CONTROL

REGISTERS

CONTROL

LOGIC

VREF

SDEN

SCLK

SDATA

SG

RG

WG

121011

732928

BYPS

BYP

HOLD~

AGCRST

UFDC

SFC

VCC

95

96

7

9

SG

VMIN

SQUELCH

SFWR

DECODE

LOGIC

3.2V

Vref

C B A

MAXREF

STROBE

RESET~

D

8081

8283

69

6670

1/(M+1)

1/(N+1)

DECISION

DIRECTED

PHASE

DETECTOR

PHASE/

FREQ

DETECTOR

CHARGE

PUMP

PHASE/

FREQ

DETECTOR

CHARGE

PUMP

VCO

DAMPING

CONTROL

RCLK

CLOCK

GEN

ATO

TEST

MUX

POWER

DOWN

CONTROL

DSCLK

TBGOUT

CWBD

DATA SYNCHRONIZER

TIME BASE GENERATOR

MAXREF

DACs

RCLK

ATO

RCLK 37

57

FREF

FLTR2

FLTR2~

PDWN~

FLTR1~ FLTR1

RR

15 68

18

19

54

55 44

AGC

AMP

SP

SP SP

WG

SP

SFC

SP

TBGOUT

SP

SERVO

LEAKAGE

+

-

SP

Fig 1 LD4100 Block Diagram

SP

1/24

SPSP SP

SYNC BYTE

DETECTOR

BUFFER

SP

LD4100

EEPR4 Read/Write Controller

Page 48 version 2.1

This document may contain preliminary information and is subject to change by LDIC without notice. LDIC assumes no responsibility or liability for any use of this information herein. Nothing in this document shall operate as an express or implied license of indemnity under the intellectual property rights of LDIC or third parties. NO WARRENTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIES WARRENTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.

N/C

RG

WG

N/C

SBD~

NRZ1

NRZ0

VND

VPD

RCLK

N/C

WCLK

N/C

VNC

VPC

N/C

PWRDN~

VNP

N/C

WD~

N/C

WD

VNT

FLTR1

FLTR1~

VPT

VNF

VPF

FREF

RDT

SDEN

SCLK

SDATA

AGCRST

FASTREC

LOWZ

HOLD~

N/C

VIA~

N/C

VIA

N/C

D

CAB

N/C

TPE

TPD

TPD~

N/C

VPA

VNA

RX

TPC~

TPC

BYPS

N/C

BYPD

N/C

100-Lead TQFP

N/C N/C

PPOL

SG

RDS~ RESET~

RR

MAXREF N/C

STROBE TPA~

TPA TPB

TPB~

VNS

VPS VPS

VNS VPP

ATO FLTR2

FLTR2~ N/C

N/C N/C

LD4100

75 74

72

73

71 70

68

69

67

66

64

65

63

62

60

61 59

58

56

57 55

54 52

53 51

26

272928

30

313332343537363839

41

40424345444647

494850

25

24

22 23

21

20

18 19

17

16

14 15

13

12

10 11

9

8

6

7

5

4

2

3

1

76

777978

80

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88

899190

92

939594

96

979998

100