Page 1
LD4000
PR4/EPR4 Read/Write Controller
GENERAL DESCRIPTION
The part is a high performance BICMOS read channel IC that provides all of the functions needed to
implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive
systems with data rates from 67 to 212 Mbps.
Functional blocks include a serial port, an automatic gain control amplifier, a programmable filter, an
offset canceller, a peak detecting pulse qualifier, an adaptive transversal filter, a Viterbi qualifier, a 8/9
GCR ENDEC, a data synchronizer, a time base generator, an integrating servo demodulator, as shown in
figure 1.
The part requires a single +5V power supply. The part utilizes an advanced BiCMOS process technology
along with advanced circuit design techniques which results in a high performance device with low power
consumption.
FEATURES
GENERAL
• Register programmable data rates from 67 to
212 Mbit/s
• Sampled data read channel with Viterbi
qualification
• Programmable filter for PR4 equalization
• Five tap transversal filter with adaptive PR4
equalization
• 8/9 GCR ENDEC
• Data Scrambler / Descrambler
• Presettable Precoder state
• Programmable write precompensation
• Low operating power - 1000mW maximum
at 5.5V to allow use of TOFP packages.
Active power management is applied to
achieve this target
• Register programmable power management
(<5 mW power down mode)
• 4-bit nibble and byte wide bi-directional
NRZ data interface
• 8 bit direct write mode automatically
configured for CLK=VCO/8
• Serial Interface port for access to internal
program storage registers
• Single power supply (5V ± 10%)
• Small package footprint: 100 lead TOFP
AUTOMATIC GAIN CONTROL
• Dual mode AGC, continuous time during
acquisition, sampled during data reads
• Separate AGC level storage pins for data and
servo
• Dual rate attack and decay charge pump for
rapid AGC recovery in continuous time mode
• Programmable, symmetric, charge pump
currents for data reads in sampled mode
• Charge pump currents track programmable
data rate during data reads
• Low drift AGC hold circuitry
• Low-Z circuitry at AGC input provides for
rapid external coupling capacitor recovery
• AGC Amplifier squelch during Low-Z
• Wide bandwidth amplitude feedback circuit
to allow improved stability of AGC level vs.
frequency
• Programmable AGC controls
• Separate external input pins for AGC
hold, fast recovery, and Low-Z control
or
• Internal Low-Z and fast recovery timing
for rapid transient recovery and AGC
acquisition. Timing set with external
resistors (2). Ultra fast decay current set
with external resistor.
version 2.1
Page 2
LD4000
PR4/EPR4 Read/Write Controller
FILTER / EQUALIZER
• Programmable, 7-pole, continuous time filter
with asymmetrical zeros
• Channel filter and pulse slimming
equalization for coarse equalization to PR4
• Programmable cutoff frequency from 10 to
56 MHz
• Programmable boost/equalization of 0 to 13
dB
• Programmable “zeros” equalization provides
asymmetry compensation
• ±30% group delay variation from 0.3Fc to
Fc with Fc=56 MHz
• Low-Z switch for fast offset recovery at the
filter output
• No external coupling capacitors required
• DC offset compensation provided at the filter
output
• Three or Five tap transversal filter for fine
equalization to PR4.
• Self adapting symmetric Inner taps
• Programmable symmetric outer taps with 4
bits of resolution
• Equalization hold input
• Asymmetry factor output and “zeros”
channel quality output
PULSE QUALIFICATION
• Sampled Viterbi qualification of signal
equalized to PR4
• Register programmable hysteresis or window
qualification peak detector for servo reads,
with programmable thresholds
• Selectable RDS pulse width for servo grey
code reads
• RDS and PPOL outputs are disabled during
burst capture to reduce noise generation
DATA SEPARATOR
• Fully integrated data separator includes data
synchronizer and 8/9 GCR ENDEC
• Register programmable to 212 Mbps
• Fast Acquisition, sampled data phase locked
loop
• Decision directed clock recovery from data
samples
• Adaptive clock recovery thresholds
• Programmable damping ratio for data
synchronizer PLL is constant for all data
rates
• Data scrambler / descrambler to reduce fixed
pattern effects
• Byte wide NRZ data interface and 4 bits
nibble interface
• Time base tracking, programmable write
precompensation
• Differential PECL write data output
• Surface defect scan mode
• Direct Write modes
SERVO
• 6-burst servo capture with A-B, C-D, E-F
outputs
• Internal hold capacitors
• Separate, automatically selected, registers for
servo fc, boost, and threshold
• Wide bandwidth, high precision full-wave
rectifier is optimized for low-level linearity
• “Soft Landing” charge pump architecture
• Programmable selection of normal or
differentiated filter output to servo-capture
block
• Programmable gain with 2 external inputs
TIME BASE GENERATOR
• Better than 1% frequency resolution
• Up to 225 MHz frequency output
• Independent M and N divide-by registers
• No active external components required
Page 2 version 2.1
Page 3
LD4000
Fig 1 LD4000 Block Diagram
PR4/EPR4 Read/Write Controller
VPA
VPD
VPT
VPF
VPC
VPP
VPS
VPS
VNA
VND
VNT
VNF
VNC
VNP
VNS
VNS
VRDT
TPBB
TPB
TPAB
TPA
EQHOLD
PPOL
RDS/RDSB
TPE
TPCB
TPC
TPDB
TPD
SBDB
30
BYTE
DUAL "OR"
TYPE SYNC
62 68 58 47 12 15 38 95
69 67 55 54 14 18 37 86
SP
MUX
TEST POINT
84 85 60 66 65 64 63 8
UFDC
FASTREC
87
LOWZ
TPE MUX
SFWR
TPD
TPC
MUX
MUX
SP
CPCNDP
OD-
OD+
PROGRAMMABLE 7th
91
88 89 90
96
RX
AGC
98
VIA
NRZP
PERR/NCLK
31
32
PARITY
GEN/CHK
DETECTOR
To SFC
LEVEL OR
HYSTERISIS
PULSE QUAL
DN
SFC
CANCEL
EN
DC OFFSET
ON+
ON-
FILTER
ASYMMETRIC 0's
ORDER LOW-PASS
AMP
97
VIAB
33-36, 39-42
CHANQUAL
LOWZ
SP SP
NRZ0-7
PARALLEL
INTERFACE
DESCRAMBLER
9/8
(0,4/4)
DECODER
PARALLEL
SERIAL TO
CODE WORD
MUX
VITERBI
DETECTOR
SSBYP
5-TAP
2-PROG
EQUALIZER
2-ADAPTIVE
SQUELCH
4
WCLK
43
NIBBLE
SCRAMBLER
8/9
(0,4/4)
DSCLK
CWBD
DETECTOR
BOUNDARY
SP SP
ASYMM FACTOR
VMIN
SG
3
BYPS
BYPD
INTERFACE
ENCODER
SFC
SYNC
FIELD
FROM
SP
DSCLK
DWB
DW
19
20
RCLK
AUTOMATIC
GENERATOR
TRAINING & SYNC BYTE
COUNTER
LEVEL QUAL
WDBWDDWRB
212245
WRITE
WRITE
PRECODER
PARALLEL
TO SERIAL
MUX
FLIP-FLOP
MUXMUX
PRECOMP
GEN
PATTERN
VCO SYNC
SP
SP
TBGOUT
RCLK
RCLK 44
RCLK
CLOCK
DSCLK
CWBD
VCO
DATA SYNCHRONIZER
CHARGE
PHASE
DECISION
DIRECTED
DETECTOR
C
E
GEN
TBGOUT
PUMP
SFC
SP
ATO
61
SP
ATO
MUX
TEST
DACs
VREFS
CHANQUAL
ASYMM FACTOR
DAMPING
CONTROL
DOWN
POWER
CONTROL
SP
VCO
PUMP
CHARGE
TBGOUT
TIME BASE GENERATOR
FREQ
PHASE/
DETECTOR
1/(M+1)
1/(N+1)
SP
FREQ
PHASE/
A
DETECTOR
VREFS
RECTIFIER
FULL WAVE
RECTIFIER
FULL WAVE
SP
DAC
SERVO
AGC
CONV
PUMP
SFC
HOLD
UFDC
5
92
HOLDB
AGCRST
VCC
Page 3 version 2.1
CHARGE
AGC
CHARGE
SAMPLED
PUMP
SP
LOGIC
LEAKAGE
SP
SERIAL
PORT &
11910
SCLK
SDEN
DECODE
CONTROL
REGISTERS
SDATA
CONTROL
832928
SG
RG
LOGIC
WG
-
+
SFWR
SP
SMS
HOLD
LOWZ
FASTREC
AGC CONTROL
6
7
94
LOWZ
WRDEL
FASTREC
SQUELCH
LOGIC
UFDC
93
AGCDEL
SERVO
SP
VREF
73
VREF
SP
PDWNB
56 46
FLTR2B
FLTR2
57
17
FLTR1B
FLTR1
16
RR
13 72
FREF
79808182716970
E-F
C-D
A-B
N/X
AV1
7877
AV0
VREFS
STROBE
RESETB
Page 4
LD4000
PR4/EPR4 Read/Write Controller
N/C
N/C
BYPD
BYPS
HOLDB
LOWZ
FASTREC
VRDT
SCLK
SDATA
SDEN
VPF
FREF
VNF
VPT
FLTR1
FLTR1B
VNT
DW1B
DW1
WDB
WD
N/C
N/C
N/C
2
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
N/C
RX
VIA
N/C
96
979998
100
1
3
4
5
7
8
9
272928
30
26
AGCRST
92
939594
3133323435373638394140
TPCB
AGCDEL
VPA
WRDEL
VIAB
TPC
TPD
TPDB
88
899190
TPE
87
VNA
86
PPOL
85
SG
RDS/RDSB
84
42
43454446474948
N/X
A-B
818382
C-D
80
E-F
AV1
AV0
777978
N/C
76
50
59
58
57
55
54
53
51
75
74
73
71
70
69
68
67
66
65
64
63
62
61
60
56
52
72
N/C
N/C
VREF
RR
VREFS
RESETB
STROBE
VPS
VNS
TPA
TPAB
TPB
TPBB
VPS
ATO
EQHOLD
VNS
VPP
FLTR2
FLTR2B
VNP
VNC
N/C
N/C
N/C
N/C
N/C
WG/WGB
RG
SBDB
PERR
NRZ0
NRZP
NRZ1
NRZ2
VND
NRZ3
VPD
NRZ4
NRZ5
NRZ7
NRZ6
RCLK
WCLK
DWRB
PDWNB
VPC
N/C
N/C
N/C
LD4000
100-Lead TQFP
Page 54 version 2.1
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