Datasheet LD39100PUR, LD39100PU12R, LD39100PU25R Datasheet (ST)

LD39100XX12, LD39100XX25

1 A, low quiescent current, low noise voltage regulator

Features

■ Input voltage from 1.5 to 5.5 V

■ Ultra low dropout voltage (200 mV typ. at 1 A

load)

■ Very low quiescent current (20 µA typ. at no

load, 200 µA typ. at 1 A load, 1 µA max in off mode)

■ Very low noise with no bypass capacitor

(30 µV

■ Output voltage tolerance: ± 2.0 % @ 25 °C

■ 1 A guaranteed output current

■ Wide range of output voltages available on

request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 V

■ Logic-controlled electronic shutdown

■ Stabilized with ceramic capacitors C

■ Internal current and thermal limit

■ DFN6 (3 x 3 mm) package

■ Temperature range: - 40 °C to 125 °C

Applications

■ Printers

■ Personal digital assistants (PDAs)

■ Cordless phones

■ Consumer applications

RMS

at V

OUT

= 0.8 V)

OUT

= 1 µF

LD39100XX

DFN6 (3 x 3 mm)

with a typical dropout voltage of 200 mV. The device is stable due to the use of ceramic capacitors on the input and output. The ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery powered applications. Power supply rejection is 65 dB at low frequencies and starts to roll off at 10 kHz. An enable logic control function puts the LD39100xx in shutdown mode, allowing a total current consumption lower than 1 µA. The device also includes short-circuit constant current limiting and thermal protection.

Description

The LD39100xx provides 1 A maximum current from an input voltage ranging from 1.5 V to 5.5 V

Table 1. Device summary

October 2011 Doc ID 15676 Rev 3 1/23

Part numbers Order codes Output voltages

LD39100XX LD39100PUR Adj. from 0.8 V

LD39100XX12 LD39100PU12R 1.2 V

LD39100XX25 LD39100PU25R 2.5 V

www.st.com

23

Contents LD39100XX, LD39100XX12, LD39100XX25

Contents

1 Circuit schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Power Good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Circuit schematics

1 Circuit schematics

Figure 1. Schematic diagram for the LD39100PU

IN

BandGap

BandGap reference

reference

OpAmp

EN

Figure 2. Schematic diagram for the LD39100PUxx

Internal

Internal enable

enable

GND

Power-good

Current

limit

Thermal

protection

signal

PG

IN

ININ

OUT

ADJ

IN

BandGap

BandGap reference

reference

OpAmp

EN

Internal

Internal enable

enable

GND

Power-good

Current

limit

Thermal

protection

signal

PG

IN

ININ

OUT

R

1

NC

R

2

Doc ID 15676 Rev 3 3/23

Pin configuration LD39100XX, LD39100XX12, LD39100XX25

2 Pin configuration

Figure 3. Pin connection (top view)

EN

GND

PG

LD39100PUxx

V

NC

V

IN

OUT

EN

GND

PG

LD39100PU

Table 2. Pin description

Pin n°

Symbol

LD39100PU LD39100PUxx

EN 1 1 Enable pin logic input: Low = shutdown, High = active

GND 2 2 Common ground

PG 3 3 Power Good

V

OUT

4 4 Output voltage

ADJ 5 - Adjust pin

V

IN

6 6 Input voltage of the LDO

NC - 5 Not connected

GND EXP pad Exposed pad must be connected to GND

Function

V

IN

ADJ

V

OUT

4/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Maximum ratings

3 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

IN

V

OUT

EN Enable pin -0.3 to V

DC input voltage -0.3 to 7 V

DC output voltage -0.3 to VIN + 0.3 (7 V max) V

+ 0.3 (7 V max) V

IN

PG Power Good pin -0.3 to 7 V

ADJ Adjust pin 4 V

I

T

OUT

P

D

STG

OP

Output current Internally limited

Power dissipation Internally limited

Storage temperature range - 65 to 150 °C

Operating junction temperature range - 40 to 125 °C

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.

Functional operation under these conditions is not implied. All values are referred to GND.

Table 4. Thermal data

Symbol Parameter Value Unit

R

thJA

thJC

Thermal resistance junction-ambient 55 °C/W

Thermal resistance junction-case 10 °C/W

Table 5. ESD performance

Symbol Parameter Test conditions Value Unit

ESD ESD protection voltage

HBM 4 kV

MM 0.4 kV

Doc ID 15676 Rev 3 5/23

Electrical characteristics LD39100XX, LD39100XX12, LD39100XX25

4 Electrical characteristics

TJ = 25 °C, V

= 1.8 V, CIN = C

IN

OUT

= 1 µF, I

= 100 mA, VEN = VIN, unless otherwise

OUT

specified.

Table 6. Electrical characteristics for the LD39100PU

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

IN

V

ADJVADJ

I

ADJ

ΔV

OUT

ΔV

OUT

ΔV

OUT

ΔV

OUT

V

DROP

e

N

SVR

I

Q

PG

I

SC

Operating input voltage 1.5 5.5 V

I

=10mA, TJ = 25°C 784 800 816

accuracy

OUT

=10mA, -40°C<TJ<125°C 776 800 824

I

OUT

Adjust pin current 1µA

+1 V ≤ VIN ≤ 5.5 V,

V

Static line regulation

Transient line regulation

(1)

Static load regulation I

Transient load regulation

Dropout voltage

(2)

(1)

Output noise voltage

Supply voltage rejection

= 0.8 V

V

O

Quiescent current

Power good output threshold

OUT

=100mA

I

OUT

ΔVIN=500mV, I

=500mV, I

ΔV

IN

=10mA to 1A 0.002 %/mA

OUT

I

=10mA to 1A, tR=5µs 40

OUT

=1A to 10mA, tF=5µs 40

I

OUT

I

=1A, VO fixed to 1.5V

OUT

=100mA, tR=5µs 10

OUT

=100mA, tF=5µs 10

OUT

-40°C<TJ<125°C

10Hz to 100kHz, I V

=0.8V

OUT

VIN=1.8V+/-V V

RIPPLE

I

=10mA

OUT

=1.8V+/-V

V

IN

V

RIPPLE

I

=100mA

OUT

=0mA 20

I

OUT

I

=0mA, -40°C<TJ<125°C 50

OUT

=0 to 1A 200

I

OUT

=0 to 1A, -40°C<TJ<125°C 300

I

OUT

V

input current in off mode:

IN

VEN=GND

RIPPLE

=0.25V, freq. = 1kHz

RIPPLE

=0.25V, freq.=10kHz

(3)

OUT

=100mA,

Rising edge

Falling edge

0.01 %/V

200 400 mV

30 µV

65

62

0.001 1

0.92* V

OUT

0.8*

V

OUT

Power good output voltage low Isink=6mA open drain output 0.4 V

Short-circuit current RL=0 1.5 A

mV

mVpp

RMS

dB

µA

V

6/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Electrical characteristics

Table 6. Electrical characteristics for the LD39100PU (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

EN

Enable input logic high 0.9 V

I

Enable pin input current VEN= V

EN

t

ON

Turn-on time

(4)

=1.5V to 5.5V, -40°C<TJ<125°C

V

IN

0.1 100 nA

30 µs

Enable input logic low

0.4 V

Thermal shutdown 160

T

SHDN

Hysteresis 20

°C

Capacitance (see typical

C

Output capacitor

OUT

performance characteristics for

122µF

stability)

1. All transient values are guaranteed by design, not production tested

2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 1.5 V

3. PG pin floating

4. Turn-on time is time measured between the enable input just exceeding V reaching 95% of its nominal value

high value and the output voltage just

EN

Doc ID 15676 Rev 3 7/23

Electrical characteristics LD39100XX, LD39100XX12, LD39100XX25

TJ = 25 °C, V

IN

= V

OUT(NOM)

+ 1 V, CIN = C

OUT

= 1 µF, I

= 100 mA, VEN = VIN, unless

OUT

otherwise specified.

Table 7. Electrical characteristics for LD39100PUxx

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

V

OUTVOUT

ΔV

OUT

ΔV

OUT

ΔV

OUT

ΔV

OUT

V

DROP

Operating input voltage 1.5 5.5 V

>1.5V, I

V

OUT

V

>1.5V, I

OUT

-40°C<TJ<125°C

=10mA, TJ = 25°C -2.0 2.0

OUT

=10mA,

OUT

-3.0 3.0

accuracy

V

Static line regulation V

Transient line regulation

(1)

Static load regulation I

Transient load regulation

Dropout voltage

(2)

(1)

≤ 1.5V, I

OUT

V

≤ 1.5V, I

OUT

-40°C<TJ<125°C

+1V ≤ VIN ≤ 5.5V, I

OUT

ΔVIN=500mV, I

=500 mV, I

ΔV

IN

=10 mA to 1A 0.002 %/mA

OUT

I

=10 mA to 1A, tR=5µs 40

OUT

=1A to 10mA, tF=5µs 40

I

OUT

I

=1A, V

OUT

-40°C<TJ<125°C

=10mA ±20

OUT

=10mA,

OUT

=100mA 0.01 %/V

OUT

=100mA, tR=5µs 10

OUT

=100mA, tF=5µs 10

OUT

> 1.5V,

OUT

±30

mV

mVpp

200 400 mV

%

e

N

SVR

I

Q

Output noise voltage

Supply voltage rejection

=1.5V

V

OUT

Quiescent current

10Hz to 100kHz, I V

=2.5V

OUT

VIN=V

OUT(NOM

V I

V V I

I

V V

=0.1V, freq. = 1kHz

RIPPLE

=10mA

OUT

IN=VOUT(NOM)

=0.1V, freq.=10 kHz

RIPPLE

=100mA

OUT

= 0 mA 20

OUT

= 0 mA, -40°C<TJ<125°C 50

OUT

= 0 to 1A 200

OUT

= 0 to 1A -40°C<TJ<125°C 300

OUT

input current in OFF mode:

IN

EN

= GND

(3)

Rising edge

Power good output threshold

PG

Power good output voltage low Isink=6mA open drain output 0.4 V

Short-circuit current RL=0 1.5 A

I

SC

Falling edge

Enable input logic low

V

EN

Enable input logic high 0.9 V

=1.5 V to 5.5 V, -40°C<TJ<125°C

V

IN

=100mA,

OUT

)+0.5V+/-V

+0.5V+/-V

RIPPLE

85 µV

65

62

0.001 1

0.92* V

OUT

0.8*

V

OUT

0.4 V

RMS

dB

µA

V

8/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Electrical characteristics

Table 7. Electrical characteristics for LD39100PUxx (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

Enable pin input current V

EN

T

ON

Turn-on time

(4)

Thermal shutdown 160

T

SHDN

Hysteresis 20

C

1. All transient values are guaranteed by design, not production tested

2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This

3. PG pin floating

4. Turn-on time is time measured between the enable input just exceeding V

Output capacitor

OUT

specification does not apply for output voltages below 1.5 V

95% of its nominal value

= V

EN

IN

Capacitance (see typical performance characteristics for stability)

high Value and the output voltage just reaching

EN

0.1 100 nA

30 µs

°C

122µF

Doc ID 15676 Rev 3 9/23

Typical performance characteristics LD39100XX, LD39100XX12, LD39100XX25

5 Typical performance characteristics

CIN = C

Figure 4. V

0.86

0.84

0.82

[V]

0.8

ADJ

V

0.78

0.76

0.74

ADJ

V

= 1.8 V, V

V

= 1.8 V, V

IN

EN

IN

EN

-50 -25 0 25 50 75 100 125 150

= 1 µF.

OUT

accuracy Figure 5. V

= VIN, I

= 10 mA

= VIN, I

= 10 mA

OUT

T [°C]

Figure 6. Dropout voltage vs. temperature

(V

= 2.5 V)

VENto VIN, V

OUT

= 2.5 V, I

= 1 A

OUT

T [°C]

350

300

250

200

150

100

Dropout [mV]

50

0

-50 -25 0 25 50 75 100 125 150

accuracy

OUT

2.56

V

= 3.5 V, V

= VIN, I

EN

= VIN, I

OUT

= 10 mA

T [°C]

V

= 3.5 V, V

IN

2.5

-50 -25 0 25 50 75 100 125 150

[V]

V

OUT

2.54

2.52

2.48

2.46

2.44

Figure 7. Dropout voltage vs. temperature

(V

= 1.5 V)

OUT

400

VENto VIN, V

350

300

250

200

150

Dropout [mV]

100

50

0

-50 -25 0 25 50 75 100 125 150

OUT

@ 1.5 V, I

= 1 A

OUT

T [°C]

Figure 8. Dropout voltage vs. output current Figure 9. Short-circuit current vs. drop

0.25

V

@ 1.5 V

V

@ 1.5 V

OUT

0.2

0.15

0.1

Dropout [V]

0.05

OUT

V

= 2.5 V

V

= 2.5 V

OUT

0

0 200 400 600 800 1000 1200

I

V

OUT

EN

to V

[mA]

IN

10/23 Doc ID 15676 Rev 3

3.5

3

2.5

2

[A]

SC

1.5

I

1

0.5

0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

voltage

VINfrom 0 to 5.5 V, VENto VIN, V

OUT

= 0.8 V

Vdrop [V]

125 °C

125 °C 85 °C

85 °C 55 °C

55 °C 25 °C

25 °C

0 °C

-25 °C

-40 °C

LD39100XX, LD39100XX12, LD39100XX25 Typical performance characteristics

Figure 10. Output voltage vs. input voltage

1.2

1

0.8

[V]

0.6

OUT

V

0.4

0.2

0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

(V

= 0.8 V)

OUT

VINfrom 0 to 5.5 V, VENto VIN, V

Figure 11. Output voltage vs. input voltage

(V

= 2.5 V)

OUT

3

= 0.8 V, I

= 1 A

= 0.8 V, I

OUT

V

[V]

IN

= 1 A

OUT

125°C

85°C

55°C

25°C

0°C

-25°C

-40°C

3

VINfrom 0 to 5 V, VENto VIN, V

2.5

2

[V]

1.5

OUT

V

1

0.5

0

00.511.522.533.544.555.56

OUT

= 2.5 V, I

= 1A

OUT

[V]

V

IN

Figure 12. Quiescent current vs. temperature Figure 13. VIN input current in off mode vs.

140

120

100

No Load

80

60

Iq [µA]

VIN= 1.8 V, VENto VIN, V

40

20

0

-50 -25 0 25 50 75 100 125 150

OUT

= 2.5 V

T [°C]

No Load

I

= 1 A

I

= 1 A

OUT

0.6

0.5

0.4

0.3

Iq [µA]

0.2

0.1

0

temperature

VIN= 3.5 V, VENto GND, V

-50 -25 0 25 50 75 100 125 150

= 2.5 V

OUT

T [°C]

125°C

85°C

55°C

25°C

0°C

-25°C

-40°C

Figure 14. Load regulation Figure 15. Line regulation

0.04

0.015

0.01

0.005

0

-0.005

Load [%/mA]

-0.01

-0.015

-50 -25 0 25 50 75 100 125 150

VIN= 3.5 V, I

= from 10 mA to 1 A, VEN=VIN, V

OUT

T [°C]

= 2.5 V

OUT

0.04

VIN= from 1.8 V to 5.5 V, I

0.03

0.02

0.01

0

-0.01

Line [%/V]

-0.02

-0.03

-0.04

-50 -25 0 25 50 75 100 125 150

Doc ID 15676 Rev 3 11/23

= 100 mA, VEN= VIN, V

OUT

T [°C]

= 0.8 V

OUT

Typical performance characteristics LD39100XX, LD39100XX12, LD39100XX25

Figure 16. Line regulation Figure 17. Supply voltage rejection vs.

0.04

-0.01

Line [%/V]

-0.02

-0.03

-0.04

0.04

0.03

0.02

0.01

VIN= from 3.5 V to 5.5 V, I

0

-50 -25 0 25 50 75 100 125 150

= 100 mA, VEN= VIN, V

OUT

T [°C]

= 2.5 V

OUT

Figure 18. Supply voltage rejection vs.

100

80

60

40

SVR [dB]

20

0

-50 -25 0 25 50 75 100 125 150

temperature (V

VINfrom 2.9 V to 3.1 V, VENto VIN, V

T [°C]

= 2.5 V)

OUT

Freq. = 10 kHz, I

Freq. = 1 kHz, I

= 2.5 V

OUT

= 100 mA

= 10 mA

temperature (V

100

80

60

40

SVR [dB]

20

0

-50 -25 0 25 50 75 100 125 150

VINfrom 1.7 V to 1.9 V, VENto VIN, V

T [°C]

Figure 19. Supply voltage rejection vs.

frequency (V

100

VINfrom 1.55 V to 2.05 V, VENto VIN, V

80

60

40

SVR [dB]

20

0

0 102030405060708090100110

Freq [kHz]

OUT

= 0.8 V

= 0.8 V)

OUT

Freq.10 kHz, I

Freq.1 kHz, I

= 0.8 V)

= 0.8 V

OUT

= 100 mA

OUT

= 10 mA

OUT

I

OUT

I

OUT

= 10 mA

= 100 mA

Figure 20. Supply voltage rejection vs.

100

90

90 80

80 70

70 60

60 50

50 40

40

SVR [dB]

30

30 20

20 10

10

0

0 102030405060708090100110

frequency (V

VINfrom 2.9 V to 3.1 V, VENto VIN, V

12/23 Doc ID 15676 Rev 3

OUT

= 2.5 V

OUT

Freq [kHz]

= 2.5 V)

I

OUT

I

OUT

= 10 mA

= 100 mA

Figure 21. Output noise voltage vs. frequency

AP - IOUT = 10 0mA

2.5

2.0

1.5

1.0

eN [µV/SQRT(Hz)]

0.5

0.0

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

VIN = 1.8 V, V

= 0.8 V, VEN = V

OUT

f [Hz]

AP - IOUT = 10 mA

AP - IOUT = 1mA

AP - IOUT = 0A

IN

LD39100XX, LD39100XX12, LD39100XX25 Typical performance characteristics

Figure 22. Enable voltage vs. temperature Figure 23. Load transient (I

1

0.9

0.8

0.7

0.6

[V]

0.5

EN

V

0.4

0.3

0.2

0.1

0.1 0

0

-50 -25 0 25 50 75 100 125 150

Figure 24. Load transient (V

V

OUT

VIN= 5.5 V I

= 100 mA, V

OUT

T [°C]

= 0.8 V

OUT

= 0.8 V) Figure 25. Load transient (V

OUT

High

Low

V

OUT

I

OUT

VEN= VIN=3.5V, V

tR= tF =5 µs

V

OUT

to 1 A)

=0.8V, I

OUT

= from10mA to 1A,

OUT

= from 10 mA

OUT

= 2.5 V)

OUT

I

OUT

VEN= VIN=3.5V, V

tR= tF =5 µs

OUT

Figure 26. Load transient (I

VEN= VIN=3.5V, V

V

OUT

I

OUT

tR= tF =5 µs

to 1 A)

OUT

=0.8V, I

=2.5V, I

= from100 mA to 1A,

OUT

= from 100 mA

OUT

= from100 mA to 1A,

OUT

I

OUT

VEN= VIN=3.5V, V

tR= tF =5 µs

OUT

=2.5V, I

= from10 mA to 1A,

OUT

Figure 27. Line regulation transient

V

IN

V

OUT

VEN= V

=1.8 V to 2.3 V, V

IN

t

= tF = 5 µs

R

OUT

= 0.8V, I

OUT

=100 mA,

Doc ID 15676 Rev 3 13/23

Typical performance characteristics LD39100XX, LD39100XX12, LD39100XX25

Figure 28. Startup transient Figure 29. Enable transient

V

IN

V

OUT

V

EN

V

OUT

VEN= VIN= from 0.8 V, V

OUT

=0.8 V, I

OUT

= 100 mA

Figure 30. ESR required for stability with

ESR @ 100 kHz [ohm]

V

= V

IN

mA to 1 A

0.25

0.2

0.15

0.1

0.05

0

EN

ceramic capacitors (V

UNSTABLE ZONE

STABLE ZONE

1 2 3 4 5 6 7 8 9 10111213141516171819202122

= from 1.5 V to 5.5 V, V

C

[µF] (no minal valu e)

OUT

= 0.8 V, I

OUT

= 0.8 V)

= from 1

VEN= 0 to 2 V, V

tR = 5 µs

OUT

=0.8 V, V

= 3.5 V, I

IN

= 100 mA,

OUT

Figure 31. ESR required for stability with

0.25

0.2

]

Ω

0.15

0.1

ESR @ 100kHz [

0.05

0

12345678910111213141516171819202122

V

= V

IN

EN

mA to 1 A

ceramic capacitors (V

UNSTABLE ZONE

STABLE ZONE

C

[µF] (nominal value)

C

[µF] (nominal value)

OUT

= from 3.5 V to 5.5 V, V

OUT

= 2.5 V, I

OUT

= 2.5 V)

= from1

14/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Application information

6 Application information

The LD39100xx is an ultra low dropout linear regulator. It provides up to 1 A with a low 200 mV dropout. The input voltage range is from 1.5 V to 5.5 V. The device is available in fixed and adjustable output versions.

The regulator is equipped with internal protection circuitry, such as short-circuit current limiting and thermal protection.

The regulator is stable due to ceramic capacitors on the input and the output. The expected values of the input and output ceramic capacitors are from 1 µF to 22 µF with 1 µF typical. The input capacitor must be connected within 0.5 inches of the V capacitor must also be connected within 0.5 inches of output pin. There is no upper limit to the value of the input capacitor.

Figure 32 and Figure 33 illustrate the typical application schematics:

Figure 32. Typical application circuit for the fixed output version

V

IN

6

V

IN

PG

3

terminal. The output

IN

1

OFF ON

C

IN

Figure 33. Typical application circuit for the adjustable version

V

IN

C

OFF ON

6

1

OFF ON

IN

LD39100PUxx

EN

V

IN

LD39100PU

EN

GND

2

GND

2

V

OUT

NC

PG

V

OUT

ADJ

V

OUT

C

OUT

V

OUT

4

5

3

4

R

1

5

1

R

2

Doc ID 15676 Rev 3 15/23

Application information LD39100XX, LD39100XX12, LD39100XX25

For the adjustable version, the output voltage can be adjusted from 0.8 V up to the input voltage, minus the voltage drop across the PMOS (dropout voltage), by connecting a resistor divider between the ADJ pin and the output, thus allowing remote voltage sensing.

The resistor divider should be selected using the following equation:

V

= V

OUT

It is recommended to use resistors with values in the range of 10 k

(1 + R1 / R2) with V

ADJ

= 0.8 V (typ.)

ADJ

Ω to 50 kΩ. Lower values

can also be suitable, but will increase current consumption.

6.1 Power dissipation

An internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 160 °C. This feature protects the device from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without the risk of damaging the device.

It is very important to use a good PC board layout to maximize power dissipation. The thermal path for the heat generated by the device is from the die to the copper lead frame through the package leads and exposed pad to the PC board copper. The PC board copper acts as a heat sink. The footprint copper pads should be as wide as possible to spread and dissipate the heat to the surrounding ambient. Feed-through vias to the inner or backside copper layers are also useful in improving the overall thermal performance of the device.

The power dissipation of the device depends on the input voltage, output voltage and output current, and is given by:

P

= (VIN -V

D

OUT

) I

OUT

The junction temperature of the device is:

T

J_MAX

= TA + R

thJA

x P

D

where:

T

R

Figure 34. Power dissipation vs. ambient temperature

is the maximum junction of the die,125 °C;

J_MAX

is the ambient temperature;

A

is the thermal resistance junction-to-ambient.

thJA

3.5

3

2.5

2

[W]

D

1.5

P

1

0.5

0

-50 -30 -10 10 30 50 70 90 110 130

[°C]

T

A

16/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Application information

6.2 Enable function

The LD39100xx features an enable function. When the EN voltage is higher than 2 V, the device is ON, and if it is lower than 0.8 V, the device is OFF. In shutdown mode, consumption is lower than 1 µA.

The EN pin does not have an internal pull-up, which means that it cannot be left floating if it is not used.

6.3 Power Good function

Most applications require a flag showing that the output voltage is in the correct range.

The Power Good threshold depends on the adjust voltage. When the adjust is higher than

0.92*V

0.80*V Good pin is at high impedance. If the output voltage is fixed using an external or internal resistor divider, the Power Good threshold is 0.92*V

The use of the Power Good function requires an external pull-up resistor, which must be connected between the PG pin and V is up to 6 mA. The use of a pull-up resistor for PG in the range of 100 k recommended. If the Power Good function is not used, the PG pin must remain floating.

, the Power Good (PG) pin goes to high impedance. If the adjust is below

ADJ

the PG pin goes to low impedance. If the device is functioning well, the Power

ADJ

.

OUT

IN

or V

. The typical current capability of the PG pin

OUT

Ω to 1 MΩ is

Doc ID 15676 Rev 3 17/23

Package mechanical data LD39100XX, LD39100XX12, LD39100XX25

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK specifications, grade definitions and product status are available at: ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

www.st.com.

18/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Package mechanical data

DFN6 (3x3 mm) mechanical data

mm. inch.

Dim.

Min. Typ. Max. Min. Typ. Max.

A0.800.90 1.00 0.031 0.035 0.039

A1 0 0.02 0.05 0 0.001 0.002

A3 0.20 0.008

b 0.23 0.300.38 0.009 0.012 0.015

D2.90 3.00 3.10 0.114 0.118 0.122

D2 2.23 2.38 2.48 0.088 0.094 0.098

E2.90 3.00 3.10 0.114 0.118 0.122

E2 1.50 1.65 1.75 0.059 0.065 0.069

e0.950.037

L0.30 0.40 0.50 0.012 0.016 0.020

7946637A

Doc ID 15676 Rev 3 19/23

Package mechanical data LD39100XX, LD39100XX12, LD39100XX25

Tape & reel QFNxx/DFNxx (3x3) mechanical data

mm. inch.

Dim.

Min. Typ. Max. Min. Typ. Max.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N60 2.362

T18.4 0.724

Ao 3.3 0.130

Bo 3.3 0.130

Ko 1.1 0.043

Po 4 0.157

P 8 0.315

20/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25 Package mechanical data

Figure 35. DFN6 (3 x 3) footprint recommended data

Doc ID 15676 Rev 3 21/23

Revision history LD39100XX, LD39100XX12, LD39100XX25

8 Revision history

Table 8. Document revision history

Date Revision Changes

29-Jul-2009 1 Initial release.

16-Apr-2010 2 Modified Figure 8 on page 10.

11-Oct-2011 3 Document status promoted from preliminary data to datasheet.

22/23 Doc ID 15676 Rev 3

LD39100XX, LD39100XX12, LD39100XX25

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Doc ID 15676 Rev 3 23/23