Datasheet LCX012BL Datasheet (Sony)

Page 1

LCX012BL

3.3cm (1.3-inch) Black-and-White LCD Panel

Description

The LCX012BL is a 3.3cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. Use of three panels in combination with the LCX012BL provides a full-color representation. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines.

The adoption of advanced on-chip black matrix realizes high picture quality without cross talk by incorporating high luminance screen and cross talk free circuit.

This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals.

Using Sony’s timing generator “CXD2442Q” sends timing signal necessary for LCD panel drive by identificating computer supporting VGA automatically, and supports double-speed processed NTSC/PAL.

Features

• The number of active dots: 312,000 (1.3-inch; 3.3cm in diagonal)

• Accepts the computer requirements of VGA platform (640 x 480)

• High optical transmittance: 25% (typ.)

• Supports NTSC/PAL by processing the video signal at double speed

• Built-in cross talk free circuit

• High contrast ratio with normally white mode: 250 (typ.)

• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)

• Up/down and/or right/left inverse display function

Element Structure

• Dots: 644 (H) × 484 (V) = 311,696

• Built-in peripheral driver using polycrystalline silicon super thin film transistors.

Applications

• Liquid crystal data projectors

• Liquid crystal projectors, etc.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96512-ST

Page 2

Block Diagram

Up/Down or Right/Left

PSIG

Inversion

HST

HCK1

Input Signal

Level

Shifter

HCK2

PCG

DWN

ENB

VST

RGT

VCK

H Shift Register (Bidrectional Scanning)

CLR

LCX012BL

SIG2

Vss

SIG1

SIG3

SIG4

SIG5

SIG6

COM

V Shift Register

(Bidrectional Scanning)

Signal Control Circuit

Uniformity Improvement

V Shift Register

(Bidrectional Scanning)

COM PAD

– 2 –

Page 3

LCX012BL

Absolute Maximum Ratings (VSS = 0V)

• H driver supply voltage HVDD –1.0 to +20 V

• V driver supply voltage VVDD –1.0 to +20 V

• Common pad voltage COM –1.0 to +17 V

• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V

RGT

• V shift register input pin voltage VST, VCK, PCG, –1.0 to +17 V CLR, ENB, DWN

• Video signal input pin voltage SIG1, SIG2, SIG3, SIG4, –1.0 to +15 V SIG5, SIG6, PSIG

• Operating temperature Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

Operating Conditions (VSS = 0V)

Supply voltage

HVDD 15.5 ±0.5 V VVDD 15.5 ±0.5 V

Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)

Vin 5.0 ±0.5 V

Pin Description

Pin No.

Symbol Description

PSIG

SIG6

SIG5

SIG4

SIG3

SIG2

SIG1

NC; Open

Uniformity improvement signal

Video signal 6 to panel

Video signal 5 to panel

Video signal 4 to panel

Video signal 3 to panel

Video signal 2 to panel

Video signal 1 to panel

Pin No.

Symbol Description

HCK2

VSS

CLR

ENB

VCK

VST

DWN

Clock pulse for H shift register drive

GND (H, V drivers) Improvement pulse (1) for

uniformity Enable pulse for gate selection

NC; Open Clock pulse for V shift register

drive Start pulse for V shift register

drive Drive direction pulse for V shift

HVDD

RGT

HST

HCK1

Power supply for H driver Driver direction pulse for H shift

drive Clock pulse for H shift register

drive

– 3 –

PCG

VVDD

COM

TEST

Improvement pulse (2) for uniformity

Power supply for V driver

Common voltage of panel

Test; Open

Page 4

LCX012BL

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to VSS with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)

(1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG

Input

1MΩ

(2) HCK1, HCK2

Input

(3) RGT

(4) HST

(5) PCG, VCK

Input

250Ω

1MΩ

2.5kΩ2.5kΩ

1MΩ

250Ω

250Ω250Ω

Signal line

Level conversion circuit

(2-phase input)

Level conversion circuit

(single-phase input)

Level conversion circuit

(single-phase input)

Input

(6) VST, CLR, ENB, DWN

Input

(7) COM

Input

VVDD

250Ω250Ω

1MΩ

2.5kΩ2.5kΩ

1MΩ

Level conversion circuit

(single-phase input)

Level conversion circuit

(single-phase input)

– 4 –

Page 5

Input Signals

1. Input signal voltage conditions (VSS = 0V)

LCX012BL

Item

(Low)

Symbol Min. Typ. Max. Unit

VHIL

–0.5

0.0

0.4

H driver input voltage

(High) (Low)

VHIH VVIL

4.5

–0.5

5.0

0.0

5.5

0.4

V V

V driver input voltage

(High) Video signal center voltage Video signal input range∗1(SIG1 to 6) Common voltage of panel

∗2

Uniformity improvement signal input voltage (PSIG)

∗1

input signal shall be symmetrical to VVC.

∗2

The typical value of the common pad voltage may lower its suitable voltage according to the set

∗3

VVIH VVC Vsig Vcom

Vpsig

4.5

6.8 VVC – 4.5 VVC – 0.5

VVC ± 3.3

5.0

7.0

VVC – 0.4

VVC ± 3.5

5.5

7.2 VVC + 4.5 VVC – 0.3

VVC ± 3.7

V V V V

construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower.

∗3

Input a uniformity improvement signal PSIG in the same polarity with video signals SIG1 to 6 and which is symmetrical to VVC. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below).

Input waveform of uniformity improvement signal PSIG

90%

PSIG

10%

trPSIG tfPSIG

PCG

VVC

Level Conversion Circuit

The LCX012BL has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.

– 5 –

Page 6

LCX012BL

2. Clock timing conditions (Ta = 25°C) (VGA mode: fHCKn = 2.5MHz, fVCK = 15.7kHz) Item Symbol Min. Typ. Max. Unit

HST

HCK

CLR

VST

VCK

Hst rise time Hst fall time Hst data set-up time Hst data hold time Hckn rise time Hckn fall time

∗4

Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Clr rise time Clr fall time Vck rise/fall → Clr fall time Clr pulse width Vst rise time Vst fall time Vst data set-up time Vst data hold time Vck rise time Vck fall time

trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trClr tfClr Tdclr twClr trVst tfVst tdVst thVst trVck tfVck

— — 30 30 —

— –15 –15

—

–100 2400

—

5 — —

—

— 100 100

—

0 — —

2500

— —

15 15

— —

30 170 170

15 100 100 100

2600

100 100

µs

25 100 100

Enb rise time Enb fall time

ENB

Vck rise/fall to Enb rise time Enb pulse width Pcg rise time Pcg fall time

PCG

Pcg rise to Vck rise/fall time Pcg pulse width

∗4

Hckn means Hck1 and Hck2.

trEnb tfEnb toEnb twEnb trPcg tfPcg toVck twPcg

— —

400

2400

—

— 500 900

— —

500

2500

— —

800

1000

100 100 600

2600

30 1000 1100

– 6 –

Page 7

Item Symbol Waveform Conditions

LCX012BL

HST

HCK

Hst rise time

Hst fall time

Hst data set-up time

Hst data hold time

Hckn rise time

Hckn fall time

∗4

Hck1 fall to Hck2 rise time

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

Hst

∗

Hst

Hck1

Hckn

∗

Hck1

90%

10%

trHst tfHst

50%

tdHst thHst

90%

∗4

10%

trHckn tfHckn

50%

90%

50%

90%

10%

50%

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

Hck1 rise to Hck2 fall time

Clr rise time

Clr fall time

to2Hck

trClr

tfClr

CLR

Clr pulse width

Vck rise/fall → Clr fall time

∗5

Definitions: The right-pointing arrow ( ) means +.

twClr

tdClr

The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement.

Hck2

Clr

Vck

Clr

∗5

50%

to2Hck to1Hck

90%

10%

trClr tfClr

50%

twClr

50%

tdClr

50%

90%

10%

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

– 7 –

Page 8

Item Symbol Waveform Conditions

LCX012BL

VST

VCK

Vst rise time

Vst fall time

Vst data set-up time

Vst data hold time

Vck rise time

Vck fall time

Enb rise time

trVst

tfVst

tdVst

thVst

trVck

tfVck

trEnb

Vst

∗

Vst

Vck

90%

10%

trVst tfVst

50%

tdVst thVst

90%

10%

trVckn tfVckn

90%

10%

Enb

90%

10%

50%

90%

10%

90%

ENB

PCG

Enb fall time

Vck rise/fall to Enb rise time

Enb pulse width

tfEnb

tdEnb

twEnb

Pcg rise time trPcg

Pcg fall time tfPcg

Pcg rise to Vck rise/fall time

toVck

Pcg pulse width twPcg

Vck

Enb

∗5

Pcg

Vck

Pcg

∗5

50%

tfEn trEn

90%

10%

toVck

twPcg

50%

twEnb

to3Vck

trPcg tfPcg

50%

tdEnb

90%

10%

– 8 –

Page 9

Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)

1. Horizontal drivers

LCX012BL

Item

Input pin capacitance HCKn

HST

Input pin current HCK1

HCK2 HST

RGT Video signal input pin capacitance Current consumption

2. Vertical drivers

Item

Input pin capacitance VCK

VST

Input pin current VCK PCG, VST, ENB, CLR, DWN

Symbol Min. Typ. Max. Unit Condition CHckn CHst

Csig IH

— —

–500

–1000

–500 –150

— —

10 –250 –300 –150

–25 100

4.0

15 15 — — — —

150

6.0

pF pF

HCK1 = GND

µA

HCK2 = GND

µA

HST = GND

µA

RGT = GND

µA pF

HCKn: HCK1, HCK2 (2.5MHz)

Symbol Min. Typ. Max. Unit Condition CVck CVst

— —

–1000

–150

10 10

–150

–25

15 15 —

—

pF pF

µA

VCK = GND PCG, VST, ENB, CLR,

µA

DWN = GND

Current consumption

—

2.0

3.0

3. Total power consumption of the panel

Item

Total power consumption of the panel (VGA)

Symbol Min. Typ. Max. Unit

PWR

—

100 150

4. Pin input resistance

Item

Symbol Min. Typ. Max. Unit

Pin – VSS input resistance Rpin 0.4 1 — MΩ

5. Uniformity improvement signal

Item

Input pin capacitance for uniformity improvement signal

Symbol Min. Typ. Max. Unit

CPSIGon

—

6.5 nF

7.0

VCK: (15.7kHz)

– 9 –

Page 10

LCX012BL

Electro-optical Characteristics (Ta = 25°C, VGA mode)

Contrast ratio Optical transmittance

V-T characteristics

ON time

Response time

OFF time

Flicker Image retention time Cross talk

Item

V90

V50

V10

25°C 25°C

25°C

60°C

25°C

60°C

25°C

60°C

0°C

25°C

0°C 25°C 60°C 25°C 25°C

Symbol Measurement method Min. Typ. Max. Unit CR T RV90-25 GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 GV50-25 BV50-25

150

1.1

1.2

1.3

1.0

1.1

1.5

1.6

1.7

250

1.5

1.7

1.8

1.4

1.5

1.6

1.9

2.0

2.1

— —

1.8

2.0

2.1

1.7

1.8

1.9

2.2

2.3

2.4

RV50-60 GV50-60 BV50-60 RV10-25 GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ton0 ton25 toff0 toff25 F YT60 CTK

1.5

1.6

2.0

2.1

2.2 — —

— —

5 6 7

— — —

1.8

1.9

2.0

2.4

2.5

2.3

2.4

2.5 36 14

106

–74

—

2.1

2.2

2.3

2.7

2.8

2.6

2.7

2.8 80 40

200

–40

0 5

— %

Reflection Preventive Processing

When a phase substrate which rotates polarization axis is used to adjust to the polarization direction of polarization screen or prism, use the phase substrate with reflection preventive processed on the surface. This prevents characteristic deterioration caused by luminous reflection.

– 10 –

Page 11

<Electro-optical Characteristics Measurement>

Basic measurement conditions (1) Driving voltage HVDD = 15.5V, VVDD = 15.5V  VVC = 7.0V, Vcom = 6.6V (2) Measurement temperature  25°C unless otherwise specified. (3) Measurement point  One point in the center of screen unless otherwise specified. (4) Measurement systems  Two typed of measurement system are used as shown below. (5) Video input signal voltage (Vsig)  Vsig = 7.0 ±V AC [V] (VAC: signal amplitude)

• Measurement system I

LCX012BL

approx. 2000mm

Screen

• Measurement system II

Light receptor lens

Drive Circuit

Luminance Meter

LCD Projector

Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or an equivalent Projection lens: The focal distance 80mm, F1.9 Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500) (× 24, Sensor area: 7mmφ) Polarizer: Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T or equivalent

Optical fiber

LCD panel

Light Source

Measurement Equipment

Light Detector

Measurement Equipment

1. Contrast Ratio

Contrast Ratio (CR) is given by the following formula (1).

CR =

L (White) L (Black)

...

(1)

L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the center of the screen at VAC = 4.5V. Both luminosities are measured by System Ι.

– 11 –

Page 12

2. Optical Transmittance

Optical Transmittance (T) is given by the following formula (2).

LCX012BL

T = x 100 [%]

White luminance

...

(2)

Luminance of light source

"White luminance" means the maximum luminance at the input signal amplitude VAC = 0.5V on Mesurement System II.

3. V-T Characteristics

V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are

measured by System II. V90, V50, and V10 correspond to the each voltage which defines 90%, 50%, and 10%

of transmittance respectively.

Transmittance [%]

90 V50 V10

VAC – Signal amplitude [V]

4. Respons Time

Response time ton and toff are defined by

Input signal voltage (Waveform applied to the measured pixels)

the formula (5) and (6) respectively.

ton = t1 – tON toff = t2 – tOFF

...

(5)

(6)

t1: time which gives 10% transmittance of

the panel.

t2: time which gives 90% transmittance of

the panel.

The relationships between t1, t2, tON and tOFF are shown in the right figure.

4.5V

7.0V

Optical transmittance output waveform

0.5V

100%

90%

10%

tON t1

ton

tOFF t2

toff

– 12 –

Page 13

LCX012BL

5. Flicker

Flicker (F) is given by the formula (7). DC and AC (NTSC VGA: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗mode are measured by a DC voltmeter and a spectrum analizer in System II.

F [dB] = 20log { }

AC component

DC component

...

(7)

∗

Each input signal condition for gray raster mode is given by Vsig = 7.0 ± V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics.

6 Image Retention Time

Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale

of Vsig = 7.0 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure the time till the residual image becomes indistinct.

∗

Monoscope signal conditions: Vsig = 7.0 ± 4.5 or ±2.0 [V] (shown in the right figure) Vcom = 6.6V

4.5V

2.0V

7.0V

Vsig waveform

Black level

White level

2.0V

4.5V

7. Cross Talk

Cross talk is determined by the luminance differences between adjacent areas represented Wi' and Wi (i =

1 to 4) around black window (Vsig = 4.5V/1V)

W1’W1

W2 W2’

W3’W3

W4’

Cross talk value CTK = × 100 [%]

Wi' – Wi

– 13 –

Page 14

Viewing angle characteristics (Typical Value)

LCX012BL

Phi

180

270

Marking

30 7010 50

θ0°

Theta

φ90°

φ180°

φ270°

– 14 –

φ0°

Measurement method

Page 15

Optical transmittance of LCD panel (Typical Value)

Trans. [%]

LCX012BL

400 500 600 700

Wavelength [nm]

Measurement method: Measurement system II

– 15 –

Page 16

1. Dot Arrangement

The dots are arranged in a stripe. The shaded area is used for the dark border around the display.

Gate SW Gate SW Gate SW

LCX012BL

1 dot

Photo-shielding

5 dots

Active area

644 dots

654 dots

484 dots

486 dots

1 dot

5 dots

– 16 –

Page 17

LCX012BL

2. LCD Panel Operations

[Description of basic operations]

The basic operations of the LCD panel are shown below based on the VGA mode.

• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 484 gate lines sequentially in every horizontal scanning period. Two lines of horizontal electrodes are sequentially selected in NTSC/PAL mode.

• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 644 signal electrodes sequentially in a single horizontal scanning period.

• Vertical and horizontal shift registers address one pixel, and then Thin film Transistors (TFTs; two TFTs) turn on to apply a video signal to the dot. The same procedures lead to the entire 484 × 644 dots to display a picture in a single vertical scanning period.

• To change the combination of the horizontal electrode in NTSC/PAL mode, the phase of VCK need to be inverted. Normally, switching every field maximizes vertical resolution.

• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be grounded when not in use.

• The video signal shall be input with 1H-inverted system.

• Timing diagrams of the vertical for VGA mode and NTSC/PAL mode and the horizontal display cycle are

shown below:

(1) Vertical display cycle (VGA)

VST (DWN = High level)

VST (DWN = Low level)

VCK

1 2 480

Vertical display cycle 480H

(2) Horizontal display cycle

HST

HCK1

HCK2

123456

108

109

Horizontal display cycle

– 17 –

Page 18

LCX012BL

[Description of operating mode]

The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems.

• Right/left inverse mode

• Up/down inverse mode

These modes are controlled by two signals (RGT and DWN). The setting mode is shown below.

RGT

HLRight scan

Left scan

Mode

DWN

HLDown scan

Up scan

Mode

The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin block upside.

• To improve uniformity, the analog signals PSIG shall be input by synchronizing with SIG1 to SIG6.

• When the up-scan mode (DWN = Low level) is set, the phase of VST shall be inverted

3. 6-dot Simultaneous Sampling and Dot-inverted Drive

Horizontal driver samples SIG1 to SIG6 signal simultaneously. Which requires the phase matching between SIG1 to SIG6 signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. The block diagram of the delaying procedure using sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between SIG1 to SIG6 signals.

SIG1

S / H

AC Amp

SIG1

SIG2

SIG3

SIG4

SIG5

SIG6

CK1

S / H

CK2

S / H

CK3

S / H

CK4

S / H

CK5

S / H

CK6

AC Amp

<Phase relationship of delaying sample-and-hold pulses> (right scan)

HCKn

CK1 CK2

CK3 CK4 CK5

SIG2

SIG3

SIG4

SIG5

SIG6

LCX012BL

CK6

– 18 –

Page 19

Display System Block Diagram

An example of display system is shown below.

R G B

RGB Driver CXA1853Q

FRP

Discrete Buff.

S/H

CXA2504N

LCX012BL

HD VD

C.SYNC

CXD2442Q

HCK, VCK

S/H

CXA2504N

S/H

CXA2504N

LCX012BL

– 19 –

Page 20

Notes on Handling

(1) Static charge prevention

Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionozed air to discharge the panels.

(2) Protection from dust and dirt

a) Operate in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet.

Peel off the protective sheet carefully not to damage the panel.

c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room

wiper with isopropyl alcohol. Be careful not to leave stain on the surface.

d) Use ionized air to blow off dust at a panel.

LCX012BL

(3) Other handling precautions

a) Do not twist or bend the flexible PC board especially at the connecting region because the board is

easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel

damages. g) Minimum bent radius rating for flexible substrates is 1mm. h) Panel screw torque should not exceed 3kg · cm.

– 20 –

Page 21

Package Outline Unit: mm

25.0 ± 0.15

LCX012BL

3.7 ± 0.1

Thickness of the connector 0.3 ± 0.05

1.8 ± 0.1

4-R2.5

2.1 ± 0.05

PIN1

Active Area

(26.65)

30.0 ± 0.1

38.0 ± 0.15

P 1.0 × 23 = 23.0 ± 0.1

1.0 ± 0.15

0.6 ± 0.05

3-φ2.3 ± 0.05 C0.8

(20.03)

21.0 ± 0.25

19.0 ± 0.25

4.0 ± 0.1

37.0 ± 0.1

2.5 ± 0.1

(62.0)

104.0 ± 1.4

42.0 ± 0.15

Incident

light

φ2.1 ± 0.05

PIN24

0.5 ± 0.15

4.0 ± 0.4

Polarizing Axis

2 3

Description

F P C

Molding material

Outside frame

electrode (enlarged)

The rotation angle of the active area relative to H and V is ± 1°.

– 21 –

Reinforcing board

4 5

Reinforcing material 6 7

Polarizing film

Cover

weight 7.5g