Page 1
3.4cm (1.35-inch) Color LCD Panel
Description
The LCX007AK is a 3.4cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral driving
circuit, and it provides a full-color representation is
possible.
This panel provides a wide aspect ratio of 16:9,
such as those represented in HD. The built-in sideblack function also allows an aspect ratio of 4:3 in
the NTSC/PAL mode.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing
system and control signals.
LCX007BK
Features
• The number of active dots: 512,880 (1.35-inch; 3.4cm in diagonal)
• Horizontal resolution: 400 TV lines
• High optical transmittance: 4.0% (typ.)
• High contrast ratio with normally white mode: 190 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• NTSC/NTSC-WIDE/HD (band: 20MHz) mode selectable
(PAL/PAL-WIDE mode also available through conversion of scanned dot numbers by an external IC)
• Up/down and/or right/left inverse display function
• Side-black function
• 16:9 and 4:3 aspect-ratio switching function
• Full-color display
Element Structure
• Dots
16:9 display: 1068.5 (H) × 480 (V) = 512,880
4:3 display: 799.5 (H) × 480 (V) = 383,760
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.
Applications
Liquid crystal projectors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95733A64-ST
Page 2
Block Diagram
1
SID
8
HST
10
HCK1
11
HCK2
6
WID
RGT
7 16
VST
VCK
1514
PCG
17
DWN
13
ENB
12
CLR
LCX007BK
DD
DD
VV
HV
18
5
SS
V
SIG1(G)
9
2
SIG2(R)
3
SIG3(B)
19
4
COM
Input Signal
Level Shifter
4 : 3/16 : 9
Control Circuit
Up/Down or Right/Left Inversion
V Shift Register
(Bidirectional Scanning)
H Shift Register (Bidirectional Scanning)
V Shift Register
(Bidirectional Scanning)
COM
Pad
Side Black
Control Circuit
– 2 –
Page 3
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage HVDD –1.0 to +20 V
• V driver supply voltage VVDD –1.0 to +20 V
• Common pad voltage COM –1.0 to +17 V
• H shift register input pin voltage HST, HCK1, HCK2 –1.0 to +17 V
RGT, WID
• V shift register input pin voltage VST, VCK, PCG –1.0 to +17 V
CLR, ENB, DWN
• Video signal input pin voltage SIG1, SIG2, SIG3, SID –1.0 to +15 V
• Operating temperature Topr –10 to +70 °C
• Storage temperature Tstg –30 to +85 °C
Operating Conditions (VSS = 0V)
• Supply voltage
HVDD 15.7 V
VVDD 15.7 V
+0.3
–0.4
+0.3
–0.4
• Input pulse voltage (Vp-p of all input pins except video signal and side black signal input pins)
Vin 5.0 ± 0.5 V
LCX007BK
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
Symbol Description
SID
SIG1 (G)
SIG2 (R)
SIG3 (B)
HVDD
WID
RGT
HST
Side black signal for 4:3 display
Video signal (G) to panel
Video signal (R) to panel
Video signal (B) to panel
Power supply for H driver
Aspect-ratio switching
(H: 16:9, L: 4:3)
Drive direction pulse for H shift
register (H: normal, L: reverse)
Start pulse for H shift register
drive
Pin
No.
11
12
13
14
15
16
17
18
Symbol Description
HCK2
CLR
ENB
VCK
PCG
VST
DWN
VVDD
Clock pulse for H shift register
drive
Improvement pulse (1) for
uniformity
Enable pulse for gate selection
Clock pulse for V shift register
drive
Improvement pulse (2) for
uniformity
Start pulse for V shift register
drive
Drive direction pulse for V shift
register (H: normal, L: reverse)
Power supply for V driver
9
10
Vss
HCK1
GND (H, V drivers)
Clock pulse for H shift register
drive
– 3 –
19
20
COM
TEST
Common voltage of panel
Test; Open
Page 4
LCX007BK
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) SIG1, SIG2, SIG3, SID
HV
DD
Input
1MΩ
(2) HCK1, HCK2
(3) RGT, WID
(4) HST
(5) PCG, VCK
Input
Input
Input
HV
DD
250Ω
250Ω
HV
HV
VV
DD
DD
DD
1MΩ
1MΩ
2.5kΩ2.5kΩ
1MΩ
1MΩ
250Ω
Level conversion circuit
250Ω
250Ω250Ω
(2-phase input)
Level conversion circuit
(single-phase input)
Level conversion circuit
(single-phase input)
Signal line
Input
(6) VST, CLR, ENB, DWN
Input
(7) COM
Input
VV
VVDD
DD
1MΩ
1MΩ
250Ω250Ω
Level conversion circuit
(single-phase input)
2.5kΩ2.5kΩ
Level conversion circuit
(single-phase input)
1MΩ
– 4 –
LC
Page 5
Input Signals
1. Input signal voltage conditions (VSS = 0V)
LCX007BK
Item
H driver input voltage
WID, RGT, HST, HCK1, HCK2
V driver input voltage
CLR, ENB, VCK, PCG, VST, DWN
(Low)
(High)
(Low)
(High)
Video signal center voltage
Video signal input range
Common voltage of panel
∗1
Video input signal shall be symmetrical to VVC.
∗2
Common voltage of the panel shall be adjusted to VVC – 0.4V.
∗1
∗2
Symbol Min. Typ. Max. Unit
VHIL
VHIH
VVIL
VVIH
VVC
Vsig
Vcom
–0.5
4.5
–0.5
4.5
6.5
VVC – 4.5
VVC – 0.5
0.0
5.0
0.0
5.0
7.0
—
VVC – 0.4
0.3
5.5
0.3
5.5
7.2
VVC + 4.5
VVC – 0.3
V
V
V
V
V
V
V
Level Conversion Circuit
The LCX007BK has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
– 5 –
Page 6
LCX007BK
2. Clock timing conditions (Ta = 25°C) (fHCKn = 7.5MHz, fVCK = 15.7kHz)
Item Symbol Min. Typ. Max. Unit
HST
HCK
CLR
VST
VCK
Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn∗3rise time
Hckn∗3fall time
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Clr rise time
Clr fall time
Clr pulse width
Vck rise/fall to Clr fall time
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vck rise time
Vck fall time
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trClr
tfClr
twClr
tdClr
trVst
tfVst
tdVst
thVst
trVck
tfVck
—
—
20
–40
—
—
–15
–15
—
—
3000
–50
—
—
–25
5
—
—
—
—
67
0
—
—
0
0
—
—
3100
0
—
—
15
15
—
—
30
30
100
40
30
30
15
ns
15
100
100
3200
50
100
100
25
µs
25
100
100
Enb rise time
Enb fall time
ENB
Vck rise/fall to Enb rise time
Enb pulse width
Pcg rise time
Pcg fall time
PCG
Pcg fall to Vck rise/fall time
Pcg pulse width
∗3
Hckn means Hck1 and Hck2.
trEnb
tfEnb
tdEnb
twEnb
trPcg
tfPcg
toVck
twPcg
—
—
350
3450
—
—
650
1150
—
—
400
3500
—
—
700
1200
100
100
450
3550
20
20
750
1250
ns
– 6 –
Page 7
<Horizontal Shift Register Driving Waveform>
Item Symbol Waveform Conditions
LCX007BK
HST
HCK
Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn∗3rise time
Hckn∗3fall time
Hck1 fall to Hck2 rise
time
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
Hst
∗4
Hst
Hck1
Hckn
∗4
Hck1
90%
10%
trHst tfHst
50%
50%
tdHst thHst
90%
∗3
10%
trHckn tfHckn
50%
90%
50%
50%
90%
10%
10%
50%
O Hckn
∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
O Hckn
∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
O Hckn
∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
CLR
Hck1 rise to Hck2 fall
time
Clr rise time
Clr fall time
Clr pulse width
Vck rise/fall to Clr fall
time
to2Hck
trClr
tfClr
twClr
tdClr
Hck2
Clr
Vck
Clr
∗4
50%
to2Hck to1Hck
90%
10%
trClr tfClr
50%
50%
twClr
50%
90%
50%
tdClr
10%
O Hckn
∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
– 7 –
Page 8
<Vertical Shift Register Driving Waveform>
Item Symbol Waveform Conditions
LCX007BK
VST
VCK
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vck rise time
Vck fall time
Enb rise time
Enb fall time
trVst
tfVst
tdVst
thVst
trVck
tfVck
trEnb
tfEnb
Vst
∗4
Vst
Vck
Vck
90%
10%
trVst tfVst
50%
50%
tdVst thVst
90%
10%
trVckn tfVckn
90%
10%
Enb
tfEn trEn
90%
50%
10%
10%
50%
90%
10%
90%
ENB
Vck rise/fall to Enb rise
time
Enb pulse width
tdEnb
twEnb
Vck
Enb
Pcg rise time trPcg
Vck
Pcg fall time tfPcg
PCG
Pcg fall to Vck rise/fall
time
toVck
Pcg
50%
Pcg pulse width twPcg
∗4
Definitions: The right-pointing arrow ( ) means +.
The left-pointing arrow ( ) means –.
The black dot at an arrow ( ) indicates the start of measurement.
50%
twEnb
50%
twPcg toVck
tdEnb
50%
50%
50%
∗4
∗4
– 8 –
Page 9
Electrical Characteristics (Ta = 25°C, HVDD = 15.7V, VVDD = 15.7V)
1. Horizontal drivers
LCX007BK
Item
Input pin capacitance
HCKn
HST
Input pin current HCK1
HCK2
HST
WID, RGT
Video signal input pin capacitance
Current consumption
2. Vertical drivers
Item
Input pin capacitance VCK
VST
Input pin current VCK
PCG, VST, EN, CLR, DWN
Symbol Min. Typ. Max. Unit Condition
CHckn
CHst
Csig
IH
—
—
–500
–1000
–500
–150
—
—
7
7
–120
–450
–160
–30
250
7.5
10
10
—
—
—
—
—
10
pF
pF
HCK1 = GND
µA
HCK2 = GND
µA
HST = GND
µA
WID, RGT = GND
µA
pF
HCKn: HCK1, HCK2 (7.5MHz)
mA
Symbol Min. Typ. Max. Unit Condition
CVck
CVst
—
—
–1000
–150
7
7
–160
–30
10
10
—
—
pF
pF
µA
VCK = GND
µA
PCG, VST, EN, CLR, DWN = GND
Current consumption
IV
—
1.5
4
3. Total power consumption of the panel
Item
Total power consumption of
the panel (NTSC)
Symbol Min. Typ. Max. Unit
PWR — 150 250 mW
4. Pin input resistance
Item
Symbol Min. Typ. Max. Unit
Pin-VSS input resistance Rpin 0.4 1 — MΩ
5. Side signal input pin capacitance
Item
Side signal input pin
capacitance
Symbol Min. Typ. Max. Unit
CSIDon
81012nF
mA
VCK: (15.7kHz)
– 9 –
Page 10
LCX007BK
Electro-optical Characteristics (Ta = 25°C, NTSC mode)
Contrast ratio
Optical transmittance
Chromaticity
V-T
characteristics
Item
R
G
B
V90
V50
V10
25°C
60°C
X
Y
X
Y
X
Y
25°C
60°C
25°C
60°C
25°C
60°C
Symbol
CR25
CR60
T
Rx
Ry
Gx
Gy
Bx
By
V90-25
V90-60
V50-25
V50-60
V10-25
V10-60
Measurement
method
1
2
3
4
Min. Typ. Max. Unit
60
190
—
—
100
3.3
0.560
0.300
0.275
0.541
0.120
0.040
1.4
1.2
1.8
1.6
2.4
2.2
190
4.0
0.622
0.347
0.302
0.601
0.144
0.087
1.7
1.5
2.1
1.9
2.7
2.5
—
—
0.670
0.390
0.347
0.650
0.187
0.122
2.0
1.8
2.4
2.2
3.0
2.8
%
CIE
standards
V
Half tone color reproduction
range
ON time
Response time
OFF time
Flicker
Image retention time
R vs. G
B vs. G
0°C
25°C
0°C
25°C
60°C
25°C
V50RG
V50BG
ton0
ton25
toff0
toff25
F
YT60
—
5
–0.10
—
0.15
—
—
6
—
—
7
8
—
—
50
15
52
16
–50
—
–0.25
0.50
100
40
150
60
–30
5
V
ms
dB
s
– 10 –
Page 11
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.7V, VVDD = 15.7V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V] (VAC: signal amplitude)
• Measurement system Ι
LCX007BK
Back Light
3.5mm
• Measurement system ΙΙ
Light receptor lens
Drive Circuit
LCD panel
Light
Source
Luminance
Meter
Back light: color temperature 6500 ± 700K (25°C)
Polarizer: POLATECHNO Co., Ltd. THC-13U (Luminance meter side)
Optical fiber
LCD panel
Measurement
Equipment
Light Detector
Measurement
Equipment
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
CR =
L (Black)
... (1)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V.
Both luminosities are measured by System I.
– 11 –
Page 12
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
LCX007BK
T =
Luminance of Back Light
L (White)
× 100 [%] ... (2)
L (White) is the same expression as defined in the 'Contrast Ratio' section.
3. Chromaticity
Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses
Chromaticity of x and y on the CIE standards here.
Signal amplitudes (VAC) supplied to each input
R input G input B input
R
G
0.5
4.5
4.5
0.5
4.5
4.5
Raster
B
4.5
4.5
0.5
(Unit: V)
4. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
90
measured by System II. V90, V50 and V10 correspond to
the each voltage which defines 90%, 50% and 10% of
50
transmittance respectively.
Transmittance [%]
10
5. Half Tone Color Reproduction Range
Half tone color reproduction range of the LCD panels is
characterized by the defferences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II. System
II defines signal voltages of each R, G, B raster modes
which corresponds to 50% of transmittance, V50R, V50G
and V50B respectively. V50RG and V50BG, the voltage
differences between V50R and V50G, V50B and V50G, are
simply given by the following formula (3) and (4)
respectively.
V50RG = V50R–V50G ... (3)
V50BG = V50B–V50G ... (4)
– 12 –
100
50
R raster
Transmittance [%]
0
90 V50 V10
V
VAC – Signal amplitude [V]
V50RG
V50BG
50R V50B
V
V50G
VAC – Signal amplitude [V]
G raster
B raster
Page 13
LCX007BK
6. Response Time
Response time ‘ton’ and ‘toff’ are defined by
the formula (5) and (6) respectively.
ton = t1 – tON ... (5)
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
4.5V
7.0V
0V
Input signal voltage (waveform applied to the measured pixels)
0.5V
Light transmission output waveform
100%
90%
10%
0%
tON t1
ton
tOFF t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster∗mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
F [dB] = 20 log
AC component
{
DC component
... (7)
}
∗
Each input signal condition for gray raster mode is given by
Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T characteristics.
8. Image Retention Time
Image Retention time is given by following procedures.
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Hold VAC that maximizes image retention judging by sight. Measure the
time till the residual image becomes indistinct.
∗
Monoscope signal conditions:
Vsig = 7.0 ± 4.5 or ±2.0 [V]
(shown in the right figure)
Vcom = 6.6V
4.5V
2.0V
7.0V
Black level
White level
2.0V
4.5V
– 13 –
0V
Vsig waveform
Page 14
Optical transmittance of LCD panel (Typical value)
20
15
10
Trans. [%]
5
LCX007BK
0
400 500 600 700
Wavelength [nm]
Measurement method: Measurement system ΙΙ
– 14 –
Page 15
Viewing angle characteristics (Typical value)
CR = 5
10
LCX007BK
90
180
20
50
100
200
150
270
10
30 50 70
Phi
0
Theta
φ180°
– 15 –
Marking
X
φ270°
θ0°
Z
θ
φ
φ90°
Y
φ0°
Measurment method
Page 16
LCX007BK
The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display.
The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively.
Description of Operation
1. Dot Arrangement (1) (16:9 display)
ODD = 13 dots
EVEN = 13 dots
ODD = 1094 dots
EVEN = 1095 dots
ODD = 1069 dots
EVEN = 1068 dots
ODD = 13 dots
EVEN = 14 dots
DR4
DR3
DR2
DR1
357
356
314
313
312
311
48
47
46
45
44
2
1
DL4
DL3
DL2
DL1
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
G BR
3 dots
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
R R R R R R R R R R R R
GBR
GBR
B
G
R
GBR
GBR
B
G
B
B
GR
GR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
R R R R R R
GBR
GBR
B
G
R
GBR
GBR
B
G
R
GBR
GBR
B
G
R
GBR
GBR
B
G
R
G BR
GBR
123
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
R R R R R R R R R R R R
B
G
R
B
G
B
G
B
G
B
G
B
G
B
G
R R R R R R
B
G
R
B
G
R
B
G
R
B
G
R
4
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
480 dots
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
479
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
480
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
3 dots
– 16 –
Page 17
B
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
BR
G
GBR
B
R
G
GBR
GB
B
G
GBR
GBR
B
G
R R R R R R R R R R R R
GBR
GBR
B
G
R
GBR
GBR
B
G
B
B
GR
GR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
GBR
GBR
B
G
R R R R R R
GBR
GBR
B
G
R
GBR
GBR
B
G
R
GBR
GBR
B
G
R
GBR
GBR
B
G
R
G BR
GBR
123
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
R R R R R R R R R R R R
B
G
R
B
G
B
G
B
G
B
G
B
G
B
G
R R R R R R
B
G
R
B
G
R
B
G
R
B
G
R
4
ODD = 13 dots
EVEN = 13 dots
ODD = 135 dots
EVEN = 134 dots
ODD = 799 dots
EVEN = 800 dots
ODD = 1094 dots
EVEN = 1095 dots
Side Black 4:3 Area Side Black
ODD = 135 dots
EVEN = 134 dots
ODD = 13 dots
EVEN = 14 dots
DR4
DR3
DR2
DR1
357
356
314
313
312
311
48
47
46
45
44
GATE SW GATE SW
2
GATE SW
1
GATE SW
DL4
GATE SW
DL3
GATE SW
DL2
GATE SW
DL1
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
GATE SW
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
G BR
3 dots
Dot Arrangement (2) (4:3 display)
The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display.
The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively.
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
480 dots
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
479
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
480
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R R R R R R R
GBR
B
G
R
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
GBR
B
G
R R R R R R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
B
G
R
GBR
3 dots
LCX007BK
– 17 –
Page 18
LCX007BK
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the wide-display mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 480 gate lines sequentially in every horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then turn on Thin Film Transistors (TFTs; two
TFTs) to apply a video signal to the dot. The same procedures lead to the entire 480 × 1068.5 dots to display
a picture in a single vertical scanning period.
• The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line are
positioned with 1.5-dot offset against those of the adjacent horizontal line. Horizontal Start Pulse (HST) is
generated with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold
(S/H) pulses follow the same 1.5-bit offset scheme.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be
grounded when not in use.
• The video signal shall be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal display cycle are shown below:
(1) Vertical display cycle
VD
VST
VCK
1 2 480
Vertical display cycle 480H
(2) Horizontal display cycle (16:9)
BLK
HST
HCK1
HCK2
123456
Horizontal display cycle
356
357
(3) Horizontal display cycle (4:3)
BLK
HST
HCK1
HCK2
123456
267
268
Horizontal display cycle
– 18 –
Page 19
LCX007BK
[Description of operating mode]
The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
• 4:3 display mode with side-black display
These modes are controlled by three signals (RGT, DWN, and WID). The setting mode is shown below:
WID
RGT Mode DWN
H
H
16:9 right scan
H
L
16:9 left scan
L
H
4:3 right scan
L
L
4:3 left scan
H
L
Down scan
Up scan
Mode
The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin
block upside.
• The analog signal (SID) to display side-black shall be input by 1H inversion synchronized with the signal.
3. 3-dot Simultaneous Sampling
Horizontal driver samples SIG1, SIG2 and SIG3 signal simultaneously, which requires the phase matching
between SIG1, SIG2, and SIG3 signals to prevent horizontal resolution from deteriorating. Thus phase
matching between each signal is required using an external signal delaying circuit before applying video
signal to the LCD panel.
The block diagram of the delaying procedure using sample-and-hold method is as follows.
The LCX007 has the right/left inverse function. The following phase relationship diagram indicates the phase
setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be
inverted between SIG2 and SIG3 signals.
3
SIG2
SIG1
SIG3
S/H S/H AC Amp
CK2
S/H
CK1
CK3
S/H AC Amp
CK3
S/H AC Amp
CK3
SIG2
SIG1
2
LCX007BK
4
SIG3
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK2
CK1
CK3
– 19 –
Page 20
Example of Color Filter Spectrum (Reference)
100
80
LCX007BK
Color Filter Spectrum
R
G
60
Transmittance [%]
40
20
B
0
400 500 600 700
Wavelength [nm]
– 20 –
Page 21
Display System Block Diagram
An example of display system is shown below.
LCX007BK
∗
The SIG1, 2, 3 and
H SYNC signals with
double-speed processing
shall be applied to those
pins in the NTSC/PAL
modes.
SIG2
SIG1
SIG3
HSYNC
VSYNC
HST
HCK1
HCK2
VST
VCK
PCG
ENB
SID
SIG2
SIG1
SIG3
COM
LCD Panel
LCX007BK
∗
∗
∗
∗
RGB Driver
CXA1819Q
FRP SH
TG
CXD2412AQ
CLR
WID
RGT
DWN
– 21 –
Page 22
Reliability test conditions
Items Test conditions Time Criterion
LCX007BK
High temperature
operation
High temperature storage
High temperature & high
humidity storage
Temperature cycle
Vibration
Ta = 70°C
HVDD = 15.7V
VVDD = 15.7V
Ta = 85°C
Ta = 40°C
95% RH
Ta = –30 to +85°C
X, Y, Z, 1.5mm
10 to 55Hz (1min. reciprocation)
250h
250h
250h
10cy
20min. for each
direction
Panel appearance
and performance
after those tests must
conform with the
standards.
– 22 –
Page 23
Important
(1) Anti-reflection coating
Use anti-reflection coating when using a phase-shifting plate on a light egress side of the LCD to align a
polarization axis with those of a polarization screen or a prism.
(2) Direction of incident light
Allow incident light to hit upon an opposite side of a mark-indicated surface.
Direction of incidence
LCX007BK
Marking side
(3) Polarizer
This LCD is attached with a polarizer on a light egress side. A suitable heat-dissipation method shall be
incorporated to suppress optical degradation of a polarizer.
(4) Light source
• Use visible light (wavelength λ = 400 to 780nm) as a light source. Do not use a light source containing
infrared or ultraviolet components.
• Suppress leakage light (reflection light) into a backside of a panel to sufficiently weak level or shut it out
completely.
– 23 –
Page 24
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Handle in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet.
Peel off the protective sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
LCX007BK
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in
panel damages.
g) Minimum bent radius rating for flexible substrate is 1mm.
h) Panel screw torque should not exceed 3kg · cm.
– 24 –
Page 25
Package Outline Unit: mm
LCX007BK
3.4 ± 0.1
2-R0.5
21.0 ± 0.15
Active Area
Thickness of the connector 0.3 ± 0.05
9.75 ± 1.5
1.8 ± 0.1
4
(40.5)
1
(42.5)
2-φ3.5
2
76.5 ± 1.3
Incident
34.0 ± 0.2
36.0 ± 0.15
light
7
31.4 ± 0.2
4.55 ± 0.1
3
5
6
Polarizing
Axis
30.75 ± 0.2
0
– 0.1
PIN1
(29.9)
20.25 ± 0.25
40.5 ± 0.15
(16.8)
13.6 ± 0.25
1.5 ± 0.15
P 1.0 × 19 = 19.0 ± 0.1
0.6 ± 0.05
1.0 ± 0.15
PIN20
φ2.5
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
0.5 ± 0.15
4.0 ± 0.3
No
1
2
3
4
5
6
7
Description
F P C
Molding material
Outside frame
Reinforcing board
Reinforcing material
Polarizing film
Cover
weight 7g
2.0 ± 0.1
– 25 –
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