Datasheet LCDA05TE, LCDA05TB, LCDA24TE, LCDA24TB, LCDA12TE Datasheet (Semtech Corporation)

PROTECTION PRODUCTS

LCDA05 THRU LCDA24

Low Capacitance TVS Diode Array

For High-Speed Data Interfaces

Description

The LCDA series of TVS arrays are designed to protect
sensitive electronics from damage or latch-up due to
ESD and other voltage-induced transient events. Each
device will protect two high-speed lines. They are
available with operating voltages of 5V, 12V, 15V and
24V. They are bidirectional devices and may be used on
lines where the signal polarities are above and below
ground.

TVS diodes are solid-state devices designed specifically
for transient suppression. They offer desirable charac­teristics for board level protection including fast re­sponse time, low operating and clamping voltage and
no device degradation. The LCDA series devices
feature low capacitance compensation diodes in series
with standard TVS diodes to provide an integrated, low
capacitance solution for use on high-speed interfaces.

The LCDA series devices may be used to meet the
immunity requirements of IEC 61000-4-2, level 4.

Features

u Transient protection for high-speed data lines to

IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (tp = 5/50ns)
IEC 61000-4-5 (Lightning) 24A (tp = 8/20µs)

u Protects two I/O lines
u Low capacitance for high-speed data lines
u Working voltages: 5V, 12V, 15V and 24V
u Low leakage current
u Low operating and clamping voltages
u Solid-state silicon avalanche technology

Mechanical Characteristics

u JEDEC SO-8 (MS-012AA) small outline package
u Molding compound flammability rating: UL 94V-0
u Marking : Part Number, Logo, Date Code
u Packaging : Tape and Reel per EIA 481

Applications

u High-Speed Data Lines
u Microprocessor Based Equipment
u Universal Serial Bus (USB) Port Protection
u Notebooks, Desktops, & Servers
u Instrumentation
u LAN/WAN Equipment
u Peripherals

Circuit Diagram (Each Line Pair) Schematic & PIN Configuration

1

2

3

45

SO-8 (Top View)

Revision 9/2000

1

8

7

6

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Absolute Maximum Rating

LCDA05 THRU LCDA24

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Electrical Characteristics

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PROTECTION PRODUCTS

Electrical Characteristics (continued)

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LCDA05 THRU LCDA24

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ã 2000 Semtech Corp.

3

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LCDA05 THRU LCDA24

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Typical Characteristics

Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve

10

(kW)

PP

1

0.1

Peak Pulse Power - P

0.01

0.1 1 10 100 1000

Pulse Duration - tp (µs)

Pulse Waveform

110
100

90
80
70

PP

60
50
40

Percent of I

30
20
10

0

0 5 10 15 20 25 30

-t

e

Time (µs)

td = IPP/2

Waveform

Parameters:

tr = 8µs

td = 20µs

110
100

90

PP

80
70
60
50
40
30

% of Rated Power or I

20
10

0

0 25 50 75 100 125 150

Ambient Temperature - T

A

(oC)

ESD Pulse Waveform (Per IEC 61000-4-2)

ESD Discharge Parameters Per IEC 61000-4-2

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Applications Information

Device Connection for Protection of Two High-Speed
Data Lines

LCDA05 THRU LCDA24

LCDA Connection Diagram

The LCDAxx is designed to protect up to two high-speed
data lines. The LCDAxx utilizes a low capacitance
compensation diode in series with, but in opposite
polarity to a TVS diode in each line. The resulting
capacitance is less than 5pF per line. Each line will
only suppress transient events in one polarity. There­fore, to achieve protection in both positive and nega­tive polarity, a second TVS/rectifier pair is connected in
anti-parallel to the first. Pins 1, 2, 7, and 8 are used to
protect one data line. Pins 3, 4, 5, and 6 are used to
protect the second data line.
The device is connected as follows:

l Pins 1 & 2 are tied together and pins 7 & 8 are tied

together providing the protection circuit for one I/O
line. Pins 3 & 4 are tied together and pins 5 & 6
are tied together providing the protection circuit for
the second I/O line. Since the device is electrically
symmetrical, either side of the connected pairs
may be used to protect the lines. The other side of
the pair is used to make the ground connection.
The ground connections should be made directly to
the ground plane for best results. The path length
is kept as short as possible to reduce the effects
of parasitic inductance in the board traces.

Circuit Board Layout Recommendations for Suppres­sion of ESD.

Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:

l Place the TVS near the input terminals or connec-

tors to restrict transient coupling.

l Minimize the path length between the TVS and the

protected line.

l Minimize all conductive loops including power and

ground loops.

l The ESD transient return path to ground should be

kept as short as possible.

l Never run critical signals near board edges.
l Use ground planes whenever possible.

I/O 1

I/O 2

1

2

3

45

8

I/O 1

7

6

I/O 2

I/O Line Protection

Connection Options

To Protected

Device

Line 1
In/Out

Line 2
Ground

In/Out

1

2

3

45

From Connector

To Protected

Device

1

2

3

Line 2

45

In/Out

8

7

6

8Line 1

7

6

Line 1
Ground

Line 2
In/Out

Ground

ã 2000 Semtech Corp.

From Connector

5

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Outline Drawing - SO-8

LCDA05 THRU LCDA24

Land Pattern - SO-8

6ã 2000 Semtech Corp.

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Ordering Information

LCDA05 THRU LCDA24

traP

rebmuN

BT.50ADCLV5005hcnI7

ET.50ADCLV5005,2hcnI31

BT.21ADCLV21005hcnI7

ET.21ADCLV21005,2hcnI31

BT51ADCLV51005hcnI7

ET.51ADCLV51005,2hcnI31

BT.42ADCLV42005hcnI7

ET.42ADCLV42005,2hcnI31

Note:
(1) No suffix indicates tube pack.

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Contact Information

ã 2000 Semtech Corp.

Semtech Corporation

Protection Products Division

652 Mitchell Rd., Newbury Park, CA 91320

Phone: [phone] FAX [phone]

7

www.semtech.com