Datasheet LC89975M Datasheet (SANYO)

Ordering number : EN*5391

41596HA (OT) No. 5391-1/7

Overview

The LC89975M is a lower-cost PAL-Format CCD delay
line based on the LC89970M, with the sizes of chip and
package miniaturized and the external parts count reduced.

Features

• 5 V single-voltage power supply

• On-chip 3× PLL circuit for 3·fsc operation from an fsc

(4.43 MHz) input

• Supports PAL/GBI and 4.43 NTSC systems, selected by
a control pin input

• Includes an on-chip comb filter for chrominance signal
crosstalk exclusion. This adjustment-free circuit
provides high-precision comb characteristics.

• Peripheral circuits included on chip to allow operation
with minimal external circuits.

• Positive-phase signal input, positive phase signal output
(luminance signal)

Functions

• CCD shift register (for chrominance and luminance
signals)

• CCD drive circuit

• Circuit for switching the number of CCD stages

• CCD signal addition circuit

• Auto-bias circuit

• Sync tip clamping circuit (luminance signal)

• Center bias circuit (chrominance signal)

• Sample-and-hold circuit

• PLL 3× circuit

• 3·fsc clock output circuit

• RD voltage generation step-up circuit

Package Dimensions

unit: mm

3111-MFP14S

Preliminary

SANYO: MFP14S

[LC89975M]

LC89975M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN

PAL-Format Delay Line

NMOS + CCD

Specifications

Absolute Maximum Ratings at Ta = 25°C

Recommended Conditions at Ta = 25°C

Parameter Symbol Conditions Ratings Unit

Supply voltage V

DD

–0.3 to +6.0 V
Allowable power dissipation Pdmax 250 mW
Operating temperature Topr –10 to +60 °C
Storage temperature Tstg –55 to +150 °C

Parameter Symbol Conditions min typ max Unit

Supply voltage V

DD

4.75 5.00 5.25 V

Clock input amplitude V

CLK

300 500 1000 mVp-p

Clock frequency F

CLK

Sine wave — 4.43361875 — MHz

Chrominance signal input amplitude V

IN-C

— 350 500 mVp-p

Luminance signal input amplitude V

IN-Y

— 400 572 mVp-p

Pin Assignment

Block Diagram

No. 5391-2/7

LC89975M

Control Pin

Switching levels

Note: Since a pull-down resistor of about 70 kΩ is built in the control pin circuit, it will remain fixed at the low level if

left open.

3fsc Pin

This pin outputs the 3·fsc clock signal generated by the PLL 3× circuit.

Electrical Characteristics at VDD= 5.0 V, Ta = 25°C, F

CLK

= 4.43361875 MHz, V

CLK

= 500 mVp-p

No. 5391-3/7

LC89975M

CONT

Mode Chrominance signal delay Luminance signal delay

(typical example) (number of CCD stages) (number of CCD stages)
Low PAL/GBI 2H (1705) + 0H (2.5) 1H (849)
High 4.43 NTSC 1H (847) + 0H (2.5) 1H (843)

Low/High Symbol min typ max Unit

Low V

L

–0.3 0.0 +0.5 V

High V

H

2.0 5.0 6.0 V

Parameter Symbol Test conditions

Switch states

min typ max Unit

SW1 SW2 SW3

Power-supply current

I

DD-1

1

a a b

27 32 37 mA

I

DD-2

b a b

Chrominance System Characteristics (with no signal applied to the Y-IN pin)

Luminance System Characteristics (with no signals applied to the C-IN1 and C-IN2 pins)

No. 5391-4/7

LC89975M

Parameter Symbol Test conditions

Switch states

min typ max Unit

SW1 SW2 SW3

Pin voltage (input)

V

INC-1

a a b

2.2 2.7 3.2 V

V

INC-2

2

b a b

Pin voltage (output)

V

OUTC-1

a a b

1.5 2.0 2.5 V

V

OUTC-2

b a b

Voltage gain

G

VC-1

3

a a b

0 2 4 dB

G

VC-2

b a b

Comb depth

C

D-1

4

a a b

— –40 –35 dB

C

D-2

b a b

Linearity

L

NC-1

5

a a b

–0.3 0.0 +0.3 dB

L

NC-2

b a b

Clock leakage (3·fsc)

L

CK3C-1

a a b

— 10 50 mVrms

L

CK3C-2

6

b a b

Clock leakage fsc)

L

CK1C-1

a a b

— 0.5 1.5 mVrms

L

CK1C-2

b a b

Noise

N

C-1

7

a a b

— 0.5 2.0 mVrms

N

C-2

b a b

Output impedance

Z

OC-1

8

a a a, b

200 350 500 Ω

Z

OC-2

b a a, b

0H delay time

T

DC-1

9

a a b

— 245 — ns

T

DC-2

b a b

Parameter Symbol Test conditions

Switch states

min typ max Unit

SW1 SW2 SW3

Pin voltage (input)

V

INY-1

a a b

1.7 2.2 2.7 V

V

INY-2

10

b a b

Pin voltage (output)

V

OUTY-1

a a b

0.8 1.3 1.8 V

V

OUTY-2

b a b

Voltage gain

G

VY-1

11

a a b

0 2 4 dB

G

VY-2

b a b

Frequency response

G

FY-1

12

a b b

–2 0 2 dB

G

FY-2

b b b

Differential gain

D

GY-1

a a b

0 5 7 %

D

GY-2

13

b a b

Differential phase

D

PY-1

a a b

0 5 7 deg

D

PY-2

b a b

Linearity

L

SY-1

14

a a b

37 40 43 %

L

SY-2

b a b

Clock leakage (3·fsc)

L

CK3Y-1

a a b

— 10 50 mVrms

L

CK3Y-2

15

b a b

Clock leakage (fsc)

L

CK1Y-1

a a b

— 0.5 1.5 mVrms

L

CK1Y-2

b a b

Noise

N

Y-1

16

a a b

— 0.5 2.0 mVrms

N

Y-2

b a b

Output impedance

Z

OY-1

17

a a c, b

250 400 550 Ω

Z

OY-2

b a c, b

Delay time

T

DY-1

18

a a b — 63.88 —

µs

T

DY-2

b a b — 63.43 —

Test Conditions

1. Power-supply current with no input signal applied

2. Pin output voltage with no input signal applied (center bias voltage)

3. Measure the C-OUT output when 350-mVp-p sine wave signals are input to C-IN1 and C-IN2.

GVC= 20 log [dB]

Measured frequencies

G

VC-1

4.429662 MHz (PAL/GBI)

G

VC-2

4.425694 MHz (4.43 NTSC)

4. Measure the comb depth from the C-OUT output when 350-mVp-p sine wave signals of frequency fa are input to C­IN1 and C-IN2 and when signals of frequency fb are input.

CD= 20 log [dB]

Measured frequencies fa fb

C

D-1

4.429662 MHz 4.425756 MHz (PAL/GBI)

C

D-2

4.425694 MHz 4.417819 MHz (4.43 NTSC)

5. Measure the C-OUT output when 200-mVp-p sine wave signals are input to C-IN1 and C-IN2 and when 500-mVp-p
sine wave signals are input and calculate the gain difference.

LNC= 20 log

(

/

)

[dB]

Measured frequencies

L

NC-1

4.429662 MHz (PAL/GBI)

L

NC-2

4.425694 MHz (4.43 NTSC)

6. Measure the 3·fsc (13.3 MHz) and fsc (4.43 MHz) components in the C-OUT output with no input signal applied.

7. Measure the noise in the C-OUT output with no input signal applied.
Set up the noise meter with a 200-kHz high-pass filter and a 5-MHz low-pass filter.

8. Let V1 be the C-OUT output when 350-mVp-p sine wave signals are input to C-IN1 and C-IN2 with SW3 in the a
position, and V2 be the C-OUT output with SW3 in the b position.

ZOC= × 500 [Ω]

Measured frequencies

Z

OC-1

4.429662 MHz (PAL/GBI)

Z

OC-2

4.425694 MHz (4.43 NTSC)

V2 [mVp-p] – V1 [mVp-p]

V1 [mVp-p]

Output for a 200-mVp-p input [mVp-p]

200 [mVp-p]

Output for a 500-mVp-p input [mVp-p]

500 [mVp-p]

The C-OUT output for an fb input [mVp-p]
The C-OUT output for an fa input [mVp-p]

C-OUT output [mVp-p]

350 [mVp-p]

No. 5391-5/7

LC89975M

9. The C-OUT output delay time with respect to a C-IN1 input (the 2.5-bit CCD delay)

10. The pin output voltage when no input signal is applied (the clamp voltage)

11. Measure the Y-OUT output when a 200-kHz 400-mVp-p sine wave is input to Y-IN.

GVY= 20 log [dB]

12. Measure the Y-OUT output when a 200-kHz 200-mVp-p sine wave is input to Y-IN and when 3.3-MHz 200-mVp-p
sine wave is input.

GFY= 20 log [dB]

Adjust Vbias to set the bias to the clamp level plus 250 mV.

13. Apply a 5-step waveform (see the figure) to Y-IN and measure the Y-OUT output differential gain and differential
phase with a vectorscope.

14. Apply a 5-step waveform (see the figure) to Y-IN and measure the Y-OUT output luminance signal level (Y) and
sync level (S).

LSY= × 100 [%]

15. Measure the 3·fsc (13.3 MHz) and fsc (4.43 MHz) components in the Y-OUT output with no input signal applied.

16. Measure the noise in the Y-OUT output with no input signal applied.
Set up the noise meter with a 200-kHz high-pass filter, a 5-MHz low-pass filter, and a 4.43-MHz trap filter.

17. Let V1 be the Y-OUT output when a 200-kHz 400-mVp-p sine wave signal is input to Y-IN and with SW3 in the c
position, and V2 be the Y-OUT output with SW3 in the b position.

ZOY= × 500 [Ω]

18. The Y-OUT output delay time with respect to inputs to Y-IN.

V2 [mVp-p] – V1 [mVp-p]

V1 [mVp-p]

S [mV]

Y [mV]

The Y-OUT output for a 3.3-MHz input [mVp-p]

The Y-OUT output for a 200-kHz input [mVp-p]

Y-OUT output [mVp-p]

400 [mVp-p]

No. 5391-6/7

LC89975M

PS No. 5391-7/7

LC89975M

Test Circuit

This catalog provides information as of April, 1996. Specifications and information herein are subject to change
without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
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distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.