Datasheet LC895198 Datasheet (SANYO)

Ordering number : ENN6237

N3099TH (OT) No. 6237-1/10

Overview

The LC895198 is a CD-ROM decoder that supports
ATAPI (IDE) and includes 1 MB of on-chip DRAM.

Functions

• CD-ROM ECC function

• Sub-code read function

• Built-in ATAPI (IDE) I/F (register and other blocks)

• CAV audio function

• Built-in DVD-ROM I/F (8-bit width)

• Built-in 1-Mbit DRAM

Features

•32× speed supported

16.6MBytes/s (with IORDY)
Operation frequency: 33.8688 MHz

•32× speed supported

16.6MBytes/s (without IORDY)
Operation frequency: 36 MHz

• CD main channel, C2 flag, and subcode areas in buffer
RAM can be set freely by user

• Built-in batch transfer function (function for sending CD
main channel, C2 flag, subcode, etc., at one time)

• Built-in multi transfer function (function for sending
several blocks at one time)

• Built-in CAV-AUDIO function

• Built-in intelligent functions (auto buffering, auto
decoding, CD-R support, etc.)

• Built-in subcode P to W buffering function (NO-ECC)
and CD-TEXT support

Package Dimensions

unit: mm

3237-LQFP120

LC895198

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

CD-ROM Decoder for 32× ATAPI (IDE) Drives

CMOS IC

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max Ta = 25°C –0.3 to +7.0 V

Input/output voltage V

I, VO

Ta = 25°C –0.3 to VDD+ 0.3 V
Allowable power dissipation Pd max Ta ≤ 70°C 400 mW
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Soldering temperature (pin part only) 10 s 235 °C
Input/output power I

I

, I

O

Per 1 input/output reference cell ±20 mA

Specifications

Absolute Maximum Ratings at VSS= 0 V

120

1

0.4

14.0

(1.2)

(0.5)

0.125

16.0

0.5

0.15

1.6max

0.1

0.4

14.0

(1.2)

(1.4)

16.0

SANYO: LQFP120

[LC895198]

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

No. 6237-2/10

LC895198

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Input high-level voltage V

IH

TTL levels (1)

2.2——V

Input low-level voltage V

IL

— — 0.8 V

Input high-level voltage V

IH

TTL levels

(9)

2.2——V

Input low-level voltage V

IL

with pull-up resistor

— — 0.8 V

Input high-level voltage V

IH

TTL levels Schmitt DRESP

2.2——V

Input low-level voltage V

IL

with pull-down resistor HDB0 to HDB7

— — 0.8 V

Input high-level voltage V

IH

TTL levels

(2), (3), (10)

2.4——V

Input low-level voltage V

IL

Schmitt

— — 0.8 V

Output high-level voltage V

OHIOH

= –2 mA

(9)

VDD– 2.1 — — V

Output low-level voltage V

OLIOL

= 2 mA — — 0.4 V

Output high-level voltage V

OHIOH

= –8 mA

(4)

VDD– 2.1 — — V

Output low-level voltage V

OLIOL

= 8 mA — — 0.4 V

Output high-level voltage V

OHIOH

= –4 mA

(7), (10)

VDD– 2.1 — — V

Output low-level voltage V

OLIOL

= 24 mA — — 0.4 V

Output low-level voltage V

OLIOL

= 24 mA (8) — — 0.4 V

Output low-level voltage V

OLIOL

= 8 mA (5), (6) — — 0.4 V

Input leak current I

IL

VI= VSS, V

DD

(1), (2), (3), (10) –10 +10 µA

Output leak current I

OZ

During high-impedance output (5), (7), (8), (10)

–10 +10 µA

Pull-up resistance R

UP

(6), (9) 40 80 160 kΩ

Pull-down resistance R

DN

DRESP, DREQ, HDB0 to HDB7

40 80 160 kΩ

Electrical Characteristics at Ta = 0 to +70°C, VSS= 0 V, VDD= 4.5 to 5.5 V

The applicable pin sets are as follows.

INPUT
(1) ATPINSEL, CSCTRL, SUA0 to SUA6, BCK, C2PO, LRCK, DSDATA, SBS0, SCOR, WFCK, TEST0 to TEST1, AUDIOCK
(2) ZRESET, ZCS, ZRD, ZWR, CSEL
(3) DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST

OUTPUT
(4) EXCK, DREQ, MCK, MCK3
(5) ZRSTCPU
(6) ZINT, ZINT1, ZSWAIT
(7) DMARQ, HINTRQ
(8) IORDY, ZIOCS16

INOUT
(9) D0 to D7
(10) DD0 to DD15, ZDASP, ZPDIAG

Note: Pins other than XTAL and XTALCK are not included in DC characteristics.

Allowable Operating Ranges at Ta = 0 to +70°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DD

4.5 5.0 5.5 V

Input voltage range V

IN

0V

DD

V

IOcell 5.0 V supply voltage

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DD

3.0 3.3 3.6 V

Input voltage range V

IN

0V

DD

V

Internal cell 3.3 V supply voltage

No. 6237-3/10

LC895198

Recommended Oscillator Circuit Example

LC895198

R1

R2

C2C1

XTALCK

PN28

XTAL
PN29

A12524

R1 = 1 MΩ
R2 = 15 Ω
C1 = 0
C2 = 47 pF
When the ceramic clock oscillator frequency is 33.8688 MHz:

(The 33.8688 MHz in this recommended example is the third harmonic.)
The exact values of the components are influenced by the printed circuit board used. Consult with the manufacturer of

the oscillator element used to determine these values.

No. 6237-4/10

LC895198

Block Diagram

Sub-code I/F

10byte FIFO for Sub Q

Address generator

Address generator

DAC

CAV-Audio contorol

De-scramble &

Buffering

Address generator

Microcontroller

RAM access

Address generator

Address generator

ECC & EDC

Based HISIDE

IDE I/F

Address generator

Data output input I/F

Address generator

DVD-ECC I/F

Bus

Arbiter

&

DRAM

controller

1Mbit

Buffer

DRAM

Each Block
Bus control
signal

Each Block
Register
R0-R127

CD-DSP I/F

& SYNC
Detector

Reset

Controller

CD-DSP

HOST

Micro

controller

DVD-ECC

dec

decoder

Clock

generator

*1

*2

*10

*6
*7

*9

*8

*3

*5

*4

EXCK

ZRESET

ZINT0

ZSWAIT

ZINT1

ZRSTCPU

XTALCK

XTAL

MCK3
MCK

Each Block

Data bus[0:7]

Address bus[0:16]

RAM
Data bus[0:15]

LC895198

**1

A12525

*1 WFCK, SBSO, SCOR
*2 BCK, SDATA, LRCK, C2PO
*3 DD0 to DD15, ZDASP, ZPDIAG
*4 ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, CSEL
*5 DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST
*6 ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
*7 D0 to D7
*8 HDB0 to HDB7, DRESP
*9 DREQ
*10 DBCK, DLRCK, DSDATA
**1 HISIDE(WD25C32) is made by WESTERN DIGITAL

No. 6237-5/10

LC895198

Pin Functions

LC895198 Pin Functions 1
(When ATPINSEL (pin 113) is 0)

Type

I INPUT B BIDIRECTION NC NOT CONNECT

O OUTPUT P POWER

Pin No. Pin Type Function

1V

DD0

P 5.0 V
2 DREQ O DVD ECC data request output
3 DRESP I DVD ECC data latch signal input
4 HDB7 (IOP0) B
5 HDB6 (IOP1) B
6 HDB5 (IOP2) B
7 HDB4 (IOP3) B DVD ECC data I/O
8 HDB3 (IOP4) B These pins can be switched to function as general-purpose I/O ports by register settings.
9 HDB2 (IOP5) B

10 HDB1 (IOP6) B
11 HDB0 (IOP7) B
12 MCK3 O XTALCLK 1/1, 1/2, and stop output
13 V

SS0

P

14 V

DD1

P 3.3 V

15 V

DD0

P 5.0 V

16 DSDATA O
17 DLRCK O D/A converter output
18 DBCK O
19 C2PO I
20 SDATA I

CD DSP interface

21 BCK I
22 LRCK I
23 EXCK O
24 WFCK I

Subcode I/O

25 SBSO I
26 SCOR I
27 MCK O XTALCLK 1/1, 1/2, and stop output
28 XTALCK I Crystal oscillator circuit input
29 XTAL O Crystal oscillator circuit output
30 V

SS0

P

31 V

DD1

P 3.3 V

32 V

DD0

P 5.0 V

33 V

SS0

P

34 CSCTRL I Active low/active high selection for the microcontroller CS pin
35 ZRD I Microcontroller data read signal input
36 ZWR I Microcontroller data write signal input
37 ZCS I Register chip select input from the microcontroller
38 SUA0 I
39 SUA1 I
40 SUA2 I
41 SUA3 I Microcontroller register selection signals
42 SUA4 I
43 SUA5 I
44 SUA6 I
45 V

DD1

P 3.3 V

46 V

DD0

P 5.0 V

47 V

SS0

P

Continued on next page.

No. 6237-6/10

LC895198

Continued from preceding page.

Pin No. Pin Type Function

48 D0 B
49 D1 B
50 D2 B
51 D3 B Microcontroller data signals.
52 D4 B These pins have built-in pull-up resistors.
53 D5 B
54 D6 B
55 D7 B
56 ZINT0 O

Interrupt request signal output to the microcontroller

57 ZINT1 O
58 ZSWAIT O WAIT signal output to the microcontroller
59 ZRSTCPU O CPU reset signal output
60 V

SS0

P

61 V

DD0

P 5.0 V

62 CSEL I
63 ZHRST I
64 ZDASP B ATAPI control signals
65 ZCS3FX I
66 ZCS1FX I
67 V

SS1

P

68 DA2 I
69 DA0 I

ATAPI control signals

70 ZPDIAG B
71 DA1 I
72 V

SS1

P

73 ZIOCS16 O

ATAPI control signals

74 HINTRQ O
75 V

SS1

P

76 V

DD1

P 3.3 V

77 ZDMACK I

ATAPI control signals

78 IORDY O
79 V

SS1

P

80 ZDIOR I
81 ZDIOW I ATAPI control signals
82 DMARQ O
83 DD15 B

ATAPI data bus

84 DD0 B
85 V

SS1

P

86 DD14 B
87 DD1 B

ATAPI data bus

88 DD13 B
89 DD2 B
90 V

SS1

P

91 V

DD0

P 5.0 V

92 DD12 B
93 DD3 B

ATAPI data bus

94 DD11 B
95 DD4 B
96 V

SS1

P

97 DD10 B
98 DD5 B ATAPI data bus
99 DD9 B

100 V

SS1

P

Continued on next page.

No. 6237-7/10

LC895198

Continued from preceding page.

Pin No. Pin Type Function

101 DD6 B
102 DD8 B ATAPI data bus
103 DD7 B
104 V

DD1

P 3.3 V

105 V

DD1

P 3.3 V

106 V

DD0

P 5.0 V

107 V

DD1

P 3.3 V

108 ZRESET I IC reset input
109 V

DD1

P 3.3 V

110 V

SS0

P

111 TEST1 I Test pin. This pin must be connected to V

SS

in normal operation.

112 V

SS0

P

113 ATPINSEL I ATAPI pin layout selection. This pin must be connected to V

SS0

.

114 V

SS0

P

115 TEST0 I Test pin. This pin must be connected to V

SS

in normal operation.

116 V

DD0

I 5.0 V
117 AUDIOCK I Clock input for the CAV audio block
118 V

DD0

P 5.0 V

119 V

DD0

P 5.0 V

120 V

SS0

P

• Unused ("NC") pins must be left open.

• Pins whose name begin with a Z operate with inverted (negative) logic.

• V

SS0

is the logic system ground and V

SS1

is the IDE interface driver ground.

• Applications must supply 5.0 V to V

DD0

and 3.3 V to V

DD1

.

No. 6237-8/10

LC895198

Pin Functions

LC895198 Pin Functions 2
(When ATPINSEL (pin 113) is 1)

Type

I INPUT B BIDIRECTION NC NOT CONNECT

O OUTPUT P POWER

Pin No. Pin Type Function

1V

DD0

P 5.0 V
2 DREQ O DVD ECC data request output
3 DRESP I DVD ECC data latch signal input
4 HDB7 (IOP0) B
5 HDB6 (IOP1) B
6 HDB5 (IOP2) B
7 HDB4 (IOP3) B DVD ECC data I/O
8 HDB3 (IOP4) B These pins can be switched to function as general-purpose I/O ports by register settings.
9 HDB2 (IOP5) B

10 HDB1 (IOP6) B
11 HDB0 (IOP7) B
12 MCK3 O XTALCLK 1/1, 2/5, 1/5, 1/512, and stop output
13 V

SS0

P

14 V

DD1

P 3.3 V

15 V

DD0

P 5.0 V

16 DSDATA O
17 DLRCK O DAC converter output
18 DBCK O
19 C2PO I
20 SDATA I

CD DSP interface

21 BCK I
22 LRCK I
23 EXCK O
24 WFCK I

Subcode I/O

25 SBSO I
26 SCOR I
27 MCK O XTALCLK 1/1, 1/2, and stop output
28 XTALCK I Crystal oscillator circuit input
29 XTAL O Crystal oscillator circuit output
30 V

SS0

P

31 V

DD1

P 3.3 V

32 V

DD0

P 5.0 V

33 V

SS0

P

34 CSCTRL I Active low/active high selection for the microcontroller CS pin
35 ZRD I Microcontroller data read signal input
36 ZWR I Microcontroller data write signal input
37 ZCS I Register chip select input from the microcontroller
38 SUA0 I
39 SUA1 I
40 SUA2 I
41 SUA3 I Microcontroller register selection signals
42 SUA4 I
43 SUA5 I
44 SUA6 I
45 V

DD1

P 3.3 V

46 V

DD0

P 5.0 V

47 V

SS0

P

Continued on next page.

No. 6237-9/10

LC895198

Continued from preceding page.

Pin No. Pin Type Function

48 D0 B
49 D1 B
50 D2 B
51 D3 B Microcontroller data signals.
52 D4 B These pins have built-in pull-up resistors.
53 D5 B
54 D6 B
55 D7 B
56 ZINT0 O

Interrupt request signal output to the microcontroller

57 ZINT1 O
58 ZSWAIT O WAIT signal output to the microcontroller
59 ZRSTCPU O CPU reset signal output
60 V

SS0

P

61 V

DD0

P 5.0 V

62 CSEL I
63 DD7 B

ATAPI control signals

64 DD8 B

ATAPI data bus

65 DD6 B
66 DD9 B
67 V

SS1

P

68 DD5 B
69 DD10 B

ATAPI data bus

70 DD4 B
71 DD11 B
72 V

SS1

P

73 DD3 B

ATAPI data bus

74 DD12 B
75 V

SS1

P

76 V

DD1

P 3.3 V

77 DD2 B

ATAPI data bus

78 DD13 B
79 V

SS1

P

80 DD1 B
81 DD14 B

ATAPI data bus

82 DD0 B
83 DD15 B
84 DMARQ O ATAPI control signal
85 V

SS1

P

86 ZDIOW I
87 ZDIOR I

ATAPI control signal

88 IORDY O
89 ZDMACK I
90 V

SS1

P

91 V

DD0

P 5.0 V

92 HINTRQ O
93 ZIOCS16 O

ATAPI control signal

94 DA1 I
95 ZPDIAG B
96 V

SS1

P

97 DA0 I
98 DA2 I ATAPI control signal
99 ZCS1FX I

100 V

SS1

P

Continued on next page.

PS No. 6237-10/10

LC895198

This catalog provides information as of November, 1999. Specifications and information herein are
subject to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

Continued from preceding page.

Pin No. Pin Type Function

101 ZCS3FX I
102 ZDASP B ATAPI control signal
103 ZHRST I
104 V

DD1

P 3.3 V

105 V

DD1

P 3.3 V

106 V

DD0

P 5.0 V

107 V

DD1

P 3.3 V

108 ZRESET I IC reset input
109 V

DD1

P 3.3 V

110 V

SS0

P

111 TEST1 I Test pin. This pin must be connected to V

SS

in normal operation.

112 V

SS0

P

113 ATPINSEL I ATAPI pin layout selection. This pin must be connected to V

DD0

.

114 V

SS0

P

115 TEST0 I Test pin. This pin must be connected to V

SS

in normal operation.

116 V

DD0

I 5.0 V
117 AUDIOCK I Clock input for the CAV audio block
118 V

DD0

P 5.0 V

119 V

DD0

P 5.0 V

120 V

SS0

P

• Unused ("NC") pins must be left open.

• Pins whose name begin with a Z operate with inverted (negative) logic.

• V

SS0

is the logic system ground and V

SS1

is the IDE interface driver ground.

• Applications must supply 5.0 V to V

DD0

and 3.3 V to V

DD1

.