Datasheet LC863264A, LC863240A, LC863256A, LC863248A Datasheet (SANYO)

Ordering number : ENN*6694

LC863264/56/48/40A

8-Bit Single Chip Microcontroller

Preliminary
Overview

The LC863264/56/48/40A are 8-bit single chip microcontrollers with the following on-chip functional blocks:

- CPU : Operable at a minimum bus cycle time of 0.424µs

- On-chip R O M capaci ty
Program ROM : 64K/56K/48K/40K bytes
CGROM : 16K bytes

- On-chip RAM capacity : 640 bytes

- OSD RAM : 352 × 9 bits

- Closed-Caption TV controller and the on-screen display controller

- Closed-Caption data slicer

- Four channels × 8-bit AD Converter

- Three channels × 7-bit PWM

- Two 16-bit timer/counters, 14-bit base timer

- 8-bit synchronous serial interface circuit

- IIC-bus compliant serial interface circuit (Multi-master type)

- ROM correction function

- 16-sourc e 10-vect o red interrupt system

- Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the Closed Caption function

All of the above functions are fabricated on a single chip.

CMOS IC

Ver.0.91
51299

91400 RM (IM) HS No.6694-1/20

LC863264/56/48/40A

Features

(1) Read-Only Memory (ROM) : 65024
40960
16128

8 bits / 57344

×

8 bits for program

×

8 bits for CGROM

×

8 bits / 49152

×

8 bits

×

(2) Random Access Memory (RAM) : 640 × 8 bits (including 128 bytes for ROM correction function)
352

9 bits (for CRT display)

×

(3) OSD functions

- Screen display : 36 characters × 16 lines (by software)

- RAM : 352 words (9 bits per word)
Display area : 36 words × 8 lines
Control area : 8 words × 8 lines

- Characters
Up to 252 kinds of 16 × 32 dot character fonts
(4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts :
a 16 × 17 dot and 8 × 9 dot character font
At least 111 characters need to be divide to display the caption fonts.

- Various character attributes
Character colors : 16 colors
Character background colors : 16 colors
Fringe / shadow colors : 16 colors
Full screen colors : 16colors
Rounding
Underline
Italic character (slanting)

- Attribute can be changed without spacing

- Vertical display start line number can be set for each row independently (Rows can be overlapped)

- Horizontal display start position can be set for each row independently

- Horizontal pitch (bit 9 - 16)

*1

and vertical pitch (bit-32) can be set for each row independently

- Different display modes can be set for each row independently
Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode

- Ten character sizes

*1

Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5)
(1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5)

- Shuttering and scrolling on each row

- Simplified Graphic Display
*1 Note : ran ge depends on display mode : r efer to the manual f o r details.

(4) Data Slicer (NTSC)

- Line 21 closed caption data and XDS data extraction

(5) Bus Cycle Time / Instruction-Cycle Time

Bus cycle time Instruction cycle time System clock oscillati on Oscillation Frequency Voltage

0.424µs 0.848µs Internal VCO
(Ref : X’tal 32.768kHz)

7.5µs 15.0µs Internal RC 800kHz 4.5V to 5.5V

183.1µs 366.2µs Crystal 32.768kHz 4.5V to 5.5V

14.156MHz 4.5V to 5.5V

(6) Ports

- Input / Output Ports : 5 ports (28 terminals)
Data direction programmable in nibble units : 1 port (8 terminals)

(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)

Data direction programmable for each bit individually : 4 ports (20 terminals)

No.6694-2/20

LC863264/56/48/40A

(7) AD converter

- 4 channels × 8-bit AD converters

(8) Serial interfaces

- IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.

- Synchronous 8-bit serial interface

(9) PWM output

- 3 channels × 7-bit PWM

(10) Timer

- Timer 0 : 16-bit timer/counter

With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution o f timer is 1 tCYC.

- Timer 1 : 16-bit timer/PWM

Mode 0 : Two 8- bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable bit PWM (9 to 16 bits)
In mode0/1,the re solution of Ti mer1/PWM is 1 tC YC
In mode2/3,the resolution is selectable by program; tCYC or 1/2 tCYC

- Base timer
Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer
clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0

(11) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)

- Noise rejection function

- Polarity switching

(12) Watchdog timer

External RC circuit is required
Interrupt or system reset is activated when the timer overflows

(13) ROM correction function

Max 128 bytes / 2 addresses

(14) Interrupts

- 16 sources 10 vectored interrupts

1. External Interrupt INT0

2. External Interrupt INT1

3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)

4. External Interrupt INT3, base timer

5. Ti mer/counter T0H (U pp er 8 bits)

6. Timer T1H,T1L

7. SIO0

8. Data slicer

9. Vertical synchronous signal interrupt (

), horizontal line (

VS

HS

), AD

10. IIC, Port 0

No.6694-3/20

LC863264/56/48/40A

- Interrupt prior ity control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, high
or highest priority can be set.

(15) Sub-routine stack level

- A maximum of 128 levels (stack is built in the internal RAM)

(16) Multiplication/division instruction

- 16 bits × 8 bits (7 instruction cycle times)

- 16 bits / 8 bits (7 instruction cycle times)

(17) 3 oscillation circuits

- Built-in RC oscillation circuit used for the system clock

- Built-in VCO circuit used for the system clock and OSD

- X’tal oscillation circuit used for base timer, system clock and PLL reference

(18) Standby function

- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.

- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.

Pull the reset terminal (

•

Feed the selected level to either P70/INT0 or P71/INT1.

•

Input the interrupt condition to Port 0.

•

) to low level.

RES

(19) Package

- DIP42S

- QIP48E

(20) Development tools

- Flash EEPROM: 2 Flash microcontrollers are available:LC86F3264A,LC86F3248A. Flash version is different

depending on which microcontroller is used.

LC86F3264A (LC863264A / LC863256A) (under development)
LC86F3248A (LC863248A / LC863240A)

- Evaluation chip: LC863096

- Emulator: EVA86000 (main) + ECB863200 (evaluation chip board)

+ POD863200 (pod: DIP42S) or POD863201 (QIP48E)

No.6694-4/20

System Block Diagram

IIC

SIO0

Timer 0

Timer 1

Base Timer

ADC

INT0-3

Noise Rejection Filter

PWM

Data Slicer

Interrupt Control

Standby Control

X’tal

RC

VCO

PLL

LC863264/56/48/40A

Clock

Generator

ROM Correct Control

XRAM

Bus Interface

Port 1

Port 6

Port 7

Port 8

OSD
Control
Circuit

CGROM

VRAM

IR PLA

ROM

PC

ACC

B Register

C Register

ALU

PSW

RAR

RAM

Stack Pointer

Port 0

Watch Dog Timer

No.6694-5/20

LC863264/56/48/40A

N

R

G

L

I

Pin Assignment

• DIP42S

P10/SO0

P11/SI0

P12/SCK0
P13/PWM1
P14/PWM2
P15/PWM3

P17/PWM

P84/AN4
P85/AN5
P86/AN6
P87/AN7

CVIN

• QIP48E

P15/PWM3

P17/PWM

VDD

P84/AN4
P85/AN5
P86/AN6
P87/AN7

P16

VSS
XT1
XT2

VDD

RES

FILT

VS
HS

P16

VSS
XT1
XT2

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

NC

48

1
2
3
4
5
6
7
8
9
10
11
12

13

RES

42

P07

41

P06

40

P05
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P04

P03

P02

P01

P00

P73/INT3/T0IN

P72/INT2/T0IN

P71/INT1

P70/INT0

P63/SCLK1

P62/SDA1

P61/SCLK0

P60/SDA0

I

BL

B

G

R

Package Dimension

(unit : mm)

3025B

SANYO : DIP-42S(600mil)

Package Dimension

P14/PWM2

P13/PWM1

P12/SCK0

P11/SI0

P10/SO0

NC

P07

P06

P05

P04

P03

47

46

45

44

43

42

41

40

39

38

37

36

P02

35

P01

34

P00

33

NC

32

P73/INT3/T0IN

31

P72/INT2/T0IN

30

P71/INT1

29

P70/INT0

28

P63/SCLK1

27

P62/SDA1

26

P61/SCLK0

25

14

15

16

17

18

19

20

21

22

23

B

HS

VS

NC

FILT

CVI

B

P60/SDA0

24

NC

(unit : mm)

3156

SANYO : QIP-48E

No.6694-6/20

LC863264/56/48/40A

Pin Description

Pin Description Table

Terminal I/O Function Description Option
VSS - Negative power supply
XT1 I Input terminal for crystal oscillator
XT2 O Output terminal for crystal oscillator
VDD - Positive p ower supply

RES

FILT O Filter terminal for PLL
CVIN I Video signal input terminal

VS
HS

R O Red (R) output terminal of RGB image output
G O Green (G) output terminal of RGB image output
B O Blue (B) output terminal of RGB image output
I O Intensity ( I ) output terminal of RGB image output
BL O Fast blanking control signal

Port 0
P00 - P07

Port 1 •8-bit input/output port
P10 - P17

Port 6 •4-bit input/output port
P60 - P63

I Reset terminal

I Vertical synchronization signal input terminal
I Horizontal synchronization signal input terminal

Switch TV image signal and captio n/OSD image signal

I/O

I/O

I/O

•8-bit input/output port,
Input/output can be specified in nibble unit

•Other functions
HOLD release input
Interrupt input

Input/output can be specified in a bit

•Other functions

P10

Input/output can be specified for each bit

•Other functions

P60

SIO0 data output

P11

SIO0 data input/bus input/output

P12

SIO0 clock input/output

P13

PWM1 output

P14

PWM2 output

P15

PWM3 output

P17

Timer1 (PWM) output

IIC0 data I/O

P61

IIC0 clock output

P62

IIC1 data I/O

P63

IIC1 clock output

Pull-up resistor
provided/not provided
Output Format
CMOS/Nch-OD

Output Format
CMOS/Nch-OD

No.6694-7/20

LC863264/56/48/40A

Terminal I/O Function Description Option
Port 7 •4-bit input/output port
P70

P71 - P73

Port 8
P84 - P87

NC - Unused terminal

I/O

I/O

Input or output can be specified for each bit

•Other function
P70

Interrupt r eceiver format, vector addresses

rising falling rising/

INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH

•4-bit input/output port
Input or ou tput can be specified for each bit

•Other function
AD conver te r input port (4 lines)

Leave open

INT0 input/HOLD release input/
Nch-Tr. output for wachdog timer

P71

INT1 input/HOLD release input

P72

INT2 input/Timer 0 event input

INT3 input (noise rejection filter connected)

P73

Timer 0 event input

falling

/

H level L level vector

Output form and existance of pull-up resistor for all ports can be specified for each bit.

•
Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1.

•

Port status in reset

•

Terminal I/O Pull-up resistor status at selecting pull-up option

Port 0 I Pull-up resistor OFF, ON after reset release
Port 1 I Programmable pull-up resistor OFF

No.6694-8/20

LC863264/56/48/40A

1. Absolute Maximum Ratings at VSS=0V and Ta=25°C

Parameter Symbol Pins Conditions

Supply voltage VDDMAX VDD -0.3 +7.0
Input voltage VI(1) •

Output voltage VO(1) R, G, B, I, BL,

Input/output
voltage
High
level
output
current

Low
level
output
current

dissipation
Operating

temperature
range
Storage
temperature
range

output
current

Total
output
current

Peak
output
current

Total
output
current

VIO •Ports 0, 1, 6, 7,

IOPH(1) •Ports 0, 1, 7, 8 •CMOS output

IOPH(2) R, G, B, I, BL •CMOS output

IOAH(1) •Ports 0, 1 Total of all pins. -20

∑

IOAH(2) Ports 7, 8 Total of all pins. -10

∑

IOAH(3) R, G, B, I, BL Total of all pins. -15

∑

IOPL(1) Ports 0, 1, 6, 8 For each pin. 20
IOPL(2) Port 7 For each pin. 15
IOPL(3) R, G, B, I, BL For each pin. 5

IOAL(1) Ports 0, 1 Total of all pins. 40

∑

IOAL(2) Ports 6, 7, 8 Total of all pins. 40

∑

IOAL(3) R, G, B, I, BL Total of all pins. 15

∑

Pdmax

Topr -10 +70

Tstg -55 +125

RES,HS,VS

CVIN

FILT

8

DIP42S 800 Maximum power
QIP48E

,

-0.3

-0.3

-0.3

•For each pin.

•For each pin.

Ta=-10 to +70°C

Ratings

VDD[V]

min. typ. max.

VDD+0.3

VDD+0.3

VDD+0.3

-4 Peak

-5

400

unit

V

mA

mW

C

°

No.6694-9/20

LC863264/56/48/40A

2. Recommended Operating Range at Ta=-10°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

CYC

CYC

≤

Operating
supply voltage
range

VDD(1) 0.844µs ≤ t

VDD(2)

VDD

0.852µs

≤

4µs ≤ t
400µs

Hold voltage VHD VDD RAMs and the

registers data are
kept in HOLD
mode.

High level

VIH(1) Port 0 (Schumitt) Output disable 4.5 - 5.5 0.6VDD VDD

input voltage

VIH(2) •Ports 1,6 (Schumitt)

Output disable 4.5 - 5.5

•Port 7 (Schumitt)
port input/interrupt

•HS,VS,

RES

(Schumitt)

VIH(3) Port 70

Output disable 4.5 - 5.5

Watchdog timer input

VIH(4) •Port 8

Output disable 4.5 - 5.5 0.7VDD VDD

port input
Low level
input voltage

VIL(1) Port 0 (Schumitt) Output disable 4.5 - 5.5 VSS 0.2VDD
VIL(2) •Ports 1,6 (Schumitt)

Output disable 4.5 - 5.5 VSS

•Port 7 (Schumitt)

port input/interrupt

•HS,VS,

RES

(Schumitt)

VIL(3) Port 70

Output disable 4.5 - 5.5 VSS 0.6VDD

Watchdog timer input

VIL(4) Port 8

Output disable 4.5 - 5.5 VSS 0.3VDD

port input
CVIN VCVIN CVIN 5.0 1Vp-p

CYC

t

Operation
cycle time

(1) •All functions

operating

CYC

t

(2) •AD converter

operating

•OSD and Data
slicer are not
operating

CYC

t

(3) •OSD, AD

converter and
Data slicer are
not operating

Oscillation
frequency

FmRC Internal RC

oscillation

range

Ratings

VDD[V] min. typ. max.

4.5 5.5

4.5 5.5

2.0 5.5

0.75VDD

VDD-0.5

VDD

VDD

1Vp-p 1Vp-p

-3dB

4.5 - 5.5 0.844 0.848 0.852

4.5 - 5.5 0.844 30

4.5 - 5.5 0.844 400

4.5 - 5.5 0.4 0.8 3.0 MHz

* Vp-p : Peak-to-peak voltage

0.25VDD

+3dB

unit

V

Vp-p

*

s

µ

No.6694-10/20

LC863264/56/48/40A

3. Electrical Characteristics at Ta=-10°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

High level
input current

Low level
input current

output voltage

Low level
output voltage

Pull-up MOS
Tr. resistance
Bus terminal
short circuit
resistance
(SCL0-SCL1,
SDA0-SDA1)
Hysteresis
voltage

Input clump
votage
Pin
capacitance

IIH(1) Ports 0, 1, 6, 7, 8 •Output disable

•Pull-up MOS Tr.
OFF

•VIN=VDD
(including the off­ leak current of the
output Tr.)

RES

IIH(2) •

IIL(1) Ports 0, 1, 6, 7, 8 •Output disable

IIL(2) •

VOH(1) •CMOS output of

VOH(2) R, G, B, I, BL IOH=-0.1mA 4.5 - 5.5
VOL(1) Ports 0,1,71-73,8 IOL=10mA 4.5 - 5.5 1.5
VOL(2) Ports 0,1,71-73,8 IOL=1.6mA 4.5 - 5.5 0.4
VOL(3) •R, G, B, I, BL

VOL(4) Port 6 IOL=6.0mA 4.5 - 5.5 0.6
VOL(5) Port 70 IOL=1mA 4.5 - 5.5 0.4
Rpu •Ports 0, 1, 7, 8 VOH=0.9VDD 4.5 - 5.5 13 38 80 KΩ

RBS •P60-P62

VHIS •Ports 0, 1, 6, 7

VCLMP CVIN 5.0 2.3 2.5 2.7

CP All pins •f=1MHz

HS,VS

RES
HS,VS

RES
HS,VS

•

•

ports 0,1,71-73,8

•Port 6

•P61-P63

•

•

•VIN=VDD 4.5 - 5.5 1

•Pull-up MOS
Tr. OFF

•VIN=VSS
(including the off­ leak current of the
output Tr.)
VIN=VSS 4.5 - 5.5 -1

IOH=-1.0mA 4.5 - 5.5 VDD-1 High level

IOL=3.0mA 4.5 - 5.5 0.4

4.5 - 5.5 130

Output disable 4.5 - 5.5 0.1VDD

•Every other
terminals are
connected to VSS.

•Ta=25°C

Ratings

VDD[V] min. typ. max.

4.5 - 5.5 1

4.5 - 5.5 -1

VDD-0.5

4.5 - 5.5 10 pF

unit

µ

V

Ω

V

A

No.6694-11/20

LC863264/56/48/40A

Y

Y

4. Serial Input/Output Characteristics at Ta=-10°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

Cycle

Low Level

CKCY

t

(1) 2

•SCK0

Refer to figure 4. 4.5 - 5.5

•SCLK0

CKL

t

(1) 1

pulse width

Input clock

High Level

CKH

t

(1)
pulse width
Cycle

Serial clock

Low Level

CKCY

t

CKL

t
pulse width
High Level

Output clock

CKH

t

•SCK0

(2) 2

•SCLK0

(2)

•Use pull-up
resistor (1kΩ)
when Nch open­ drain output.

(2)

•Refer to figure 4.

pulse width

Data set up ti me

Data hold time

Serial input

ICK

t

CKI

t

SI0 •Data set-up to

0.1
SCK0.

•Data hold from
SCK0.

•Refer to figure 4.

Output delay time
(Using external

Output delay time
(Using internal

Serial output

clock)

clock)

CKO(1)

t

SO0 4.5 - 5.5

CKO(2)

t

SO0

•Data hold from
SCK0.

•Use pull-up
resistor (1kΩ)
when Nch open­ drain output.

•Refer to figure 4.

Ratings

VDD[V] min. typ. max.

1

4.5 - 5.5

1/2tCKC

1/2tCKC

4.5 - 5.5

0.1

7/12tCYC

+0.2

4.5 - 5.5

1/3tCYC

+0.2

unit

CYC

t

µ

s

5. IIC Input/Output Conditions at Ta=-10°C to +70°C, VSS=0V

Parameter Symbol

SCL Frequency f
BUS free time between stop - start t
HOLD time of start, restart condition t
L time of SCL t
H time of SCL t
Set-up time of restart condition t
HOLD time of SDA t
Set-up time of SDA t

SCL

0 100 0 400 kHz

BUF

4.7 - 1.3 - µs

HD;STA

4.0 - 0.6 - µs

LOW

4.7 - 1.3 - µs

HIGH

4.0 - 0.6 - µs

SU;STA

4.7 - 0.6 - µs

HD;DAT

0 - 0 0.9 µs

SU;DAT

250 - 100 - ns
Rising time of SDA, SCL tR - 1000 20+0.1Cb 300 ns
Falling time of SDA, SCL tF - 300 20+0.1Cb 300 ns
Set-up time of stop condition t

SU;STO

4.0 - 0.6 - µs

Standard High speed

min. max. min. max.

unit

Refer to figure 10
(Note) Cb : Total capacitance of all BUS (unit : pF)

No.6694-12/20

LC863264/56/48/40A

6. Pulse Input Conditions at Ta=-10°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

High/low level
pulse width

Rising/falling
time

tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)

tPIH(3)
tPIL(3)

tPIH(4)
tPIL(4)

tPIL(5)
tPIH(6)

tPIL(6)

tTHL
tTLH

•INT0, INT1

•INT2/T0IN
INT3/T0IN
(1/1 is selected for
noise rejection
clock.)
INT3/T0IN
(1/16 is selected
for noise rejection
clock.)
INT3/T0IN
(1/64 is selected
for noise rejectio n
clock.)

RES
HS,VS

HS

•Interrupt accept able

•Timer0-countable

•Interrupt accept able

•Timer0-countable

•Interrupt accept able

•Timer0-countable

•Interrupt accept able

•Timer0-countable

Reset acceptable 4.5 - 5.5 200

•Display position
controllable (Note)

•The active edge of

HS

and VS must

be apart at least

CYC

.

1 t

•Refer to figure 6.
Refer to figure 6. 4.5 - 5.5 500 ns

Ratings

VDD[V] min. typ. max.

4.5 - 5.5 1

4.5 - 5.5 2

4.5 - 5.5 32

4.5 - 5.5 128

4.5 - 5.5 8

unit

CYC

t

µ

s

7. AD Converter Characteristics at Ta=-10°C to + 70°C, VSS=0V

Parameter Symbol Pins Conditions

Resolution N 8 bit
Absolute
precision

time
Analog input

voltage range

input current

ET (Note 3) ±1.5 LSB

tCAD

VAIN VSS VDD V

IAINH VAIN=VDD 1 Analog port
IAINL

AN4 - AN7

ADCR2=0 (Note 4) 16 Conversion
ADCR2=1 (N ote 4) 32

VAIN=VSS

Ratings

VDD[V] min. typ. max.

4.5 – 5.5

-1

unit

CYC

t

µ

A

(Note 3) Absolute precision does not include quantizing error (1/2LSB).
(Note 4) Conversion time is the time till the complete digital conversion value for analog input value is set to a register after

the instruction to start conversion is sent.

No.6694-13/20

LC863264/56/48/40A

8. Sample Current Dissipation Characteristics at Ta=-10°C to +70°C, VSS=0V

The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the
recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents
through the output transistors and the pull-up MOS transistors are ignored.

Parameter Symbol Pins Conditions

Current dissipation
during basic
operation

(Note 3)

Current dissipation
in HALT mode

(Note 3)

Current dissipation
in HOLD mode

(Note 3)

IDDOP(1) VDD •FmX’tal=32.768kHz

X’tal oscillation

•System clock :
VCO

•VCO for OSD
operating

•Internal RC
oscillation stops

IDDHALT(1) VDD •HALT mode

•FmX’tal=32.768kHz
X’tal oscillation

•System clock :
VCO

•VCO for OSD stops

•Internal RC
oscillation stops

IDDHALT(2) VDD •HALT mode

•FmX’tal=32.768kHz
X’tal oscillation

•VCO for system
stops

•VCO for OSD stops

•System clock :
Internal RC

IDDHALT(3) VDD •HALT mode

•FmX’tal=32.768kHz
X’tal oscillation

•VCO for system
stops

•VCO for OSD stops

•System clock : X’tal

IDDHOLD VDD •HOLD mode

•All oscillation stops.

Ratings

VDD[V] min. typ. max.

4.5 - 5.5 19 32 mA

4.5 - 5.5 7 12 mA

4.5 - 5.5 300 1200

4.5 - 5.5 50 200

4.5 - 5.5 0.05 20

unit

A

µ

A

µ

(Note 3) The currents through the output transistors and the pull-up MOS transistors are ignored.

No.6694-14/20

LC863264/56/48/40A

Recommended Oscillation Circuit and Sample Characteristics

The sample oscillation circuit characteristics in the table below is based on the following conditions:

Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation

•

board.

Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally.

•

Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C)

Frequency Manufacturer Oscillator

32.768kHz Seiko Epson C-002RX 18pF 18pF Open 390kΩ 4.5 – 5.5V 1.00s 1.50s

Recommended circuit

parameters

C1 C2 Rf Rd

Operating

supply voltage

range

Oscillation

stabilizing

time

typ. max

Notes

Notes The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable

after the following conditions. (Refer to Figure 2.)

1. The VDD becomes higher than the minimum operating voltage after the power is supplied.

2. The HOLD mode is released.

The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator
manufacturer with the following notes in your mind.

Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the

•

oscillation frequency on the production board.
The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C

•

to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability
such as car products, please consult with oscillator manufacturer.
When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo

•

sales personnel.

Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low
gain in order to reduce the power dissipation, refer to the following notices.

The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as

•

possible.
The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND.

•

The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.

•

XT2 XT1

Rf

Rd

C1

C2

X’tal

Figure 1 Recommended oscillation circuit.

No.6694-15/20

LC863264/56/48/40A

Power supply

VDD
VDD limit
0V

RES

Reset time

Internal RC

resonator

oscillation

XT1,XT2

VCO for system

tmsVCO

stable

Operation mode

Unfixed Instruction execution mode Reset

<Reset time and oscillation s tabilizing time>

HOLD release signal

Valid

Internal RC

resonator

oscillation

XT1,XT2

VCO for system

tmsVCO

stable

Operation mode

Instruction executi on mode HOLD

<HOLD release signal and oscillation stabilizing time>

Figure 2 Oscillation stabilizing time

No.6694-16/20

LC863264/56/48/40A

est load

V

CKO

C

C

C

C

CKC

VDD

RES

R

RES

C

RES

(Note) Determine the C

generate more than 200µs reset time.

RES

, R

RES

value to

Figure 3 Reset circuit

<AC timing measurement point>

0.5VDD

Y

SCK0

t

KL

SI0

SO0

SB0

t

t

tI

K

< Timing >

KH

t

t

KI

1KΩ

50pF

< T

DD

>

Figure 4 Serial input / output test condition

No.6694-17/20

LC863264/56/48/40A

tPIH (1)-(4) tPIL (1)-(5)

Figure 5 Pulse input timing condition – 1

HS

VS

tPIL(6)

0.75VDD

0.25VDD
tTLH

tPIL(6)

more than ±1tCYC

Figure 6 Pulse input timing condition - 2

10kΩ

LC863264A

C536 HS

HS

Figure 7 Recommended Interface circuit

No.6694-18/20

LC863264/56/48/40A

C-Video

Noise filter

1µF

CVIN

200Ω

1000pF

Coupling capacitor

Output impedance of C-Video before Noise filter should be less then 100Ω.

Figure 8 CVIN recommended circuit

1M Ω

+

2.2 µ F

-

100Ω

FILT

33000pF

Figure 9 FILT recommended circuit

(Note) Place FILT parts on board as close to the microcontroller as possible.

P S Sr

SDA

tBUF

tHD;STA tR

tF

tHD;STA

tsp

SCL

tLOW

tHD;DAT

tHIGH

tSU;DAT tSU;STA

S : start condition tsp : Spike suppression Standard mode : not exist
P : stop condition High speed mode : less than 50ns
Sr : restart condition

Figure 10 IIC timing

P

tSU;STO

No.6694-19/20

memo:

LC863264/56/48/40A

No.6694-20/20

PS