CMOS LSI
No. *5601
Preliminary
Overview
The LC82151 is a facsimile controller that integrates the
main functions required by facsimile systems on a single
chip. The LC82151 includes a FAX modem with ADPCM
and HDLC functions, image processing functions that can
create high-quality binary image data without external
memory, a CODEC accelerator, a CPU and CPU
peripheral circuits, general-purpose I/O ports, and other
functions. A facsimile system with excellent costperformance characteristics can be created easily by
providing ROM and RAM.
Functions
• CPU and peripheral circuits
– High-speed 16-bit CPU (65C816) operating at
7.4 MHz
– 16-MB program address space
– CODEC accelerator
– Two-channel DMA controller
– Four 16-bit timers
– 16-bit watchdog timer
– TPH interface
– Serial I/O interface
– Parallel I/O: 10 to 43 pins
• Image processing
– Processes 2048 pixels per line
– Processing speed: 540 ns per pixel (maximum)
– Built-in 8-bit A/D converter (Includes a sensor signal
delay function.)
– Sensor drive circuit (Supports CCDs and all major
CIS devices.)
– Distortion correction (White distortion: 8-pixel
averaging correction, black correction: Allows the
black correction subtraction data to be set.)
– γ-correction (Supports user-defined correction curves.)
– Simple binary conversion processing (fixed threshold
and density-adaptive threshold)
– Halftone processing error diffusion method (64 levels)
– Image reduction (decimation, fine black line retention,
and fine white line retention)
LC82151
Single-Chip Facsimile Controller
• Modem
– Group 3 FAX modem
ITU-T V.29 (9600, 7200, and 4800 bps)
ITU-T V.27ter (4800 and 2400 bps)
ITU-T V.21ch2 (300 bps)
– Simultaneous high/low-speed wait function
– Short training function (ITU-T V.27ter only)
– HDLC function (for all transmission speeds)
– Synthesizer function
– Caller ID function
Bell 202 (1200 bps)
ITU-T V.23 (1200 bps)
– ADPCM function
Encoding: 2, 3, or 4 bits
Sampling frequencies: 9.6, 7.2, 4.8, and 3.6 kHz
– RTC low-voltage backup
– 5-V single-voltage power supply
Package Dimension
unit: mm
3214-SQFP144
[LC82151]
SANYO: SQFP144
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
43097 (OT) No. 5601-1/8
Block Diagram
Ø2, RES, R/W,
IRQ, VP, RDY,
BE, NMI, VPA,
VDA, ABCNT
CPU
65C816
LC82151
AIN, ATAP, TEMP, SH, RS, ACLK1,
ACLK2, ASAMP, DAREFH, DAREFL
Image
processing
PXD7 to PXD0
PDREQ, PDACK
RD, WR
ROMCS, RAMCS,
IOCS, MCS
BREQ, BACK, EXRDY
PA7 to PA0
PB2 to PB0
TO0
TO1
RTC, CTS,
DSR, DTR,
RI, DCD
TD, RD
CPU
interface
PIO
Timer
SIO
WDT
Modem
CODEC
accelerator
RTC
DMAC
Interrupt
controller
TXA, RXA,
PGCO, PGCI, V
RIN, VCOI, PHASEO,
EYED, EYECLK,
EYESYNC
ROSC1
ROSC2
INT2
INT8
REF
,
PCK/SCLK,
PDATA/TXD,
EXCLK,
LATCH/RXD,
STB0 to STB3,
HVON
PROTECT
XTAL1, XTAL2,
XOUT,CLKIN,
RESET,
BACKUP
TEST2 to TEST0
TESTOUT
TPH interface
D7 to D0
A19 to A0
DRAM
controller
RAS
CAS
No. 5601-2/8
LC82151
Pin Assignment
Type
I Input pins B
O Output pins P Power pins
Pin No. Pin I/O Pin function
1V
2
3 RDY O ICE ready signal
4 VPA I ICE valid program address signal
5 VDA I ICE valid data address signal
6 A19 O
7 A18 O
8 A17 O
9 A16 O
10 D7 B
11 D6 B
12 D5 B
13 D4 B
14 D3 B
15 D2 B
16 D1 B
17 D0 B
18 V
19 V
20 RD O Read signal from the CPU
21 WR O Write signal from the CPU
22 ROMCS O Program ROM chip select signal
23 RAMCS O Working RAM chip select signal
24 IOCS O External I/O chip select signal
25 MCS O External I/O chip select signal
26 RAS/PG1 B DRAM row address strobe/general-purpose port G
27 CAS/PG2 B DRAM column address strobe/general-purpose port G
28 PA7 B
29 PA6 B
30 PA5 B
31 PA4 B
32 PA3 B
33 PA2 B
34 PA1 B
35 PA0 B
36 V
37 V
38 RIN I PLL bias input
39 PHASEO O PLL phase detector output
40 VCOI I PLL voltage-controlled oscillator input
41 INT8/PB7 B
42 INT2/PB6 B
43 BACK/PB5 B CPU bus acknowledge signal/general-purpose port B
44 BREQ/PB4 B CPU bus request signal/general-purpose port B
45 EXRDY/PB3 B External ready input/general-purpose port B
46 PB2 B
47 PB1 B General-purpose port B
48 PB0 B
49 NMI I Non-maskable interrupt request signal
50 TEST2 I Test pin
SS
VP
DD
SS
SS
DD
P Ground
I ICE vector address signal
Address bus
Data bus
P Power supply
P Ground
General-purpose port A
P Ground
P Power supply
External interrupt request signal/general-purpose port B
Bidirectional pins
NC No connection
Continued on next page.
No. 5601-3/8
LC82151
Continued from preceding page.
Pin No. Pin I/O Pin function
51 TEST1 I
52 TEST0 I Test pins
53 TESTOUT I
54 V
55 V
DD
SS
56 ROSC1 I
57 ROSC2 O
58
BACKUP
59
RESET
60 AV
61 AV
DD
SS
62 AIN I Sensor signal input
63 TEMP I Thermistor input
64 ATAP O A/D converter reference voltage output
65 DAREFH I D/A converter high-level reference voltage input
66 DAREFL I D/A converter low-level reference voltage input
67 TXA O Modem analog transmit output
68 RXA I Modem analog receive input
69 PGCO O Modem gain adjustment output
70 PGCI I Modem gain adjustment input
71 V
72 V
73 V
REF
SS
DD
74 SH O Image sensor start pulse
75 RS O Image sensor reset pulse
76 ACLK1 O
77 ACLK2 O
78 ASAMP O Built-in A/D converter sampling point monitor signal
79 PXD7/PC7 B
80 PXD6/PC6 B
81 PXD5/PC5 B
82 PXD4/PC4 B
83 PXD3/PC3 B
84 PXD2/PC2 B
85 PXD1/PC1 B
86 PXD0/PC0 B
87 PDREQ/PF7 B Image data DMA request signal/general-purpose port F
88
PDACK/PF6
89 EYED/PF5 B Eye pattern data output/general-purpose port F
90 V
91 V
92
93
DD
SS
EYECLK/PF4 B Eye pattern data clock/general-purpose port F
EYESYNC/PF3
94 TO1/PF2 B
95 TO0/PF1 B
96
PCK/SCLK/PE7
97
PDATA/TXD/PE6
98 EXCLK/PE5 B Thermal head control external clock/general-purpose port E
99
LATCH/RXD/PE4
100
STB3/PE3
101
STB2/PE2
102
STB1/PE1
103
STB0/PE0
104 HVON/PF0 B Head power on/off control signal/general-purpose port F
105
PROTECT/PG0
P Power supply
P Ground
RTC crystal oscillator connections
I Low power mode input
I System reset signal
P Analog system power supply
P Analog system ground
I Modem analog block reference input
P Ground
P Power supply
Image sensor data transfer clocks
Image data output/general-purpose port C
B Image data DMA acknowledge signal/general-purpose port F
P Power supply
P Ground
B Eye pattern data synchronizing signal/general-purpose port F
Timer outputs/general-purpose port F
B Thermal head data transfer clock/serial I/O clock/general-purpose port E
B Thermal head serial output data/serial I/O send data/general-purpose port E
B Thermal head data latch signal/serial I/O receive data/general-purpose port E
B
B
Thermal head strobe signal/general-purpose port E
B
B
B Head protection abnormality indication signal input/general-purpose port G
Continued on next page.
No. 5601-4/8
LC82151
Continued from preceding page.
Pin No. Pin I/O Pin function
106 XTAL1 I
107 XTAL2 O
108 V
109 V
SS
DD
110 XOUT O Crystal oscillator clock output
111 CLKIN I System clock input
112 A15 B
113 A14 B
114 A13 B
115 A12 B
116 A11 B
117 A10 B
118 A9 B
119 A8 B
120 TD/PD7 B Serial port transmit data output/general-purpose port D
121 RD/PD6 B Serial port receive data input/general-purpose port D
122 RTS/PD5 B Request to send signal/general-purpose port D
123 CTS/PD4 B Clear to send signal/general-purpose port D
124 DSR/PD3 B Data set ready/general-purpose port D
125 DTR/PD2 B Data terminal ready/general-purpose port D
126 V
127 V
DD
SS
128 RI/PD1 B Ring indicator/general-purpose port D
129 DCD/PD0 B Data carrier detect/general-purpose port D
130 A7 B
131 A6 B
132 A5 B
133 A4 B
134 A3 B
135 A2 B
136 A1 B
137 A0 B
138 ABCNT O ICE bus control signal
139 BE O ICE bus enable signal
140 ø2 O ICE system clock
141 RES O ICE reset signal
142 RWB I ICE read/write signal
143 IRQ O ICE interrupt request signal
144 V
DD
System clock crystal oscillator element connection (29.4912 MHz)
P Ground
P Power supply
Address bus
P Power supply
P Ground
Address bus
P Power supply
No. 5601-5/8
Sample Application
Document
LC82151
NCU
Public telephone
network
Stepping motor
Motor driver
Cutter
Stepping motor
Fluorescent lamp
Image
sensor
Lens
Temperature
sensor
Thermal head
Paper
Facsimile
controller
LC82151
Telephone
RAM
ROM
To LCD
To key matrix
No. 5601-6/8
LC82151
Specifications
Absolute Maximum Ratings at Ta = 25°C, V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
Input and output voltage V
Allowable power dissipation Pd max Ta ≤70°C 550 mW
Operating temperature Topr –30 to +70 °C
Storage temperature Tstg –55 to +125 °C
Soldering temperature
max –0.3 to +7.0 V
DD
, V
I
O
= 0 V
SS
–0.3 to VDD+0.3 V
Manual soldering (3 seconds) 350 °C
Reflow soldering (10 seconds) 235 °C
Allowable Operating Ranges at Ta = –30 to +70°C, V
Parameter Symbol Conditions
Supply voltage V
Input voltage V
DD
IN
SS
= 0 V
Electrical Characteristics at Ta = –30 to +70°C, VDD= 4.5 to 5.5 V
Parameter Symbol Conditions
Input high-level voltage V
Input low-level voltage V
Input leakage current I
Output high-level voltage V
Output low-level voltage V
Output leakage current I
Charge pump output current
Vref input voltage V
Vref impedance V
Input voltage range V
Operating voltage range V
Output impedance R
Oscillator frequency
Current drain
IH1
IL1
L
OHIOH
OLIOL
OZ
I
POZ
I
NOZ
REFVREF
REFVREF
IA
OA
O
f
CLK1
f
CLK2
I
DD1
I
DD2
= –4mA 2.4 V
= 4mA 0.4 V
When outputs are high impedance –10 +10 µA
PHASEO = 2 V 7 15 27 mA
PHASEO = 2 V –8 –15 –28 mA
RXA, PGCI V
TXA, PGCO V
TXA, PGCO 7.0 kΩ
XTAL1, XTAL2, CLKIN 29.4912 MHz
ROSC1, ROSC 2 32.768 kHz
Operating 100 mA
In backup mode, VDD= 2.5 V, BACKUP = 0
Ratings
min typ max
4.5 5.5 V
0V
Ratings
min typ max
2.2 V
–10 +10 µA
VDD/2 V
1MΩ
× 0.2 V
DD
× 0.2 V
DD
× 0.8 V
DD
× 0.8 V
DD
5µA
Unit
DD
Unit
0.8 V
V
Power on Timing
Applications must control the timing of the power on sequence carefully. Although AVSSand VSSare completely
isolated internally in the LC82151, AVDDand VDDare connected through the substrate. This means that there must be
no potential difference between AVDDand VDD. Also, the power supply voltage rise and fall times must be under 3 ms.
Analog Characteristic
D/A Converter
Parameter Symbol Conditions
Resolution 6 bit
Reference resistors value DAREFL, DAREFH 5.0 kΩ
min typ max
Ratings
Unit
A/D Converter at an ATAP potential of 4.2 V
A/D Converter
Parameter Symbol Conditions
Resolution 8 bit
Linearity error ±1 LSB
Differential linearity error ±1 LSB
min typ max
Ratings
Unit
No. 5601-7/8
LC82151
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of April, 1997. Specifications and information herein are subject to change
without notice.
No. 5601-8/8
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