Page 1
Ordering number : ENN6266A
51003AS / D2599TH (OT) No. 6266-1/37
Overview
The LC75804E and LC75804W are 1/3 duty and 1/4 duty
LCD display drivers that can directly drive up to 300
segments and can control up to eight general-purpose
output ports. These products also incorporate a key scan
circuit that accepts input from up to 30 keys to reduce
printed circuit board wiring.
Features
• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
• 1/3 duty and 1/4 duty drive schemes can be controlled
from serial data.
• 1/2 bias and 1/3 bias drive schemes can be controlled
from serial data.
• Capable of driving up to 228 segments using 1/3 duty
and up to 300 segments using 1/4 duty.
• Sleep mode and all segments off functions that are
controlled from serial data.
• Segment output port/general-purpose output port
function switching that is controlled from serial data.
• Serial data I/O supports CCB format communication
with the system controller.
• Direct display of display data without the use of a
decoder provides high generality.
• Independent V
LCD
for the LCD driver block (V
LCD
can
be set to in the range VDD– 0.5 to 6.0 volts.)
• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
• RES pin provided for forcibly initializing the IC internal
circuits.
• RC oscillator circuit.
Package Dimensions
unit: mm
3151A-QFP100E
unit: mm
3181C-SQFP100
20.0
23.2
14.0
17.2
0.15
0.8
(2.7)
3.0max
0.1
0.3
0.65
(0.58)
130
80 51
31
50
100
81
SANYO: QFP100E(QIP100E)
[LC75804E]
14.0
16.0
14.0
16.0
0.145
0.2
0.5
(1.0)
(1.4)
1.6max
0.1
0.5
125
26
50
5175
76
100
SANYO: SQFP100
[LC75804W]
LC75804E, LC75804W
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
1/3, 1/4 Duty LCD Display Drivers
with Key Input Function
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Page 2
No. 6266-2/37
LC75804E, LC75804W
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage
V
DD
max V
DD
–0.3 to +7.0 V
V
LCD
max V
LCD
–0.3 to +7.0
V
IN
1 CE, CL, DI, RES –0.3 to +7.0
Input voltage V
IN
2 OSC,TEST –0.3 to VDD+0.3 V
V
IN
3 V
LCD
1, V
LCD
2, KI1 to KI5 –0.3 to V
LCD
+0.3
V
OUT
1 DO –0.3 to +7.0
Output voltage V
OUT
2 OSC –0.3 to VDD+0.3 V
V
OUT
3 S1 to S76, COM1 to COM4, KS1 to KS6, P1 to P8 –0.3 to V
LCD
+0.3
I
OUT
1 S1 to S76 300 µA
Output current
I
OUT
2 COM1 to COM4 3
I
OUT
3 KS1 to KS6 1 mA
I
OUT
4 P1 to P8 5
Allowable power dissipation Pd max Ta = 85°C 200 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Specifications
Absolute Maximum Ratings at Ta=25°C, VSS=0V
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage
V
DDVDD
4.5 6.0
V
V
LCDVLCD
VDD– 0.5 6.0
Input voltage
V
LCD
1 V
LCD
1 2/3 V
LCD
V
LCD
V
V
LCD
2 V
LCD
2 1/3 V
LCD
V
LCD
Input high level voltage
V
IH
1 CE, CL, DI, RES 0.8 V
DD
6.0
V
V
IH
2 KI1 to KI5 0.6 V
DD
V
LCD
Input low level voltage V
IL
CE, CL, DI, RES, KI1 to KI5 0 0.2 V
DD
V
Recommended external resistance R
OSC
OSC 39 kΩ
Recommended external capacitance C
OSC
OSC 1000 pF
Guaranteed oscillator range f
OSC
OSC 19 38 76 kHz
Data setup time t
ds
CL, DI :Figure 2 160 ns
Data hold time t
dh
CL, DI :Figure 2 160 ns
CE wait time t
cp
CE, CL :Figure 2 160 ns
CE setup time t
cs
CE, CL :Figure 2 160 ns
CE hold time t
ch
CE, CL :Figure 2 160 ns
High level clock pulse width tø
H
CL :Figure 2 160 ns
Low level clock pulse width tø
L
CL :Figure 2 160 ns
Rise time t
r
CE, CL, DI :Figure 2 160 ns
Fall time t
f
CE, CL, DI :Figure 2 160 ns
DO output delay time t
dc
DO RPU=4.7 kΩ, CL=10pF *1:Figure 2 1.5 µs
DO rise time t
dr
DO RPU=4.7 kΩ, CL=10pF *1:Figure 2 1.5 µs
Allowable Operating Ranges at Ta = –40 to +85°C, VSS=0V
Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPUand the load capacitance CL.
Page 3
No. 6266-3/37
LC75804E, LC75804W
Parameter Symbol Conditions
Ratings
Unit
min typ max
Hysteresis V
H
CE, CL, DI, RES, KI1 to KI5 0.1 V
DD
V
Power-down detection voltage V
DET
2.5 3.0 3.5 V
Input high level current I
IH
CE, CL, DI, RES: VI= 6.0 V 5.0 µA
Input low level current I
IL
CE, CL, DI, RES: VI= 0 V –5.0 µA
Input floating voltage V
IF
KI1 to KI5 0.05 V
DD
V
Pull-down resistance R
PD
KI1 to KI5: VDD= 5.0 V 50 100 250 kΩ
Output off leakage current I
OFFH
DO: VO = 6.0 V 6.0 µA
V
OH
1 KS1 to KS6: IO= –500 µA V
LCD
– 1.0 V
LCD
– 0.5 V
LCD
– 0.2
Output high level voltage
V
OH
2 P1 to P8: IO= –1 mA V
LCD
– 1.0
V
V
OH
3 S1 to S76: IO= –20 µA V
LCD
– 1.0
V
OH
4 COM1 to COM4: IO= –100 µA V
LCD
– 1.0
V
OL
1 KS1 to KS6: IO= 25 µA 0.2 0.5 1.5
V
OL
2 P1 to P8: IO= 1 mA 1.0
Output low level voltage V
OL
3 S1 to S76: IO= 20 µA 1.0 V
V
OL
4 COM1 to COM4: IO= 100 µA 1.0
V
OL
5 DO: IO= 1 mA 0.1 0.5
V
MID
1 COM1 to COM4: 1/2 bias, IO= ±100 µA
1/2 V
LCD
– 1.0 1/2 V
LCD
+ 1.0
V
MID
2 S1 to S76: 1/3 bias,IO= ±20 µA
2/3 V
LCD
– 1.0 2/3 V
LCD
+ 1.0
Output middle level voltage *
2
V
MID
3 S1 to S76: 1/3 bias, IO= ±20 µA
1/3 V
LCD
– 1.0 1/3 V
LCD
+ 1.0
V
V
MID
4 COM1 to COM4: 1/3 bias,IO= ±100 µA
2/3 V
LCD
– 1.0 2/3 V
LCD
+ 1.0
V
MID
5 COM1 to COM4: 1/3 bias,IO= ±100 µA
1/3 V
LCD
– 1.0 1/3 V
LCD
+ 1.0
Oscillator frequency fosc OSC: R
OSC
= 39 kΩ, C
OSC
= 1000 pF 30.4 38 45.6 kHz
I
DD
1 VDD:Sleep mode 100
I
DD
2 VDD: VDD= 6.0 V, output open,fosc = 38 kHz 270 540
Current drain
I
LCD
1 V
LCD
: Sleep mode 5
µA
I
LCD
2
V
LCD
: V
LCD
= 6.0 V, output open, 1/2 bias,
200 400
fosc = 38 kHz
I
LCD
3
V
LCD
: V
LCD
= 6.0 V, output open, 1/3 bias,
120 240
fosc = 38 kHz
Electrical Characteristics for the Allowable Operating Ranges
Nete: *2. Excluding the bias voltage generation divider resistor built into V
LCD
1 and V
LCD
2. (See Figure 1.)
Page 4
Figure 1
1. When CL is stopped at the low level
Figure 2
No. 6266-4/37
LC75804E, LC75804W
VLCD
VLCD2
V
LCD1
tdh
50%
VIH1
VIH1
VIL
VIL
VIH1
VIL
tdrtdc
tchtcstcp
tds
tr
CL
t Lt ø H
tf
DO
DI
D1D0
CE
ø
2. When CL is stopped at the high level
50%
VIH1
VIL
tdh
VIH1
VIL
VIH1
VIL
tdrtdc
tchtcstcp
tds
tf
CL
tø Htø L
tr
DO
DI
D1D0
CE
To the common segment driver
Excluding these registors.
Page 5
Pin Assignments
No. 6266-5/37
LC75804E, LC75804W
KI1
VDD
VLCD2
P4/S4
S10
S16
S21
S15
S34
S39
S44
S59
S58
S49
S50
S51
S52
S53
S54
S55
S56
S57
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
COM4/S74
COM3
COM2
COM1
KS1/S75
P3/S3
S9
P2/S2
P1/S1
DI
CL
LC75804E
(QFP100E)
S76/KS2
KS6
KS3
KS4
KS5
KI2
KI3
KI5
KI4
VLCD
VLCD1
VSS
TEST
RES
OSC
DO
S33
S32
S31
S30
S29CE
5180
5081
31100
30
(Top view)
(Top view)
1
P8/S8
P7/S7
P6/S6
P5/S5
S14
S20
S13
S12
S11
S19
S18
S17
S25
S24
S23
S22
S28
S27
S26
S38
S37
S36
S35
S43
S42
S41
S40
S48
S47
S46
S45
S55
S51
S52
S53
S54
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
COM4/S74
COM3
P5/S5
S11
P4/S4
P3/S3
P2/S2
P1/S1
LC75804W
(SQFP100)
COM1
S76/KS2
S75/KS1
KS3
COM2
KS4
KS5
KS6
KI2
KI1
KI4
KI3
S35
S34
S33
S32
S31
S29
S30
S27
S28
S26DI
5175
5076
26100
251
KI5
VLCD
VDD
VLCD2
VLCD1
VSS
OSC
TEST
RES
CE
DO
CL
S10
S9
P8/S8
P7/S7
P6/S6
S16
S22
S15
S14
S13
S12
S21
S20
S19
S18
S17
S25
S24
S23
S40
S39
S38
S37
S36
S45
S44
S43
S42
S41
S50
S49
S48
S47
S46
Page 6
Block Diagram
No. 6266-6/37
LC75804E, LC75804W
VDET
CCB
INTERFACE
COM4/S74
COM3
COM2
COM1
COMMON
DRIVER
CLOCK
GENERATOR
VSS
VLCD2
VLCD1
VLCD
CE
VDD
DI
TEST
CL
DO
OSC
RES
KI5
KI4
KI3
KI2
KI1
KS6
KS5
KS4
KS3
S76/KS2
S75/KS1
KEY SCAN
KEY BUFFER
CONTROL
REGISTER
SHIFT REGISTER
SEGMENT DRIVER & LATCH
S1/P1
S2/P2
S8/P8
S9
S73
Page 7
No. 6266-7/37
LC75804E, LC75804W
Pin
Pin No.
Function Active I/O
Handling
LC75804E LC75804W
when unused
—
●● OPEN
COM1
COM2
— ●● OPEN
COM3
COM4/S74
KS1/S75 80 78
KS2/S76 81 79 — O OPEN
KS3 to KS6 82 to 85 80 to 83
KI1 to KI5 86 to 90 84 to 88 H I GND
OSC 97 95 — I/O V
DD
CE 100 98 H I
CL 1 99 I GND
DI 2 100 — I
DO 99 97 — O OPEN
RES 98 96 L I V
DD
TEST 96 94 This pin must be connected to ground. — I —
V
LCD
1 93 91 — I OPEN
V
LCD
2 94 92 — I OPEN
V
DD
91 89 — — —
V
LCD
92 90 — — —
V
SS
95 93 Power supply connection. Connect to ground. — — —
Pin Functions
Segment outputs for displaying the display data transferred by serial
data input.
The S1/P1 to S8/P8 pins can be used as general-purpose output ports
under serial data control.
Common driver outputs
The frame frequency fo is given by : fo = (f
OSC
/384)Hz.
The COM4/S74 pin can be used as a segment output in 1/3 duty.
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in
the timing lines to prevent shorts, since these outputs are unbalanced
CMOS transistor outputs, these outputs will not be damaged by shorting
when these outputs are used to form a key matrix. The KS1/S75 and
KS2/S76 pins can be used as segment outputs when so specified by
the control data.
Key scan inputs
These pins have built-in pull-down resistors.
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin.
Serial data interface connections to the controller. Note that DO, being
an open-drain output, requires a pull-up resistor.
CE :Chip enable
CL :Synchronization clock
DI :Transfer data
DO :Output data
▲
Reset signal input
RES = low
.....
Display off
Key scan disabled
All key data is reset to low
RES = high
....
Display on
Key scan enabled
However, serial data can be transferred when RES is low.
Used for applying the LCD drive 2/3 bias voltage externally. Must be
connected to V
LCD
2 when a 1/2 bias drive scheme is used.
Used for applying the LCD drive 1/3 bias voltage externally. Must be
connected to V
LCD
1 when a 1/2 bias drive scheme is used.
Logic block power supply connection. Provide a voltage of between 4.5
and 6.0V.
LCD driver block power supply connection. Provide a voltage of
between V
DD
– 0.5 and 6.0V.
S1/P1 to
S8/P8
S9 to S73
3 to 10
11 to 75
1 to 8
9 to 73
79
78
77
76
77
76
75
74
Page 8
Serial Data Input
1. 1/3 duty
① When CL is stopped at the low level
Note: B0 to B3, A0 to A3
......
CCB address
DD
................................
Direction data
No. 6266-8/37
LC75804E, LC75804W
A3A2A1A0B3B2B1B0
00
DRSC
P3P2P1P0K1K0S1S0 DT000
D78D77D76D75D74D73D2D1
01000010
DD
DO
DI
CL
CE
00
A3A2A1A0B3B2B1B0
1000000000000000
D153D152D151D80D79
01000010
DD
00000
A3A2A1A0B3B2B1B0
0100000000000000
D228D227D226D155D154
01000010
DD
00000
Display data Control data
Fixed data
Display data
Fixed data
Display data
Page 9
No. 6266-9/37
LC75804E, LC75804W
② When CL is stopped at the high level
Note: B0 to B3, A0 to A3
......
CCB address
DD
................................
Direction data
CCB address
............
42H
D1 to D228
..............
Display data
S0, S1
......................
Sleep control data
K0, K1
......................
Key scan output/segment output selection data
P0 to P3
..................
Segment output port/general-purpose output port selection data
SC
............................
Segment on/off control data
DR
............................
1/2 bias or 1/3 bias drive selection data
DT
............................
1/3 duty or 1/4 duty drive selection data
A3A2A1A0B3B2B1B0
00
DT
DRSCP3P2P1P0K1K0S1S0000
D78D77D76D75D74D73D2D1
01000010
DD
DO
DI
CL
CE
00
A3A2A1A0B3B2B1B0
1000000000000000
D153D152D151D80D79
01000010
DD
00000
A3A2A1A0B3B2B1B0
0100000000000000
D228D227D226D155D154
01000010
DD
00000
Display data
Control data
Fixed data
Display data
Display data
Fixed data
Page 10
No. 6266-10/37
LC75804E, LC75804W
2. 1/4duty
① When CL is stopped at the low level
Note: B0 to B3, A0 to A3
......
CCB address
DD
................................
Direction data
A3A2A1A0B3B2B1B0
00DRSCP3P2P1P0K1K0S1S0 DT000
D76D75D74D72 D73D1
01000010
DD
DO
DI
CL
CE
0000
A3A2A1A0B3B2B1B0
1000000000000000
D152D151D150D148 D149 D77
01000010
DD
0000
A3A2A1A0B3B2B1B0
0100000000000000
D228D227D226D224 D225D153
01000010
DD
0000
A3A2A1A0B3B2B1B0
110000000000000001000010
DD
00000
D300
D229
000
Display data
Control data
Fixed data
Display data
Display data
Display data
Fixed data
Fixed data
Page 11
No. 6266-11/37
LC75804E, LC75804W
② When CL is stopped at the high level
Note: B0 to B3, A0 to A3
......
CCB address
DD
................................
Direction data
CCB address
............
42H
D1 to D300
..............
Display data
S0, S1
......................
Sleep control data
K0, K1
......................
Key scan output/segment output selection data
P0 to P3
..................
Segment output port/general-purpose output port selection data
SC
............................
Segment on/off control data
DR
............................
1/2 bias or 1/3 bias drive selection data
DT
............................
1/3 duty or 1/4 duty drive selection data
A3A2A1A0B3B2B1B0
00DTDRSCP3P2P1P0K1K0S1S0
000
D76D75D74D72 D73
D1
01000010
DD
DO
DI
CL
CE
0000
A3A2A1A0B3B2B1B0
1000000000000000
D152D151D150D148 D149
D77
01000010
DD
0000
A3A2A1A0B3B2B1B0
0100000000000000
D228D227D226D224 D225
D153
01000010
DD
0000
A3A2A1A0B3B2B1B0
1100000000000000
D300D229
01000010
DD
00000000
Display data
Control data
Fixed data
Display data
Display data
Display data
Fixed data
Fixed data
Page 12
Control Data Functions
1. S0, S1 : Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan
outputs during key scan standby.
Note: This assumes that the KS1/S75 and KS2/S76 output pins are selected for key scan output.
No. 6266-12/37
LC75804E, LC75804W
Control data
Mode OSC oscillator
Segment outputs
Output pin states during key scan standby
S0 S1
Common outputs
KS1 KS2 KS3 KS4 KS5 KS6
0 0 Normal Operating Operating H H H H H H
0 1 Sleep Stopped L L L L L L H
1 0 Sleep Stopped L L L L L H H
1 1 Sleep Stopped L H H H H H H
2. K0, K1 : Key scan output /segment output selection data
These control data bits switch the functions of the KS1/S75 and KS2/S76 output pins between key scan output and
segment output.
X: don’t care
Note: KSn(n = 1 or 2) : Key scan output
Sn (n = 75 or 76): Segment output
Control data Output pin state
Maximum number of
K0 K1 KS1/S75 KS2/S76
input keys
0 0 KS1 KS2 30
0 1 S75 KS2 25
1 X S75 S76 20
3. P0 to P3 : Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S8/P8 output pins between the segment output port and
the general-purpose output port.
Note: Sn(n=1 to 8): Segment output port
Pn(n=1 to 8): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to
be general-purpose output ports.
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level (V
LCD
) when the display data D13 is 1, and will output a low level
(Vss) when D13 is 0.
Control data Output pin state
P0 P1 P2 P3 S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8
0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8
0 0 0 1 P1 S2 S3 S4 S5 S6 S7 S8
0 0 1 0 P1 P2 S3 S4 S5 S6 S7 S8
0 0 1 1 P1 P2 P3 S4 S5 S6 S7 S8
0 1 0 0 P1 P2 P3 P4 S5 S6 S7 S8
0 1 0 1 P1 P2 P3 P4 P5 S6 S7 S8
0 1 1 0 P1 P2 P3 P4 P5 P6 S7 S8
0 1 1 1 P1 P2 P3 P4 P5 P6 P7 S8
1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8
Output pin
Corresponding display data
1/3 duty 1/4 duty
S1/P1 D1 D1
S2/P2 D4 D5
S3/P3 D7 D9
S4/P4 D10 D13
S5/P5 D13 D17
S6/P6 D16 D21
S7/P7 D19 D25
S8/P8 D22 D29
Page 13
No. 6266-13/37
LC75804E, LC75804W
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
SC Display state
0 on
1 off
4. SC : Segment on/off control data
This control data bit controls the on/off state of the segments.
DR Bias drive scheme
0 1/3 bias drive
1 1/2 bias drive
5. DR : 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DT Duty drive scheme Output pin state (COM4/S74)
0 1/4 duty drive COM4
1 1/3 duty drive S74
6. DT : 1/3 duty or 1/4 duty drive selection data
This control data bit switches between LCD 1/3 duty or 1/4 duty drive.
Note: COM4: Common output
S74 : Segment output
Display Data and Output Pin Correspondence
1. 1/3 duty
Note: This is for the case where the output pins S1/P1 to S8/P8, COM4/S74, KS1/S75 and KS2/S76 are selected for use as segment outputs.
Output pin COM1 COM2 COM3
S1/P1 D1 D2 D3
S2/P2 D4 D5 D6
S3/P3 D7 D8 D9
S4/P4 D10 D11 D12
S5/P5 D13 D14 D15
S6/P6 D16 D17 D18
S7/P7 D19 D20 D21
S8/P8 D22 D23 D24
S9 D25 D26 D27
S10 D28 D29 D30
S11 D31 D32 D33
S12 D34 D35 D36
S13 D37 D38 D39
S14 D40 D41 D42
S15 D43 D44 D45
S16 D46 D47 D48
S17 D49 D50 D51
S18 D52 D53 D54
S19 D55 D56 D57
S20 D58 D59 D60
S21 D61 D62 D63
S22 D64 D65 D66
S23 D67 D68 D69
S24 D70 D71 D72
S25 D73 D74 D75
S26 D76 D77 D78
Output pin COM1 COM2 COM3
S53 D157 D158 D159
S54 D160 D161 D162
S55 D163 D164 D165
S56 D166 D167 D168
S57 D169 D170 D171
S58 D172 D173 D174
S59 D175 D176 D177
S60 D178 D179 D180
S61 D181 D182 D183
S62 D184 D185 D186
S63 D187 D188 D189
S64 D190 D191 D192
S65 D193 D194 D195
S66 D196 D197 D198
S67 D199 D200 D201
S68 D202 D203 D204
S69 D205 D206 D207
S70 D208 D209 D210
S71 D211 D212 D213
S72 D214 D215 D216
S73 D217 D218 D219
COM4/S74 D220 D221 D222
KS1/S75 D223 D224 D225
KS2/S76 D226 D227 D228
Output pin COM1 COM2 COM3
S27 D79 D80 D81
S28 D82 D83 D84
S29 D85 D86 D87
S30 D88 D89 D90
S31 D91 D92 D93
S32 D94 D95 D96
S33 D97 D98 D99
S34 D100 D101 D102
S35 D103 D104 D105
S36 D106 D107 D108
S37 D109 D110 D111
S38 D112 D113 D114
S39 D115 D116 D117
S40 D118 D119 D120
S41 D121 D122 D123
S42 D124 D125 D126
S43 D127 D128 D129
S44 D130 D131 D132
S45 D133 D134 D135
S46 D136 D137 D138
S47 D139 D140 D141
S48 D142 D143 D144
S49 D145 D146 D147
S50 D148 D149 D150
S51 D151 D152 D153
S52 D154 D155 D156
Page 14
No. 6266-14/37
LC75804E, LC75804W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31 D32 D33
0 0 0 The LCD segments for COM1, COM2 and COM3 are off.
0 0 1 The LCD segment for COM3 is on.
0 1 0 The LCD segment for COM2 is on.
0 1 1 The LCD segments for COM2 and COM3 are on.
1 0 0 The LCD segment for COM1 is on.
1 0 1 The LCD segments for COM1 and COM3 are on.
1 1 0 The LCD segments for COM1 and COM2 are on.
1 1 1 The LCD segments for COM1, COM2 and COM3 are on.
2. 1/4 duty
Output pin COM1 COM2 COM3 COM4
S1/P1 D1 D2 D3 D4
S2/P2 D5 D6 D7 D8
S3/P3 D9 D10 D11 D12
S4/P4 D13 D14 D15 D16
S5/P5 D17 D18 D19 D20
S6/P6 D21 D22 D23 D24
S7/P7 D25 D26 D27 D28
S8/P8 D29 D30 D31 D32
S9 D33 D34 D35 D36
S10 D37 D38 D39 D40
S11 D41 D42 D43 D44
S12 D45 D46 D47 D48
S13 D49 D50 D51 D52
S14 D53 D54 D55 D56
S15 D57 D58 D59 D60
S16 D61 D62 D63 D64
S17 D65 D66 D67 D68
S18 D69 D70 D71 D72
S19 D73 D74 D75 D76
S20 D77 D78 D79 D80
S21 D81 D82 D83 D84
S22 D85 D86 D87 D88
S23 D89 D90 D91 D92
S24 D93 D94 D95 D96
S25 D97 D98 D99 D100
S26 D101 D102 D103 D104
S27 D105 D106 D107 D108
S28 D109 D110 D111 D112
S29 D113 D114 D115 D116
S30 D117 D118 D119 D120
S31 D121 D122 D123 D124
S32 D125 D126 D127 D128
S33 D129 D130 D131 D132
S34 D133 D134 D135 D136
S35 D137 D138 D139 D140
S36 D141 D142 D143 D144
S37 D145 D146 D147 D148
S38 D149 D150 D151 D152
Output pin COM1 COM2 COM3 COM4
S39 D153 D154 D155 D156
S40 D157 D158 D159 D160
S41 D161 D162 D163 D164
S42 D165 D166 D167 D168
S43 D169 D170 D171 D172
S44 D173 D174 D175 D176
S45 D177 D178 D179 D180
S46 D181 D182 D183 D184
S47 D185 D186 D187 D188
S48 D189 D190 D191 D192
S49 D193 D194 D195 D196
S50 D197 D198 D199 D200
S51 D201 D202 D203 D204
S52 D205 D206 D207 D208
S53 D209 D210 D211 D212
S54 D213 D214 D215 D216
S55 D217 D218 D219 D220
S56 D221 D222 D223 D224
S57 D225 D226 D227 D228
S58 D229 D230 D231 D232
S59 D233 D234 D235 D236
S60 D237 D238 D239 D240
S61 D241 D242 D243 D244
S62 D245 D246 D247 D248
S63 D249 D250 D251 D252
S64 D253 D254 D255 D256
S65 D257 D258 D259 D260
S66 D261 D262 D263 D264
S67 D265 D266 D267 D268
S68 D269 D270 D271 D272
S69 D273 D274 D275 D276
S70 D277 D278 D279 D280
S71 D281 D282 D283 D284
S72 D285 D286 D287 D288
S73 D289 D290 D291 D292
KS1/S75 D293 D294 D295 D296
KS2/S76 D297 D298 D299 D300
Note: This is for the case where the output pins S1/P1 to S8/P8, KS1/S75 and KS2/S76 are selected for use as segment outputs.
Page 15
For example, the table below lists the segment output states for the S11 output pin.
No. 6266-15/37
LC75804E, LC75804W
Display data
Output pin state (S11)
D41 D42 D43 D44
0 0 0 0 The LCD segments for COM1,COM2,COM3 and COM4 are off.
0 0 0 1 The LCD segment for COM4 is on.
0 0 1 0 The LCD segment for COM3 is on.
0 0 1 1 The LCD segments for COM3 and COM4 are on.
0 1 0 0 The LCD segment for COM2 is on.
0 1 0 1 The LCD segments for COM2 and COM4 are on.
0 1 1 0 The LCD segments for COM2 and COM3 are on.
0 1 1 1 The LCD segments for COM2,COM3 and COM4 are on.
1 0 0 0 The LCD segment for COM1 is on.
1 0 0 1 The LCD segments for COM1 and COM4 are on.
1 0 1 0 The LCD segments for COM1 and COM3 are on.
1 0 1 1 The LCD segments for COM1,COM3 and COM4 are on.
1 1 0 0 The LCD segments for COM1 and COM2 are on.
1 1 0 1 The LCD segments for COM1,COM2 and COM4 are on.
1 1 1 0 The LCD segments for COM1,COM2 and COM3 are on.
1 1 1 1 The LCD segments for COM1,COM2,COM3 and COM4 are on.
Serial Data Output
1. When CL is stopped at the low level
Note: B0 to B3, A0 to A3······CCB address
CE
A3A2A1A0B3B2B1B0
KD2KD1X SA
KD30KD29KD28KD27
01000011
DO
DI
CL
X: don't care
2. When CL is stopped at the high level
Note: B0 to B3, A0 to A3······CCB address
CCB address
......
43H
KD1 to KD30
........
Key data
SA
........................
Sleep acknowledge data
CE
A3A2A1A0B3B2B1B0
KD3KD2KD1X XSA
KD30KD29KD28
01000011
DO
DI
CL
X: don't care
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
Output data
Output data
Page 16
Output Data
1. KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
When the KS1/S75 and KS2/S76 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S8/P8 outputs can be used as general-purpose output ports according to the state of the P0 to P3 control data
bits, even in sleep mode. (See the control data description for details.)
No. 6266-16/37
LC75804E, LC75804W
KI1 KI2 KI3 KI4 KI5
KS1/S75 KD1 KD2 KD3 KD4 KD5
KS2/S76 KD6 KD7 KD8 KD9 KD10
KS3 KD11 KD12 KD13 KD14 KD15
KS4 KD16 KD17 KD18 KD19 KD20
KS5 KD21 KD22 KD23 KD24 KD25
KS6 KD26 KD27 KD28 KD29 KD30
Page 17
2. In normal mode
• The pins KS1 to KS6 are set high.
• When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
• If a key is pressed for longer than 615T(s) (Where T= ) the LC75804E/W outputs a key data read request (a
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75804E/W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10 kΩ).
No. 6266-17/37
LC75804E, LC75804W
Key on
576T[s]
*3
*3
*3
*3
*3
*3
*3 *3
*3
1 1
22
3
4 4
55
66
KS5
KS4
KS3
KS6
KS2
KS1
*3
T=
1
fosc
DI
DO
CE
615T[s]615T[s] 615T[s]
T=
1
fosc
Note: *3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from
pins that are set low.
1
——
fosc
Key Scan Operation Functions
1. Key scan timing
The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75804E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75804E/W cannot detect a key press shorter than 615T(s).
Key input 1
Key input 2
Key scan
Key data read request
Key data read request
Key data read request
Key data read Key data read Key data read
Serial data transfer
Serial data transfer Serial data transfer
Key address (43H)
Key address
Key address
3
Page 18
No. 6266-18/37
LC75804E, LC75804W
3. In sleep mode
• The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
• If a key is pressed for longer than 615T(s)(Where T= ) the LC75804E/W outputs a key data read request (a
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75804E/W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 kΩ).
• Sleep mode key scan example
Example: S0 = 0, S1 = 1 (sleep with only KS6 high)
Multiple Key Presses
Although the LC75804E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
KI1
KI2
KI3
KI4
KI5
*4
[L] KS1
[L] KS2
[L] KS3
[L] KS4
[L] KS5
[H] KS6
DO
DI
CE
615T[s] 615T[s]
T=
1
fosc
1
——
fosc
Note: *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5
lines are pressed at the same time.
When any one of these keys is pressed,
the oscillator on the OSC pin is started
and the keys are scanned.
Key input
(KS6 line)
Key scan
Key data read request
Key data read
Serial data transfer
Key address (43H)
Key address
Key data read request
Key data read
Serial data transfer
Serial data transfer
Page 19
COM1
1/3 Duty, 1/2 Bias Drive Technique
COM2
COM3
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are turned off.
LCD driver output when only LCD segments
corresponding to COM1 are on
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are on.
1/3 Duty, 1/2 Bias Waveforms
No. 6266-19/37
LC75804E, LC75804W
VLCD1,VLCD2
VLCD
0V
[Hz]
fosc
384
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
Page 20
No. 6266-20/37
LC75804E, LC75804W
COM1
1/3 Duty, 1/3 Bias Drive Technique
COM2
COM3
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are turned off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2 and COM3 are on.
1/3 Duty, 1/3 Bias Waveforms
[Hz]
fosc
384
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
Page 21
No. 6266-21/37
LC75804E, LC75804W
COM1
1/4 Duty, 1/2 Bias Drive Technique
COM2
COM3
COM4
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/2 Bias Waveforms
VLCD1,VLCD2
VLCD
0V
fosc
384
[Hz]
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
VLCD1,VLCD2
VLCD
0V
Page 22
No. 6266-22/37
LC75804E, LC75804W
COM1
1/4 Duty, 1/3 Bias Drive Technique
COM2
COM3
COM4
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/3 Bias Waveforms
VLCD1
VLCD2
fosc
384
[Hz]
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
VLCD1
VLCD2
VLCD
0V
Page 23
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage VDDrise time when the logic block power is first applied and the
logic block power supply voltage VDDfall time when the voltage drops are both at least 1 ms.
(See Figure 3 and Figure 4.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3 and Figure 4.)
• Power on :Logic block power supply(VDD) on → LCD driver block power supply(V
LCD
) on
• Power off:LCD driver block power supply(V
LCD
) off → Logic block power supply(VDD) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75804E/W supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset methods
(1) Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage VDDrise time when logic block power is applied, a system
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is
assured as the logic block supply voltage VDDfall time when logic block power drops, a system reset will be applied in
the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the
point when all the serial data (1/3 duty: the display data D1 to D228 and the control data, 1/4 duty: the display data D1 to
D300 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data,
after all the direction data has been transferred. However, the above operations will be performed regardless of the state
(high or low) of the RES pin. If RES is high, the reset will be cleared at the point the above operations are completed. On
the other hand, if RES is low, the system will remain in the reset period as long as RES is not set high, even if the above
operations are completed. (See Figure 3 and Figure 4.)
No. 6266-23/37
LC75804E, LC75804W
Page 24
No. 6266-24/37
LC75804E, LC75804W
VDD
CE
VLCD
VIL
t3t2 t4t1
VDET
VDET
D1 to D78
S0, S1, K0, K1
P0 to P3, SC, DR, DT
Internal data (D79 to D153)
Internal data (D154 to D228)
Internal data
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDDrise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage V
DD
fall time)
• 1/3 duty
VIL
t3t2 t4t1
VDET
VDET
VDD
CE
VLCD
D1 to D76
S0, S1, K0, K1
P0 to P3, SC, DR, DT
Internal data (D77 to D152)
Internal data (D153 to D228)
Internal data
Internal data (D229 to D300)
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDDrise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage V
DD
fall time)
Figure 4
• 1/4 duty
Display and control data transfer
Undefined
Undefined
Undefined
Defined
Defined
Defined
Undefined
Undefined
Undefined
System reset period
Display and control data transfer
Undefined
Undefined
Undefined
Undefined
System reset period
Defined
Defined
Defined
Defined
Undefined
Undefined
Undefined
Undefined
Figure 3
Page 25
No. 6266-25/37
LC75804E, LC75804W
(2) Reset when the logic block power supply voltage is in the allowable operating range (VDD= 4.5 to 6.0V)
The system is reset when the RES pin is set low, and the reset is cleared by setting RES pin high.
2. LC75804E/W internal block states during the reset period
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
Page 26
No. 6266-26/37
LC75804E, LC75804W
VDET
CCB
INTERFACE
Blocks that are reset
COM4/S74
COM3
COM2
COM1
COMMON
DRIVER
CLOCK
GENERATOR
VSS
VLCD2
VLCD1
VLCD
CE
VDD
DI
TEST
CL
DO
OSC
RES
KI5
KI4
KI3
KI2
KI1
KS6
KS5
KS4
KS3
S76/KS2
S75/KS1
KEY SCAN
KEY BUFFER
CONTROL
REGISTER
SHIFT REGISTER
SEGMENT DRIVER & LATCH
S1/P1
S2/P2
S8/P8
S9
S73
3. Output pin states during the reset period
X: don’t care
Notes:*5. These output pins are forcibly set to the segment output function and held low.
*6. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is
transferred, either the common output or the segment output function is selected.
*7. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*8. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
Output pin State during reset
S1/P1 to S8/P8 L *5
S9 to S73 L
COM1 to COM3 L
COM4/S74 L *6
KS1/S75, KS2/S76 L *5
KS3 to KS5 X *7
KS6 H
DO H *8
Page 27
Sample Application Circuit 1
1/3 duty, 1/2 bias (for use with normal panels)
No. 6266-27/37
LC75804E, LC75804W
+5.5V
+5V
*9
*11
VDD
S73
COM4/S74
S9
P8/S8
P2/S2
P1/S1
COM3
(
)
(
)
(P8)
COM1
OSC
COM2
DO
DI
CL
*10
RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
From the controller
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 228 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
(P1)
(P2)
C
S75
S76
Page 28
No. 6266-28/37
LC75804E, LC75804W
Sample Application Circuit 2
1/3 duty, 1/2 bias (for use with large panels)
V
+5V
*11
VDD
S73
COM4/S74
S9
P8/S8
P2/S2
P1/S1
COM3
COM1
OSC
COM2
DO
DI
CL
*10RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
From the controller
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 228 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
*9
+5.5
R
RC
(P1)
(P2)
(P8)
(S75)
(S76)
Page 29
No. 6266-29/37
LC75804E, LC75804W
Sample Application Circuit 3
1/3 duty, 1/3 bias (for use with normal panels)
+5.5V
+5V
*9
*11
VDD
S73
COM4/S74
S9
P8/S8
P2/S2
P1/S1
COM3
COM1
OSC
COM2
DO
DI
CL
*10RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
From the controller
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 228 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
(P1)
(P2)
(P8)
C C
(S75)
(S76)
Page 30
No. 6266-30/37
LC75804E, LC75804W
Sample Application Circuit 4
1/3 duty, 1/3 bias (for use with large panels)
+5.5V
+5V
*11
S73
COM4/S74
S9
P8/S8
P2/S2
P1/S1
COM3
COM1
COM2
VDD
OSC
DO
DI
CL
*10RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
From the controller
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 228 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
(P1)
(P2)
(P8)
*9
R
R
C C
R
(S75)
(S76)
Page 31
No. 6266-31/37
LC75804E, LC75804W
Sample Application Circuit 5
1/4 duty, 1/2 bias (for use with normal panels)
+5.5V
+5V
*9
*11
S73
S9
P1/S1
P2/S2
P8/S8
COM1
COM2
COM3
S74/COM4
VDD
OSC
DO
DI
CL
*10RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
From the controller
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 300 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
DD
rise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
(P1)
(P2)
(P8)
C
(S75)
(S76)
Page 32
No. 6266-32/37
LC75804E, LC75804W
Sample Application Circuit 6
1/4 duty, 1/2 bias (for use with large panels)
+5.5V
+5V
*9
*11
S73
S9
P1/S1
P2/S2
P8/S8
COM1
COM2
COM3
S74/COM4
VDD
OSC
DO
DI
CL
*10RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
From the controller
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 300 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
DD
rise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
R
RC
(P1)
(P2)
(P8)
(S75)
(S76)
Page 33
No. 6266-33/37
LC75804E, LC75804W
Sample Application Circuit 7
1/4 duty, 1/3 bias (for use with normal panels)
+5.5V
+5V
*9
*11
S73
S9
P1/S1
P2/S2
P8/S8
COM1
COM2
COM3
S74/COM4
VDD
OSC
DO
DI
CL
*10RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
From the controller
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 300 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
C C
(P1)
(P2)
(P8)
(S75)
(S76)
Page 34
No. 6266-34/37
LC75804E, LC75804W
Sample Application Circuit 8
1/4 duty, 1/3 bias (for use with large panels)
+5.5V
+5V
*9
*11
S73
S9
P1/S1
P2/S2
P8/S8
COM1
COM2
COM3
S74/COM4
VDD
OSC
DO
DI
CL
*10RES
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
7
6
/
K
S
2
S
7
5
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
Notes on transferring display data from the controller
When using the LC75804E/W in 1/3 duty, applications transfer the display data (D1 to D228) in three operations, and in
1/4 duty, they transfer the display data (D1 to D300) in four operations. In either case, applications should transfer all of
the display data within 30 ms to maintain the quality of the displayed image.
From the controller
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
(general-purpose output ports)
Used with the backlight
controller or other circuit.
LCD panel (up to 300 segments)
To the controller
To the controller
power supply
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
DD
rise time when power is applied and the logic
block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
R
R
CC
R
(P1)
(P2)
(P8)
(S75)
(S76)
Page 35
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
(2) Timing chart
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No. 6266-35/37
LC75804E, LC75804W
YES
NO
DO = [L]
CE = [L]
DO
DI
CE
Key onKey on
t6
t9t9t9t9
t5
t8 t8
t7 t7
t5
t7
t8
t5
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ———
fosc
Key data read
processing
Key input
Key scan
Key data read request
Key data read
Key address
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key off)
Page 36
No. 6266-36/37
LC75804E, LC75804W
2. Interrupt based key data acquisition
(1) Flowchart
(2) Timing chart
YES
YES
NO
DO = [L]
CE = [L]
CE = [L]
NO
DO = [H]
Key OFF
DO
DI
CE
Key onKey on
t10t10 t10t10
t5 t6
t8 t8
t7 t7
t5
t7
t8
t5
t7
t8
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ———
fosc
Key data read
processing
Wait for at
least t10
Key input
Key scan
Key data read request
Key data read
Key address
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Page 37
PS No. 6266-37/37
LC75804E, LC75804W
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10 has
elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must
satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
This catalog provides information as of May, 2003. Specifications and information herein are subject to
change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
Loading...