Datasheet LC75410W, LC75410E Datasheet (SANYO)

Page 1
Ordering number : ENN7027
O1901RM (OT) No. 7027-1/28
Overview
The LC75410E and 75410W are electronic volume controllers that enable control of volume, balance, fader, bass/treble/mid, loudness, input switching, and input gain using only a small number of external components.
• Volume: 0 dB to –79.5 dB in 0.5-dB steps, and –(161
positions) Balance function with separate L/R control
• Fader: rear output or front output can be attenuated across 16 positions (in 1-dB steps from 0 dB to –2 dB, 2-dB steps from –2 dB to –20 dB, 10-dB steps from –20 dB to –30 dB, and –45 dB, –60 dB, –)
• Bass/treble/mid: Each band can be controlled in 1-dB
steps from 0 dB to ±6 dB, and in 2-dB steps from ±8 dB to ±12 dB.
• Input gain: 0 dB to +18.75 dB (1.25-dB steps)
amplification is possible for the input signal.
• Input switching: five input signals can be selected for
Left and for Right (Four are single­ended inputs and one is a differential input.)
• Loudness: A tap is output from the –32 dB position of a
2 dB step volume control resistor ladder. A loudness function can be implemented by connecting an external RC circuit.
Features
• On-chip buffer amplifier cuts down number of external components
• Low switching noise generated by on-chip switch through use of silicon gate CMOS process, for low switching noise when there is no signal
• Low switching noise when there is a signal due to use of on-chip zero-cross switching circuit
• On-chip 1/2 VDD reference voltage circuit
• Controls performed with serial input (CCB)
LC75410E, 75410W
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Electronic Volume Controller
for Car Audio Systems
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.
Page 2
No. 7027-2/28
LC75410E, 75410W
Package Dimensions
unit: mm
3159-QIP64E
unit: mm
3190-SQFP64
14.0
17.2
1.0
1.0
1.6
0.15
0.35
0.1
15.6
0.8
0.8
3.0max
1
16
17
32
33
48
49
64
2.7
14.0
17.2
1.0
1.0
1.6
0.8
SANYO: QIP64E
[LC75410E]
10.0
12.0
1.25
0.5
1.25
1.25 0.5 1.250.18
12.0
1 16
17
32
33
48
49
64
10.0
0.5
1.7max
0.5
0.1
0.15
SANYO: SQFP64
[LC75410W]
Pin Assignment
LC75410E LC75410W
5 4 3 2 1 11 10 9 8 7 6
RSELO
RVRIN
RCT
RCOM
RVROUT
RTIN
RF1C1
RF1C2
RF1C3
RF2C1
RF2C2
21
20 19 18 17
27
26
25
24
23
22
RFIN
RFOUT
RROUT
TIM
NC
RAVSS
MUTE
CE
DI
CL
DVSS
12
28
RF2C313RF3C114RF3C215RF3C3
16
4445464748 383940414243 37 36 35 34 33
RTOUT
TEST
29
LAVSS
30
LROUT
31
LFOUT
32
60 61 62 63 64
54 55 56 57 58 59
53
52
51
50
49
LFIN
R5P
R5M
R4
R3
R2
R1
RVref
Vref
VDD
LVref
L1
L2
L3
L4
L5M
L5P
LSELO
LVRIN
LCT
LCOM
LVROUT
LTIN
LF1C1
LF1C2
LF1C3
LF2C1
LF2C2
LF2C3
LF3C1
LF3C2
LF3C3
LTOUT
Page 3
No. 7027-3/28
LC75410E, 75410W
Equivalent Circuit Block Diagram/Sample Application Circuit
0.033µF
L5P
+
LFIN
RFIN
NC
TIM
TEST
CE
DI
CL
LOGIC CIRCUIT
ZEROCROSS DET
ZEROCROSS DET
MUTE
TEST
DVSS
VDD
LVref
1µF × 6
1µF × 6
10µF
1µF
220pF
0.001µF0.001µF0.01µF0.1µF 0.1µF 0.01µF
LTOUT
LF3C2 LF3C1
LF3C3
LF2C2
LF2C3
LF2C1
LF1C2
LF1C3
LF1C1
LTIN
LVROUT
LVref
68k
4.7k
0.1µF
10µF
10µF
LCOM
LCT
LVRIN
LSELO
CONTROL
CIRCUIT
NO SIGNAL
TIMER
Multiplexer
Multiplexer
[BASS fo 100Hz] [MID fo 1kHz] [TREBLE fo 10kHz]
0.001µF
0.001µF
10µF
RTOUT
RF3C2
RF3C3
RF3C1
0.01µF
0.01µF
RF2C2
RF2C3
RF2C1
0.1µF
0.1µF
RF1C2
RF1C3
RF1C1
10µF
LVref
LVref
+
Vref
47µF
+
+
RVref
10µF
+
RVref LVref
RVref
RVref
1M
47k
RVROUT
RTIN
RCOM
RSELO
RVRIN
RCT
10µF
10µF
220pF
1µF
68k
4.7k
0.1µF
RVref
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
L5M
+
10µF
PA
LROUT
LFOUT
10µF
PA
10µF
PA
RFOUT
RROUT
10µF
PA
L4+L3+L2+L1
+
R1+R2+R3+R4
+
R5M
+
R5P
+
+
+
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CCB
INTERFACE
DI
CE
CL
µCOM
LAVSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
[BASS fo 100Hz] [MID fo 1kHz] [TREBLE fo 10kHz]
Page 4
No. 7027-4/28
LC75410E, 75410W
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max V
DD
11 V
Maximum input voltage V
IN
max All input pins VSS– 0.3 to VDD+ 0.3 V
Allowable power dissipation Pd max Ta 85°C, when mounted on board
QIP64E 680
mW
SQFP64 800 Operating temperature Topr –40 to +85 °C Storage temperature Tstg –50 to +125 °C
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage V
DDVDD
6.0 10.5 V
Input high-level voltage V
IH
CL, DI, CE, MUTE 4.0 10.5 V
Input low-level voltage V
IL
CL, DI, CE, MUTE V
SS
1.0 V
Input amplitude voltage V
IN
V
SS
V
DD
Vp-p Input pulse width TøW CL 1 µs Setup time Tsetup CL, DI, CE 1 µs Hold time Thold CL, DI, CE 1 µs Operating frequency fopg CL 500 kHz
Allowable Operating Ranges at Ta = 25°C, VSS= 0 V
Parameter Symbol Pin Name Conditions
Ratings
Unit
min typ max
[Input block]
Input resistance Rin L1 to L4, R1 to R4 25 50 100 k Minimum input gain Ginmin L1 to L4, R1 to R4 –1 0 +1 dB Maximum input gain Ginmax +16.5 +18.75 +21 dB Step setting error ATerr ±0.5 dB L/R balance BAL ±0.5 dB
[Volume Block]
Input resistance Rvr LVRIN, RVRIN, loudness off 113 226 452 k Step setting error ATerr ±0.5 dB L/R balance BAL ±0.5 dB
[Tone block]
Step setting error ATerr ±1.0 dB Bass control range Gbass max. boost/cut ±9 ±12 ±15 dB Mid control range Gmid max. boost/cut ±9 ±12 ±15 dB Treble control range Gtre max. boost/cut ±9 ±12 ±15 dB L/R balance BAL ±0.5 dB
Electrical Characteristics at Ta = 25°C, VDD= 9 V, VSS= 0 V
Continued on next page.
Page 5
No. 7027-5/28
LC75410E, 75410W
Parameter Symbol Pin Name Conditions
Ratings
Unit
min typ max
[Fader Block]
Input resistance Rfed LFIN, RFIN 25 50 100 k
0dB to –2dB ±0.5 dB
Step setting error ATerr
–2dB to –20dB ±1 dB –20dB to –30dB ±2 dB –30dB to –60dB ±3 dB
L/R balance BAL ±0.5 dB
[General]
Total harmonic distortion
THD (1) V
IN
= 0dBV, f = 1 kHz 0.004 0.01 %
THD (2) V
IN
= –10dBV, f = 10 kHz 0.006 0.01 %
Input crosstalk CT V
IN
= 1Vrms, f = 1 kHz 80 88 dB
L/R crosstalk CT V
IN
= 1Vrms, f = 1 kHz 80 88 dB
Maximum attenuated output
Vomin (1) V
IN
= 1Vrms, f = 1 kHz 80 88 dB
Vomin (2)
V
IN
= 1Vrms, f = 1 kHz
90 95 dB
INMUTE, fader –
Output noise voltage
V
N
(1) Flat overall, IHF-A filter 5 10 µV
V
N
(2) Flat overall, 20 to 20 kHzBPF 7 15 µV
Current drain I
DD
40 45 mA
Input high-level current I
IH
CL, DI, CE, VIN= 9 V 10 µA
Input low-level current I
IL
CL, DI, CE, VIN= 0 V –10 µA
Maximum input voltage V
CL
THD = 1%, RL= 10 k
2.3 2.8 Vrms
flat overall, f
IN
= 1 kHz
Common-mode rejection ratio CMRR V
IN
= 0 dB, f = 1 kHz 45 70 dB
Continued from preceding page.
Control Timing and Data Format
To control the LC75410E and LC75410W input specified serial data to the CE, CL, and DI pins. The data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits.
CE DI
D43 D42 D41 D40 D39 D38 D5 D4 D3 D2 D0 D1 A3 A2 A1 A0 B3 B2 B1 B0
CL
1µs
min
1µs min
1µs min T
DEST
1µs min
1µs min
1µs min
CE
DI
CL
Page 6
Address code (B0 to A3)
The LC75410E and 75410W use 8-bit address code and can be used in common with ICs that support SANYO’s CCB serial bus.
Address Code
(LSB) (81HEX)
Control code allocation
Input Switching Control
No. 7027-6/28
LC75410E, 75410W
B0 B1 B2 B3 A0 A1 A2 A3
1 0 0 0 0 0 0 1
D0 D1 D2 Setting Setting
0 0 0 L1 (R1) 1 0 0 L2 (R2) 0 1 0 L3 (R3) 1 1 0 L4 (R4) 0 0 1 L5 (R5)
0 1 1
For IC testing: Normally not used
1 1 1
D3 Bit for IC testing: Normally set to 0
Input Gain Control
D4 D5 D6 D7 Operation
0 0 0 0 0dB 1 0 0 0 +1.25dB 0 1 0 0 +2.50dB 1 1 0 0 +3.75dB 0 0 1 0 +5.00dB 1 0 1 0 +6.25dB 0 1 1 0 +7.50dB 1 1 1 0 +8.75dB 0 0 0 1 +10.0dB 1 0 0 1 +11.25dB 0 1 0 1 +12.5dB 1 1 0 1 +13.75dB 0 0 1 1 +15.0dB 1 0 1 1 +16.25dB 0 1 1 1 +17.5dB 1 1 1 1 +18.75dB
Page 7
No. 7027-7/28
LC75410E, 75410W
Volume Control (0 to –20.5dB)
D8 D9 D10 D11 D12 D13 D14 D15 Operation
0 0 0 0 0 0 0 0 0dB 0 0 0 0 0 0 0 1 –0.5dB 1 0 0 0 0 0 0 0 –1dB 1 0 0 0 0 0 0 1 –1.5dB 0 1 0 0 0 0 0 0 –2dB 0 1 0 0 0 0 0 1 –2.5dB 1 1 0 0 0 0 0 0 –3dB 1 1 0 0 0 0 0 1 –3.5dB 0 0 1 0 0 0 0 0 –4dB 0 0 1 0 0 0 0 1 –4.5dB 1 0 1 0 0 0 0 0 –5dB 1 0 1 0 0 0 0 1 –5.5dB 0 1 1 0 0 0 0 0 –6dB 0 1 1 0 0 0 0 1 –6.5dB 1 1 1 0 0 0 0 0 –7dB 1 1 1 0 0 0 0 1 –7.5dB 0 0 0 1 0 0 0 0 –8dB 0 0 0 1 0 0 0 1 –8.5dB 1 0 0 1 0 0 0 0 –9dB 1 0 0 1 0 0 0 1 –9.5dB 0 1 0 1 0 0 0 0 –10dB 0 1 0 1 0 0 0 1 –10.5dB 1 1 0 1 0 0 0 0 –11dB 1 1 0 1 0 0 0 1 –11.5dB 0 0 1 1 0 0 0 0 –12dB 0 0 1 1 0 0 0 1 –12.5dB 1 0 1 1 0 0 0 0 –13dB 1 0 1 1 0 0 0 1 –13.5dB 0 1 1 1 0 0 0 0 –14dB 0 1 1 1 0 0 0 1 –14.5dB 1 1 1 1 0 0 0 0 –15dB 1 1 1 1 0 0 0 1 –15.5dB 0 0 0 0 1 0 0 0 –16dB 0 0 0 0 1 0 0 1 –16.5dB 1 0 0 0 1 0 0 0 –17dB 1 0 0 0 1 0 0 1 –17.5dB 0 1 0 0 1 0 0 0 –18dB 0 1 0 0 1 0 0 1 –18.5dB 1 1 0 0 1 0 0 0 –19dB 1 1 0 0 1 0 0 1 –19.5dB 0 0 1 0 1 0 0 0 –20dB 0 0 1 0 1 0 0 1 –20.5dB
Page 8
No. 7027-8/28
LC75410E, 75410W
Volume Control (–21 to –40.5dB)
D8 D9 D10 D11 D12 D13 D14 D15 Operation
1 0 1 0 1 0 0 0 –21dB 1 0 1 0 1 0 0 1 –21.5dB 0 1 1 0 1 0 0 0 –22dB 0 1 1 0 1 0 0 1 –22.5dB 1 1 1 0 1 0 0 0 –23dB 1 1 1 0 1 0 0 1 –23.5dB 0 0 0 1 1 0 0 0 –24dB 0 0 0 1 1 0 0 1 –24.5dB 1 0 0 1 1 0 0 0 –25dB 1 0 0 1 1 0 0 1 –25.5dB 0 1 0 1 1 0 0 0 –26dB 0 1 0 1 1 0 0 1 –26.5dB 1 1 0 1 1 0 0 0 –27dB 1 1 0 1 1 0 0 1 –27.5dB 0 0 1 1 1 0 0 0 –28dB 0 0 1 1 1 0 0 1 –28.5dB 1 0 1 1 1 0 0 0 –29dB 1 0 1 1 1 0 0 1 –29.5dB 0 1 1 1 1 0 0 0 –30dB 0 1 1 1 1 0 0 1 –30.5dB 1 1 1 1 1 0 0 0 –31dB 1 1 1 1 1 0 0 1 –31.5dB 0 0 0 0 0 1 0 0 –32dB 0 0 0 0 0 1 0 1 –32.5dB 1 0 0 0 0 1 0 0 –33dB 1 0 0 0 0 1 0 1 –33.5dB 0 1 0 0 0 1 0 0 –34dB 0 1 0 0 0 1 0 1 –34.5dB 1 1 0 0 0 1 0 0 –35dB 1 1 0 0 0 1 0 1 –35.5dB 0 0 1 0 0 1 0 0 –36dB 0 0 1 0 0 1 0 1 –36.5dB 1 0 1 0 0 1 0 0 –37dB 1 0 1 0 0 1 0 1 –37.5dB 0 1 1 0 0 1 0 0 –38dB 0 1 1 0 0 1 0 1 –38.5dB 1 1 1 0 0 1 0 0 –39dB 1 1 1 0 0 1 0 1 –39.5dB 0 0 0 1 0 1 0 0 –40dB 0 0 0 1 0 1 0 1 –40.5dB
Page 9
No. 7027-9/28
LC75410E, 75410W
Volume Control (–41 to –59.5dB)
D8 D9 D10 D11 D12 D13 D14 D15 Operation
1 0 0 1 0 1 0 0 –41dB 1 0 0 1 0 1 0 1 –41.5dB 0 1 0 1 0 1 0 0 –42dB 0 1 0 1 0 1 0 1 –42.5dB 1 1 0 1 0 1 0 0 –43dB 1 1 0 1 0 1 0 1 –43.5dB 0 0 1 1 0 1 0 0 –44dB 0 0 1 1 0 1 0 1 –44.5dB 1 0 1 1 0 1 0 0 –45dB 1 0 1 1 0 1 0 1 –45.5dB 0 1 1 1 0 1 0 0 –46dB 0 1 1 1 0 1 0 1 –46.5dB 1 1 1 1 0 1 0 0 –47dB 1 1 1 1 0 1 0 1 –47.5dB 0 0 0 0 1 1 0 0 –48dB 0 0 0 0 1 1 0 1 –48.5dB 1 0 0 0 1 1 0 0 –49dB 1 0 0 0 1 1 0 1 –49.5dB 0 1 0 0 1 1 0 0 –50dB 0 1 0 0 1 1 0 1 –50.5dB 1 1 0 0 1 1 0 0 –51dB 1 1 0 0 1 1 0 1 –51.5dB 0 0 1 0 1 1 0 0 –52dB 0 0 1 0 1 1 0 1 –52.5dB 1 0 1 0 1 1 0 0 –53dB 1 0 1 0 1 1 0 1 –53.5dB 0 1 1 0 1 1 0 0 –54dB 0 1 1 0 1 1 0 1 –54.5dB 1 1 1 0 1 1 0 0 –55dB 1 1 1 0 1 1 0 1 –55.5dB 0 0 0 1 1 1 0 0 –56dB 0 0 0 1 1 1 0 1 –56.5dB 1 0 0 1 1 1 0 0 –57dB 1 0 0 1 1 1 0 1 –57.5dB 0 1 0 1 1 1 0 0 –58dB 0 1 0 1 1 1 0 1 –58.5dB 1 1 0 1 1 1 0 0 –59dB 1 1 0 1 1 1 0 1 –59.5dB
Page 10
No. 7027-10/28
LC75410E, 75410W
Volume Control (–60 to –)
D8 D9 D10 D11 D12 D13 D14 D15 Operation
0 0 1 1 1 1 0 0 –60dB 0 0 1 1 1 1 0 1 –60.5dB 1 0 1 1 1 1 0 0 –61dB 1 0 1 1 1 1 0 1 –61.5dB 0 1 1 1 1 1 0 0 –62dB 0 1 1 1 1 1 0 1 –62.5dB 1 1 1 1 1 1 0 0 –63dB 1 1 1 1 1 1 0 1 –63.5dB 0 0 0 0 0 0 1 0 –64dB 0 0 0 0 0 0 1 1 –64.5dB 1 0 0 0 0 0 1 0 –65dB 1 0 0 0 0 0 1 1 –65.5dB 0 1 0 0 0 0 1 0 –66dB 0 1 0 0 0 0 1 1 –66.5dB 1 1 0 0 0 0 1 0 –67dB 1 1 0 0 0 0 1 1 –67.5dB 0 0 1 0 0 0 1 0 –68dB 0 0 1 0 0 0 1 1 –68.5dB 1 0 1 0 0 0 1 0 –69dB 1 0 1 0 0 0 1 1 –69.5dB 0 1 1 0 0 0 1 0 –70dB 0 1 1 0 0 0 1 1 –70.5dB 1 1 1 0 0 0 1 0 –71dB 1 1 1 0 0 0 1 1 –71.5dB 0 0 0 1 0 0 1 0 –72dB 0 0 0 1 0 0 1 1 –72.5dB 1 0 0 1 0 0 1 0 –73dB 1 0 0 1 0 0 1 1 –73.5dB 0 1 0 1 0 0 1 0 –74dB 0 1 0 1 0 0 1 1 –74.5dB 1 1 0 1 0 0 1 0 –75dB 1 1 0 1 0 0 1 1 –75.5dB 0 0 1 1 0 0 1 0 –76dB 0 0 1 1 0 0 1 1 –76.5dB 1 0 1 1 0 0 1 0 –77dB 1 0 1 1 0 0 1 1 –77.5dB 0 1 1 1 0 0 1 0 –78dB 0 1 1 1 0 0 1 1 –78.5dB 1 1 1 1 0 0 1 0 –79dB 1 1 1 1 0 0 1 1 –79.5dB 0 1 1 1 1 1 1 0
Page 11
No. 7027-11/28
LC75410E, 75410W
Three-Band Equalizer Control
D16 D17 D18 D19 D40 f1 band D20 D21 D22 D23 D41 f2 band D24 D25 D26 D27 D42 f3 band
0 1 1 0 0 +12dB 1 0 1 0 0 +10dB 0 0 1 0 0 +8dB 1 1 0 0 0 +6dB 1 1 0 0 1 +5dB 0 1 0 0 0 +4dB 0 1 0 0 1 +3dB 1 0 0 0 0 +2dB 1 0 0 0 1 +1dB 0 0 0 0 0 0dB 1 0 0 1 1 –1dB 1 0 0 1 0 –2dB 0 1 0 1 1 –3dB 0 1 0 1 0 –4dB 1 1 0 1 1 –5dB 1 1 0 1 0 –6dB 0 0 1 1 0 –8dB 1 0 1 1 0 –10dB 0 1 1 1 0 –12dB
Fader Volume Control
D28 D29 D30 D31 Operation
0 0 0 0 0dB 1 0 0 0 –1dB 0 1 0 0 –2dB 1 1 0 0 –4dB 0 0 1 0 –6dB 1 0 1 0 –8dB 0 1 1 0 –10dB 1 1 1 0 –12dB 0 0 0 1 –14dB 1 0 0 1 –16dB 0 1 0 1 –18dB 1 1 0 1 –20dB 0 0 1 1 –30dB 1 0 1 1 –45dB 0 1 1 1 –60dB 1 1 1 1
Channel Selection Control
D32 D33 Operation
0 0 L/R simultaneously, Initial setting mode 1 0 RCH 0 1 LCH 1 1 L/R simultaneously
Page 12
No. 7027-12/28
LC75410E, 75410W
Fader Rear/Front Control
D34 Setting
0 Rear 1 Front
Loudness Control
D35 Setting
0 OFF 1 ON
Test Mode Control
D43 Setting
0 For IC testing. Always set to 0.
Zero-Cross Control
D36 D37 Setting
0 0 Data write through zero-cross detection 1 1 Zero-cross detection stopped (data write at falling edge of CE)
Zero-Cross Signal Detection Block Control
D38 D39 Setting
0 0 Selector 1 0 Volume 0 1 Tone 1 1 Fader
Page 13
No. 7027-13/28
LC75410E, 75410W
Pin Functions
Pin Name Pin No. Function Equivalent circuit
• Single-end input pins
L1 L2 L3 L4 R1 R2 R3 R4
54 53 52 51 59 60 61 62
VDD
LVref RVref
• Input selector output pins
LSEL0 RSEL0
48
1
VDD
• 2-dB step volume input pins
• Perform input at low-impedance.
LVRIN
RVRIN
47
2
VDD
LVref RVref
• Loudness pins. Connect high-pass compensation RC between LCT (RCT) and LVRIN (RVRIN), and connect low-pass compensation RC between LCT (RCT) and GND.
LCT
RCT
46
3
VDD
• 2-dB stop volume output pins.
• To reduce switching noise, each of these pins should be connected to Vref through a capacitor.
LCOM
RCOM
45
4
VDD
• 0.5-dB step volume output pin
LVROUT
RVROUT
44
5
VDD
Continued on next page.
LVref RVref
VDD
VDD
M
P
• Differential input pins
50 49 63 64
L5M
L5P R5M R5P
Page 14
No. 7027-14/28
LC75410E, 75410W
Continued from preceding page.
Pin Name Pin No. Function Equivalent circuit
• Equalizer input pin
LTIN RTIN
43
6
VDD
LVref RVref
Continued on next page.
• Equalizer F1 band circuit filter configuration capacitor connection pins.
Connect capacitor between LF1C1 (RF1C1) and LF1C2 (RF1C2) LF1C2 (RF1C2) and LF1C3 (RF1C3)
LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3
42 41 40
7 8 9
Vref
VDD
VDD
FnC1
TIN
VDD
VDD
FnC3
VDD
FnC2
• Equalizer F2 band circuit filter configuration capacitor connection pins.
Connect capacitor between LF2C1 (RF2C1) and LF2C2 (RF2C2) LF2C2 (RF2C2) and LF2C3 (RF2C3)
LF2C1 LF2C2 LF2C3 RF2C1 RF2C2 RF2C3
39 38 37 10 11 12
• Equalizer F3 band circuit filter configuration capacitor connection pins.
Connect capacitor between LF3C1 (RF3C1) and LF3C2 (RF3C2) LF3C2 (RF3C2) and LF3C3 (RF3C3)
LF3C1 LF3C2 LF3C3 RF3C1 RF3C2 RF3C3
36 35 34 13 14 15
• Equalizer output pins
LTOUT
RTOUT
33 16
VDD
• Fader block input pins
• Drive at low impedance.
LFIN RFIN
32 17
VDD
• Fader output pins. Attenuation is possible separately for the front end and rear end. The attenuation amount is the same for L and R.
LFOUT LROUT RFOUT
RROUT
31 30 18 19
VDD
• Connect a capacitor of a few tens of µF between Vref and AVSS (VSS) as a 0.55 VDD voltage generator, current ripple countermeasure.
Vref 57
VDD
LVref RVref
• Internal analog system ground pins.
LVref
RVref
55 58
Page 15
No. 7027-15/28
LC75410E, 75410W
Pin Name Pin No. Function Equivalent circuit
• Power supply pinVDD 56
• Logic system ground pinDVSS 27
• External muting control pin
• Setting this pin to V
SS
level sets forcibly fader volume block to
level.
MUTE 23
VDD
• Timer pin when there is no signal in the zero-cross circuit.
Forcibly set data when there is no zero-cross signal, from the time the data is set until the timer ends.
TIM 20
VDD
• Input pin for serial data and clock used for control
CL
DI
26 25
VDD
• Chip enable pin. Data is written to the internal latch and the analog switches are operated when the level changes from High to Low.
Data transfer is enabled when the level is High.
CE 24
• No Connect pin.NC 21
Continued from preceding page.
• Analog system ground pins
LAVSS
RAVSS
29 22
• Dedicated IC test pin.
• Normally this pin is used connected to GND.
TEST 28
VDD
Page 16
Internal Equivalent Circuit Block Diagram
Selector Block Equivalent Circuit Block Diagram
No. 7027-16/28
LC75410E, 75410W
1.25dB
2.50dB
3.75dB
5.00dB
6.25dB
7.50dB
8.75dB
LSELO
0dB
+
-
50k
50k
50k
+
-
LVref
6.702k
5.804k
5.026k
4.352k
3.769k
3.264k
2.826k
2.447k
2.119k
1.835k
1.589k
1.376k
1.192k
1.032k
0.894k
5.774k
LVref
10.0dB
11.25dB
12.5dB
13.75dB
15.0dB
16.25dB
17.5dB
18.75dB
L3
LVref
LVref
LVref
INMUTE SW
L2
L1
50k
LVref
L4
R4=25k
R1=22.65k
R2=25k
R3=22.65k
LVref
L5P
L5M
Total resistance: 50 k Same for right channel Unit (Resistance: )
Page 17
2-dB Volume Block Equivalent Circuit Block Diagram
No. 7027-17/28
LC75410E, 75410W
Total resistance of 195 k over tap
Total resistance of
30.847 k under tap
Same for right channel Unit (Resistance: )
To left channel
0.5–dB block
LVref
41.139k
32.678k
25.957k
20.618k
16.378k
–2dB –4dB –6dB
–8dB –10dB –12dB –14dB
0dB
–16dB –18dB –20dB –22dB –24dB –26dB –28dB –30dB –32dB –34dB –36dB –38dB –40dB –42dB –44dB –46dB –48dB –50dB –52dB –54dB –56dB –58dB –60dB –62dB –64dB –66dB –68dB –70dB –72dB –74dB –76dB –78dB –dB
13.009k
10.334k
8.208k
6.520k
5.179k
4.114k
3.268k
2.596k
2.062k
1.638k
1.301k
6.344k
5.040k
LCT
5.750k
4.003k
3.180k
2.526k
2.006k
1.594k
1.266k
1.006k
0.799k
0.634k
0.504k
0.400k
0.318k
0.253k
0.201k
0.159k
0.127k
0.101k
0.080k
0.063k
0.050k
0.040k
0.154k
LVRIN
Page 18
0.5-dB Volume Block Equivalent Circuit Block Diagram
No. 7027-18/28
LC75410E, 75410W
Initial setting switch
From left channel 2-dB block
Initial setting switch
2.797k
Unit: Total resistance: 50 k
Same for right channel
2.640k
LVROUT
Vref
–1dB
dB
LCOM
0dB
–0.5dB
–1.5dB
2.493k
42.070k
Page 19
3-Band Graphic Equalizer Block Equivalent Circuit Diagram
No. 7027-19/28
LC75410E, 75410W
LTOUT
Unit: Total resistance: 38.861 k Same for right channel
SW3
SW4
12dB
10dB
8dB
6dB
5dB
LF2C1
4dB 3dB
2dB
1dB
0dB
SW1
SW2 SW3
SW4
12dB
10dB
8dB
6dB
5dB
LF3C1
4dB 3dB
2dB
1dB
0dB
SW1
SW2 SW3
SW4
50k
LTIN
12dB
10dB
8dB
6dB
5dB
LF1C1
LVref
4dB 3dB
2dB
1dB
0dB
SW1
SW2
3.373k
4.246k
5.346k
3.172k
3.558k
3.993k
4.480k
5.027k
5.640k
0.027k
3.373k
4.246k
5.346k
3.172k
3.558k
3.993k
4.480k
5.027k
5.640k
0.027k
3.373k
4.246k
5.346k
3.172k
3.558k
3.993k
4.480k
5.027k
5.640k
0.027k
LF1C2 LF1C3 LF2C3 LF3C3
6.50k
LF2C2
6.50k
LF3C2
6.50k
During boost, SW 1 and SW 3 are ON, during cut SW 2 and SW 4 are ON, and when 0 dB, 0 dB SW and SW 2 and SW 3 are ON.
Page 20
1 + G
+12 dB
= 20 × LOG
10
R3 = – R1
2R3+R1
R2
10
G/20
–1
R2
÷ 2 ≅ 6.5 k
F1/F2/F3 Band Circuit The equivalent circuit and the formula for calculating the external RC with a mean frequency of 1 kHz are shown below.
• F1/F2/F3 band equivalent circuit block diagram
1. Calculate R2 with G
+12 dB
= 12 dB:
2. Calculate C with the center frequency f0 = 1 kHz
No. 7027-20/28
LC75410E, 75410W
• Calculation example Specification Mean frequency: f0 = 1 kHz Gain during maximum boost: G
+12 dB
= 12 dB
Let us use R1 = 0.027 k, R2 = 38.861 kand C1 = C2 = C.
R1 R2
R3
C2C1
2
1
0
(R1+R2)R3C1C2
f
π
=
0.01 µF
38888×650010002
1
(R1+R2)R3f02
1
ππ
×
= = 0.010 × 10–6 =C
3. Calculate Q:
1.22
(R1+R2)R3
R3(R1+R2)
(2R3+R1)
1
Q ×=
Page 21
Fader Volume Block Equivalent Circuit Block Diagram
No. 7027-21/28
LC75410E, 75410W
LFIN
5.437k
When FADER = "1", S2 and S3 are ON. When FADER = "0", S1 and S4 are ON.
Unit: Total resistance: 50 k Same for right channel
4.846k
8.169k
4.094k
LFOUT
LVref
–1dB
–2dB
0dB
S1
S2
S3
S4
6.489k
5.154k
–6dB
–8dB
–4dB
3.252k
2.583k
2.052k
3.419k
–12dB
–14dB
–10dB
1.630k
1.295k
–18dB
–20dB
–16dB
1.300k
0.231k
–45dB
–60dB
dB
–30dB
0.050k
LROUT
When – data is sent to the main volume, S1 and S2 become open, and S3 and S4 simultaneously become ON.
Page 22
Usage Cautions
(1) Data transmission at power ON
• The status of internal analog switches is unstable at power ON. Therefore, perform muting or some other countermeasure until the data has been set.
• At power ON, initial setting data must be sent once in order to stabilize the bias of each block in a short time.
(2) Description of zero-cross switching circuit operation
The LC75410E and 75410W have a function to switch zero-cross comparator signal detection locations, enabling the selection of the optimum detection location for blocks whose data is to be updated. Basically, the switching noise can be minimized by inputting the signal immediately following the block whose data is to be updated to the zero-cross comparator, so it is necessary to switch the detection location every time.
LC75410E, 75410W Zero-Cross Detection Circuit
No. 7027-22/28
LC75410E, 75410W
Volume Tone
Switch
Fader
Zero-cross
comparator
Selector
(3) Zero-cross switching control method
The zero-cross switching control method consists of setting the zero-cross control bits to the zero-cross detection mode (D36, D37 = 0), and specifying the detection blocks (D38, D39) before transmitting the data. These control bits are latched immediately following data transfer, that is to say beforehand in sync with the falling edge of CE, so when updating data of volumes, etc., it is possible to perform mode setting and zero-cross switching with one data transfer. An example of control when updating the data of the volume block is shown below.
Zero-cross detection
mode setting
Volume block
setting
D36 D37 D38 D39
0 0 1 0
(4) Zero-cross timer setting
If the input signal becomes lower than the zero-cross comparator detection sensitivity, or if only low-frequency signals are input, zero-cross detection continues to be impossible, and data is not latched during this time. The zero-cross timer can set a time for forcible latch during such a status when zero-cross detection is not possible.
For example, to set 25 ms, using T = 0.69CR and C = 0.033 µF, we obtain
Normally, a value between 10 ms and 50 ms is set.
R=
1.1 M
25 ×10
–3
0.69 × 0.033 × 10
–6
Page 23
No. 7027-23/28
LC75410E, 75410W
(5) Cautions related to serial data transfer
1. To ensure that the high-frequency digital signals transferred to the CL, DI, and CE pins do not spill over to the analog signal block, either guard these signal lines with a ground pattern, or perform transmission using shielded wires.
2. The data format of the LC75410E and 75410W uses 8-bit addresses and 44-bit data. When sending data using multiples of 8 (when sending 48 bits), use the method described in Figure 1.
Method for Receiving Data Using Multiple of 8 of LC75410E and 75410W
Figure 1
D43D42D41D40D39D38D37D36D3D2D1D0XXXX
Test mode control
Input switching controlDummy data
X : don’t care
Page 24
No. 7027-24/28
LC75410E, 75410W
ILC05430
--100
--90
--80
--70
--60
--50
--40
--30
--20
--10
0
--
--70 --60 --50 --40 --30 --20 --10 0
ILC05428
0
2
4
6
8
10
12
14
16
18
20
0 2 4 1086 12 14 16 18 20
V
V
ILC05429
0
2
4
6
8
10
12
14
16
18
20
0 2 4 1086 12 14 16 18 20
V
ILC05431
--100
--90
--80
--70
--60
--50
--40
--30
--20
--10
0
--
--70 --60 --50 --40 --30 --20 --10 0
V
Input Gain Step Characteristics
Output level — dB
Step setting — dB Step setting — dB
LC75410E V
DD
=9V
V
IN
=–30dBV Input L1 Output LFOUT f=1kHz
Input gain block
Main volume block
Graphic equalizer block
Fader block
Input Gain Step Characteristics
Output level — dB
LC75410W V
DD
=9V
V
IN
=–30dBV Input L1 Output LFOUT f=1kHz
Input gain block
Main volume block
Graphic equalizer block
Fader block
Step setting — dB
Main Volume Control Step Characteristics
Attenuation — dB
LC75410W V
DD
=9V
V
IN
=0dBV Input L1 Output LFOUT f=1kHz
Input gain block
Main volume block
Graphic equalizer block
Fader block
Step setting — dB
Main Volume Control Step Characteristics
Attenuation — dB
LC75410E V
DD
=9V
V
IN
=0dBV Input L1 Output LFOUT f=1kHz
Input gain block
Main volume block
Graphic equalizer block
Fader block
Page 25
No. 7027-25/28
LC75410E, 75410W
ILC05433
--100
--90
--80
--70
--60
--50
--40
--30
--20
--10
0
--
--70 --60 --50 --40 --30 --20 --10 0
ILC05434
0.001
0.01
0.1
1.0
10
2 3
100
75 2 31k75 2 3
10k
75 2 3
100k
75
VIN= --10dBV
VIN=0dBV
VIN= --10dBV
VIN=0dBV
V
THD
METER
2
3
5
7
2
3
5
7
2
3
5
7
ILC05435
0.001
0.01
0.1
1.0
10
2 3
100
75 2 31k75 2 3
10k
75 2 3
100k
75
THD
METER
2
3
5
7
2
3
5
7
2
3
5
7
ILC05432
--100
--90
--80
--70
--60
--50
--40
--30
--20
--10
0
--
--70 --60 --50 --40 --30 --20 --10 0
V
Step setting — dB
Fader Volume Control Step Characteristics
Attenuation — dB
LC75410E V
DD
=9V, VSS=0
V
IN
=0dBV Input L1 Output LFOUT f=1kHz
Input gain block
Main volume block
Graphic equalizer block
Fader block
Step setting — dB
Fader Volume Control Step Characteristics
Attenuation — dB
LC75410W V
DD
=9V, VSS=0
V
IN
=0dBV Input L1 Output LFOUT f=1kHz
Input gain block
Main volume block
Graphic equalizer block
Fader block
Frequency, f — Hz
THD — Frequency Characteristics
Total harmonic distortion, THD — %
LC75410W V
DD
=9V Input L1 Output LFOUT 80kHz LPF
Input gain block
Main volume block
Graphic equalizer block
Fader block
Frequency, f — Hz
THD — Frequency Characteristics
Total harmonic distortion, THD — %
LC75410E V
DD
=9V Input L1 Output LFOUT 80kHz LPF
Input gain block
Main volume block
Graphic equalizer block
Fader block
Page 26
No. 7027-26/28
LC75410E, 75410W
ILC05437
0.001
0.01
0.1
1.0 7
5 3
2
7 5
3 2
7 5
3 2
--40 --35 --30 --25 --20 --15 --10 --5 0 5 10
THD
METER
ILC05438
0.001
0.01
0.1
1.0 7
5 3
2
7 5
3 2
7 5
3 2
4 5 6 7 8 9 10 11 12 13
THD
METER
ILC05439
THD
METER
ILC05436
0.001
0.01
0.1
1.0 7
5 3
2
7 5
3 2
7 5
3 2
--40 --35 --30 --25 --20 --15 --10 --5 0 5 10
THD
METER
f=10kHz
f=20kHz
f=1kHz
f=10kHz
f=20kHz
f=1kHz
f=10kHz
f=20kHz
f=1kHz
0.001
0.01
0.1
1.0 7
5 3
2
7 5
3 2
7 5
3 2
4 5 6 7 8 9 10 11 12 13
f=10kHz
f=20kHz
f=1kHz
THD — Input Level Characteristics
Total harmonic distortion, THD — %
Input level, VIN — dB
LC75410E VDD=9V, VSS=0 80kHz LPF Input L1, Output LFOUT With VR=0dB
Input gain block
Main volume block
Graphic equalizer block
Fader block
THD — Input Level Characteristics
Total harmonic distortion, THD — %
Input level, VIN — dB
LC75410W VDD=9V, VSS=0 80kHz LPF Input L1, Output LFOUT With VR=0dB
Input gain block
Main volume block
Graphic equalizer block
Fader block
THD — Supply Voltage Characteristics
Total harmonic distortion, THD — %
Supply voltage — V
LC75410W V
SS
=0, VIN=0dBV Input L1 Output LFOUT 80kHz LPF
Input gain block
Main volume block
Graphic equalizer block
Fader block
THD — Supply Voltage Characteristics
Total harmonic distortion, THD — %
Supply voltage — V
LC75410E V
SS
=0, VIN=0dBV Input L1 Output LFOUT 80kHz LPF
Input gain block
Main volume block
Graphic equalizer block
Fader block
Page 27
No. 7027-27/28
LC75410E, 75410W
ILC05440
--40
--35
--30
--25
--20
--15
--10
--5
0
100k
2 3 5 7
10k
2 3 5 7
1k
2 3 5 7
10010
2 3 5 7
ILC05441
--40
--35
--30
--25
--20
--15
--10
--5
0
100k
2 3 5 7
10k
2 3 5 7
1k
2 3 5 7
10010
2 3 5 7
ILC05442
--40
--35
--30
--25
--20
--15
--10
--5
0
100k
2 3 5 7
10k
2 3 5 7
1k
2 3 5 7
10010
2 3 5 7
ILC05443
ILC05444
--40
--35
--30
--25
--20
--15
--10
--5
0
100k
2 3 5 7
10k
2 3 5 7
1k
2 3 5 7
10010
2 3 5 7
--40
--35
--30
--25
--20
--15
--10
--5
0
100k
2 3 5 7
10k
2 3 5 7
1k
2 3 5 7
10010
2 3 5 7
ILC05445
--40
--35
--30
--25
--20
--15
--10
--5
0
100k
2 3 5 7
10k
2 3 5 7
1k
2 3 5 7
10010
2 3 5 7
ILC05446
--60
10
--10
--30
--20
--40
--50
0
--10
--30
--20
--40
--50
--12
--32
--22
--42
--52
--14
--34
--24
--44
--54
--16
--36
--26
--46
--18
--2
--4
--6
--8
--38
--28
--48
0
10 100 10k1k
LC75410E
2 3 5 7 2 3 5 7 2 3 5 7 2 3 5
100k
7
ILC05447
--60
10
--10
--30
--20
--40
--50
0
--10
--30
--20
--40
--50
--12
--32
--22
--42
--52
--14
--34
--24
--44
--54
--16
--36
--26
--46
--18
--2
--4
--6
--8
--38
--28
--48
0
10 100 10k1k
LC75410W
2 3 5 7 2 3 5 7 2 3 5 7 2 3 5
100k
7
F1 Band Characteristics
Level — dB
Frequency, f — Hz
LC75410E
V
DD
=9V
V
IN
=–20dBV Input L1 Output LFOUT
F1 Band Characteristics
Level — dB
Frequency, f — Hz
LC75410W V
DD
=9V
V
IN
=–20dBV Input L1 Output LFOUT
F2 Band Characteristics
F2 Band Characteristics
Level — dB
Level — dB
Frequency, f — Hz
Frequency, f — Hz
LC75410E V
DD
=9V
V
IN
=–20dBV Input L1 Output LFOUT
LC75410W V
DD
=9V
V
IN
=–20dBV Input L1 Output LFOUT
F3 Band Characteristics
Level — dB
F3 Band Characteristics
Level — dB
Frequency, f — Hz Frequency, f — Hz
LC75410E V
DD
=9V
V
IN
=–20dBV Input L1 Output LFOUT
LC75410W V
DD
=9V
V
IN
=–20dBV Input L1 Output LFOUT
Output Level Characteristics
Output Level Characteristics
Level — dB
Level — dB
Frequency, f — Hz
Frequency, f — Hz
VDD = 9 V, VIN = 0, Input: L1, Output: LFOUT For settings from 0 to –54 dB (in 2 dB steps)
VDD = 9 V, VIN = 0, Input: L1, Output: LFOUT For settings from 0 to –54 dB (in 2 dB steps)
Page 28
PS No. 7027-28/28
LC75410E, 75410W
This catalog provides information as of October, 2001. Specifications and information herein are subject to change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
10
0
--10
--20
--30
Level — dB
--40
--50
--60
Loudness Characteristics
VDD = 9 V, VIN = 0, Input: L1, Output: LFOUT Loudness on, for settings from 0 to -54 dB (in 2 dB steps)
2 3 5 7 2 3 5 7 2 3 5 7 2 3 5 7
Frequency, f — Hz
10
0
--2
--4
--6
--8
--10
--12
--14
--16
--18
--20
--22
--24
--26
--28
--30
--32
--34
--36
--38
--40
--42
--44
--46
--48
--50
--52
LC75410E
--54
100k10 100 10k1k
ILC05448 ILC05449
0
--10
--20
--30
Level — dB
--40
--50
--60 10 100 10k1k
Loudness Characteristics
VDD = 9 V, VIN = 0, Input: L1, Output: LFOUT Loudness on, for settings from 0 to -54 dB (in 2 dB steps)
LC75410W
2 3 5 7 2 3 5 7 2 3 5 7 2 3 5
Frequency, f — Hz
7
100k
0
--2
--4
--6
--8
--10
--12
--14
--16
--18
--20
--22
--24
--26
--28
--30
--32
--34
--36
--38
--40
--42
--44
--46
--48
--50
--52
--54
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