Page 1
Overview
The LC75394NE is an electronic volume control system
providing control over volume, balance, 5-band equalizer,
and input switching based on serial inputs.
Functions
• Volume control:
The chip provides 25 levels of volume attenuation: in 2dB steps between 0 dB and –20 dB, 3-dB steps between
–20 dB and –32 dB, 4-dB steps between –32 dB and –52
dB, 4.5-dB steps between –52 dB and –70 dB, and – ∞.
Independent control over left and right channels
provides balance control.
• Equalizer:
The chip provides control in 2-dB steps over the range
between +10 dB and –10 dB. Four of the five bands
have peaking equalization; the remaining one, shelving
equalization.
• Selector:
The left and right channels each offer a choice of four
inputs. An external constant determines the
amplification for the input signal.
Features
• Built-in buffer amplifiers reduce the number of external
parts necessary.
• Silicon gate CMOS reduces switching noise.
• Serial data input
—Supports CCB* format communication with the
system controller.
• A built-in reference voltage circuit divides the supply
voltage (VDD) in half.
Package Dimensions
unit: mm
3159-QFP64E
CMOS LSI
Ordering number : EN5466
91096HA (OT)/81095HA (OT) No. 5466-1/17
SANYO: QFP64E
[LC75394NE]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
Single-Chip Electronic Volume Control System
LC75394NE
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max V
DD
12 V
Maximum input voltage V
IN
max
CL, DI, CE, L1 to L4, R1 to R4, LTIN, RTIN, LVRIN, V
SS
– 0.3 to
V
RVRIN V
DD
+ 0.3
Allowable power dissipation Pd max Ta ≤ 85°C 310 mW
Operating temperature Topr –30 to +85 °C
Storage temperature Tstg –40 to +125 °C
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
*
Page 2
Allowable Operating Ranges at Ta = 25°C, VSS= 0 V
Electrical Characteristics at Ta = 25°C, VDD= 10 V, VSS= 0 V
Input Amplifier Characteristics at Ta = 25°C, VDD– VSS= 10 V
No. 5466-2/17
LC75394NE
Parameter Symbol Conditions min typ max Unit
Supply voltage V
DD
V
DD
6.0 11.0 V
Input high level voltage V
IH
CL, DI, CE 4.0 V
DD
V
Input low level voltage V
IL
CL, DI, CE V
SS
1.0 V
Input voltage amplitude V
IN
CL, DI, CE, L1 to L4, R1 to R4, LTIN, RTIN, LVRIN,
V
SS
V
DD
Vp-p
RVRIN
Input pulse width t
øW
CL 1.0 µs
Setup time t
SETUP
CL, DI, CE 1.0 µs
Hold time t
HOLD
CL, DI, CE 1.0 µs
Operating frequency fopg CL 500 kHz
Parameter Symbol Conditions min typ max Unit
[Input block]
Input resistance Rin L1 to L4, R1 to R4 1 MΩ
Clipping level Vcl LSELO, RSELO: THD = 1.0% 2.65 Vrms
Output load resistance R
L
LSELO, RSELO 3 kΩ
[Volume control block]
Input resistance Rin LVRIN, RVRIN 60 100 140 kΩ
[Equalizer control block]
Control range Geq Max, boost/cut ±8 ±10 ±12 dB
Step resolution Estep 1 2 3 dB
Internal feedback resistance Rfeed 17 28 39 kΩ
[Overall characteristics]
Total harmonic distortion
THD (1) V
IN
= 1 Vrms, f = 1 kHz, with all controls flat overall 0.0033 %
THD (2) V
IN
= 1 Vrms, f = 20 kHz, with all controls flat overall 0.012 %
Crosstalk CT
V
IN
= 1 Vrms, f = 1 kHz, with all controls flat overall,
86 dB
Rg = 1 kΩ
Output at maximum attenuation V
O
min VIN= 1 Vrms, f = 1 kHz, main volume –∞ –90 dB
Output noise voltage
V
N
(1) With all controls flat overall (IHF-A), Rg = 1 kΩ 3.9 µV
V
N
(2) With all controls flat overall (DIN-AUDIO), Rg = 1 kΩ 5.4 µV
Current drain I
DD
VDD– VSS= 11 V 25 33 mA
Input high level current I
IH
CL, DI, CE, VIN= 11 V 10 µA
Input low level current I
IL
CL, DI, CE, VIN= 0 V –10 µA
Parameter Symbol Conditions min typ max Unit
Input offset voltage V
IO
–10 +10 mV
Input offset current I
IO
VSS≤ VIN≤ V
DD
±10 nA
Open-loop voltage gain A
O
80 dB
Width of 0 dB band f
T
2.5 MHz
Allowable load resistance R
L
3 kΩ
Page 3
Equivalent Block Diagram and Sample Application Circuit
No. 5466-3/17
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Page 4
Test Circuits
1. Total Harmonic Distortion
No. 5466-4/17
LC75394NE
Page 5
2. Output Noise Voltage
No. 5466-5/17
LC75394NE
Page 6
3. Crosstalk
No. 5466-6/17
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Pin Assignment
No. 5466-7/17
LC75394NE
Page 8
Pin Functions
No. 5466-8/17
LC75394NE
Pin No. Symbol Function Note
12
11
10
37
38
39
9
8
7
40
41
42
6
5
4
43
44
45
3
2
1
46
47
48
13
36
14
35
64
49
21
19
17
16
28
30
32
33
57
22, 26
27
LF1C1
LF1C2
LF1C3
RF1C1
RF1C2
RF1C3
LF2C1
LF2C2
LF2C3
RF2C1
RF2C2
RF2C3
LF3C1
LF3C2
LF3C3
RF3C1
RF3C2
RF3C3
LF4C1
LF4C2
LF4C3
RF4C1
RF4C2
RF4C3
LTIN
RTIN
LSELO
RSELO
LF5
RF5
L1
L2
L3
L4
R1
R2
R3
R4
V
DD
V
SS
AV
SS
F1 band control block for left channel. Connect to external
capacitors.
F1 band control block for right channel. Connect to external
capacitors.
F2 band control block for left channel. Connect to external
capacitors.
F2 band control block for right channel. Connect to external
capacitors.
F3 band control block for left channel. Connect to external
capacitors.
F3 band control block for right channel. Connect to external
capacitors.
F4 band control block for left channel. Connect to external
capacitors.
F4 band control block for right channel. Connect to external
capacitors.
Tone control inputs. Must be driven with low-impedance
circuits.
Input selector outputs
F5 band control block. Connect to external capacitors.
Signal inputs
Power supply connection
Grounds for internal logic
Ground for internal operational amplifier
Continued on next page.
Page 9
Continued from preceding page.
No. 5466-9/17
LC75394NE
Pin No. Symbol Function Note
56
63
50
15
34
62
51
61
52
60
53
58
55
25
24
23
18
20
29
31
54
59
Vref
LVref
RVref
LINVIN1
RINVIN1
LINVIN2
RINVIN2
LTOUT
RTOUT
LVRIN
RVRIN
LVROUT
RVROUT
CE
DI
CL
NC
NC
NC
NC
NC
NC
V
DD
/2 voltage generator block. Connect capacitors between
Vref and V
SS
to minimize the effects of power supply ripple.
Pins common to volume control, tone control, and input
selection blocks. Select the capacitors between these pins
and V
SS
carefully as they contribute residual resistance
when the volume is turned down. The voltage must never
exceed V
DD
.
Operational amplifier inverted input for specifying input gain.
Operational amplifier inverted input for specifying graphic
equalization. Connecting a capacitor across INVIN2 and
TOUT permits the removal of unwanted bands and reduces
the risk of oscillation.
Tone control output
Volume control input. Must be driven with low-impedance
circuits.
Volume control output
Chip enable pin. The chip uses falling edge timing to write
data to the internal latch and shift analog switches. The high
level enables data transfer.
Serial data and clock input used for control
Leave unconnected
Page 10
Input Block Internal Equivalent Circuit Diagram
Volume Control Block Internal Equivalent Diagram
No. 5466-10/17
LC75394NE
Page 11
Equalizer Control Block Internal Equivalent Circuit (Bands F1 to F4)
Calculating the Size of External Capacitors
The LC75394NE supports four bands with peaking characteristics and one band with shelving characteristics
1. Peaking Characteristics (bands F1 to F4)
The external capacitor functions as the structural element of a simulated inductor. The equivalent circuit and the
calculations required to achieve the desired center frequency are shown below.
• Equivalent circuit for the simulated inductor
No. 5466-11/17
LC75394NE
Page 12
• Calculation example
Specifications: Central frequency, FO= 107 Hz
Q factor at maximum boost, Q
+10 dB
= 0.8
— Calculate QO, the sharpness of the simulated inductance itself.
QO= (R1 + R4)/R1 × Q
+10dB
Note: R4 is from the separately issued internal block diagram.
≠ 4.270
— Calculate C1
C1 = 1/2πFOR1QO≠ 0.536 (µF)
— Calculate C2
C2 = QO/2πFOR2 ≠ 0.021 (µF)
• Sample results
• Shelving characteristics (Band F5)
Achieving the desired control of 2-dB steps over the range between +10 dB to –10 dB requires choosing a
capacitor, C3, with an impedance of 650 Ω.
No. 5466-12/17
LC75394NE
Central frequency C1 C2
F
O
(Hz) (F) (F)
107 0.536 µ 0.021 µ
340 0.169 µ 6663
P
1070 0.054 µ 2117
P
3400 0.017 µ 666
P
Page 13
Control System Timing and Data Formats
The LC75394NE receives its control sequences via a serial interface comprised of pins CE, CL, and DI. Each sequence
consists of 40 bits: an 8-bit address followed by 32 bits of data.
No. 5466-13/17
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No. 5466-14/17
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No. 5466-15/17
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Page 16
Usage Notes
1. When the power is first applied, the internal analog switches are in indeterminate states. The chip therefore requires
muting or other external measures until it has received the proper data.
2. Provide grounding patterns or shielding for the lines to the CL, DI, and CE pins so as to prevent their high-frequency
data signals from interfering with the operation of nearby analog circuits.
No. 5466-16/17
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No. 5466-17/17
LC75394NE
This catalog provides information as of September, 1996. Specifications and information herein are subject to
change without notice.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
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