Page 1
Overview
The LC75371M is an electronic tone/volume control LSI
that can implement, with minimal external components,
volume, balance, fader, bass and treble, loudness, input
switching, and input level controls.
Functions
• Volume control: From 0 to –79 dB in 1-dB steps plus
–∞ for a total of 81 settings. Since the left and right
levels can be set independently, this function can also be
used to implement a balance function.
• Fader: Attenuates either the rear or front channels to
one of 16 levels. (Provides 16 settings, namely, from 0
to –20 dB in 2-dB steps, from –20 to –25 dB in one
5-dB step, from –25 to –45 dB in 10-dB steps, –60 dB,
and –∞.)
• Bass and treble controls: Forms an NF-type tone control
circuit (LUX type) using external capacitors. Provides
15 settings each for the bass and treble controls.
• Loudness control: A loudness function can be
implemented by attaching external RC circuits at the
taps provided from the volume control resistor ladder
starting at the –20-dB position.
• The input signal can be selected from one of three inputs
for each of the left and right channels. The input signal
can be amplified by between 0 and +18 dB in 6-dB steps.
• Serial data input: Supports CCB* format communication
with the system controller.
Features
• Built-in buffer amplifiers allow applications to be
implemented with few external components.
•A VDD/2 reference voltage generation circuit is provided
on chip.
Package Dimensions
unit: mm
3204-MFP36S
CMOS LSI
53096HA (OT) No. 5348-1/17
SANYO: MFP36S
[LC75371M]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
Car Stereo Electronic Tone
and Volume Control
LC75371M
Ordering number : EN5348
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Page 2
No. 5348-2/17
LC75371M
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V
Allowable Operating Ranges at Ta = 25°C, VSS= 0 V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max V
DD
12 V
Maximum input voltage V
IN
max CL, DI, CE, LIN, RIN, LFIN, RFIN, L1 to L3, R1 to R3 VSS– 0.3 to VDD+ 0.3 V
Allowable power dissipation Pd max Ta ≤ 85°C 230 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –50 to +125 °C
Parameter Symbol Conditions min typ max Unit
Supply voltage V
DD
V
DD
6.0 11.0 V
Input high-level voltage V
IH
CL, DI, CE 4.0 V
DD
V
Input low-level voltage V
IL
CL, DI, CE V
SS
1.0 V
Input voltage amplitude V
IN
CL, DI, CE, LIN, RIN, LFIN, RFIN, L1 to L3, R1 to R3 V
SS
V
DD
Vp-p
Input pulse width t
øW
CL 1 µs
Setup time tsetup CL, DI, CE 1 µs
Hold time thold CL, DI, CE 1 µs
Operating frequency fopg CL 500 kHz
Page 3
No. 5348-3/17
LC75371M
Electrical Characteristics at Ta = 25°C, VDD= 9 V, VSS= 0 V
Parameter Symbol Conditions min typ max Unit
[Input Block]
Input resistance Rin L1 to L3, R1 to R3 30 50 70 kΩ
Minimum input gain Gin min –2 0 +2 dB
Maximum input gain Gin max +16.0 +18.0 +20.0 dB
Step resolution Gstep +6.0 dB
[Volume Control Block]
Input resistance
Rv10 LIN, RIN: 10-dB steps, loudness off 30 50 70 kΩ
Rv1 1-dB steps 6 10 14 kΩ
Step resolution ATstep 1 dB
Step error ATerr
step = 0 to –20 dB –1 0 +1 dB
step = –20 to –50 dB –3 0 +3 dB
[Fader Block]
Input resistance Rfed LFIN, RFIN 12 20 28 kΩ
step = 0 to –20 dB 2 dB
Step resolution ATstep step = –20 to –25 dB 5 dB
step = –25 to –45 dB 10 dB
Step error ATerr
step = 0 to –45 dB –2 0 +2 dB
step = –45 dB –3 0 +3 dB
Output load resistance R
L
LFOUT, LROUT, RFOUT, RROUT 20 kΩ
[Bass and Treble Control Block]
Bass control range Gbass Max. boost/cut ±9 ±10.5 ±12 dB
Treble control range Gtre Max. boost/cut ±8 ±10.5 ±13 dB
[Overall Characteristics]
Total harmonic distortion
THD1 V
IN
= 1 Vrms, f = 1 kHz, all settings flat overall 0.045 %
THD2 V
IN
= 1 Vrms, f = 20 kHz, all settings flat overall 0.045 %
Crosstalk CT
V
IN
= 1 Vrms, f = 1 kHz, all settings flat overall,
70 dB
Rg = 1 kΩ
V
IN
= 1 Vrms, f = 1 kHz, main volume control at –∞ –76 dB
Output at maximum attenuation V
O
min
V
IN
= 1 Vrms, f = 1 kHz, main volume control at –∞,
–80 dB
INMUTE
Output noise voltage
V
N
1 All settings flat overall (IHF-A), Rg = 1 kΩ 12 30 µV
V
N
2 All settings flat overall (DIN-AUDIO), Rg = 1 kΩ 16 40 µV
Current drain I
DD
VDD– VSS= 11 V 19 22.8 mA
Input high-level current I
IH
CL, DI, CE: VIN= 9 V 10 µA
Input low-level current I
IL
CL, DI, CE: VIN= 0 V –10 µA
Maximum input level V
CL
THD = 1%, RL= 20 kΩ, all tsettings flat overall,
2 Vrms
test point = fader output.
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No. 5348-4/17
LC75371M
Equivalent Circuit Block Diagram and Sample Application Circuit
Page 5
No. 5348-5/17
LC75371M
Test Circuits
1. Total harmonic distortion
2. Output noise voltage
Page 6
No. 5348-6/17
LC75371M
3. Crosstalk
Pin Assignment
Page 7
No. 5348-7/17
LC75371M
Pin Functions
Pin No. Symbol Function Notes
Loudness circuit connections. Connect high-frequency compensation
capacitors between the LCT1/RCT1 and LIN/RIN pins, and connect lowfrequency compensation capacitors between LCT2/RCT2 and Vref2.
LCT1
LCT2
RCT1
RCT2
10
9
27
28
Connections for the bass and treble supplementary capacitors for the tone
control circuit
Connect high-frequency compensation capacitors between the T1/T2 pairs.
Connect low-frequency compensation capacitors between the T2/T3 pairs.
LT1
LT2
LT3
RT1
RT2
RT3
8
7
6
29
30
31
Tone control outputs
LOUT
ROUT
5
32
• Fader inputs
• These inputs must be driven by low-impedance outputs.
LFIN
RFIN
4
33
• Fader outputs. The front and rear can be attenuated independently. The left
and right attenuation levels are identical.
• These are low-impedance outputs, since they have built-in operational
amplifiers.
LROUT
LFOUT
RROUT
RFOUT
2
3
35
34
V
DD
/2 voltage generation block. A capacitor must be connected between Vref1
and V
SS
to suppress power supply ripple.
Vref136
• Common pin for the main volume control block, fader block, tone control
block, gain control block, and input switching block.
• Since the capacitor connected between Vref2 and V
SS
becomes the residual
resistance when the volume control is set to maximum attenuation, the value
of this capacitor must be selected carefully.
• The voltage applied to this pin must never exceed V
DD
.
Vref21
Continued on next page.
Page 8
No. 5348-8/17
LC75371M
Continued from preceding page.
Pin No. Symbol Function Notes
Test pin. This pin must be left open.TEST21
Serial data and clock inputs for LSI control.
DI
CL
18
19
Chip enable. Data is loaded into the internal latch when this pin goes from high
to low, and all analog switches operate at that time. Data transfers are enabled
when this pin is high.
CE17
Ground
V
SS
20
Power supply
V
DD
16
Signal inputs
L1
L2
L3
R1
R2
R3
15
14
13
22
23
24
Input selector outputs
LSELO
RSELO
12
25
• Main volume control inputs
• These inputs must be driven by low-impedance outputs.
LIN
RIN
11
26
Page 9
No. 5348-9/17
LC75371M
Input Block Equivalent Circuit Diagram
Main Volume Control Block Equivalent Circuit Diagram
Page 10
No. 5348-10/17
LC75371M
Tone Control Block Equivalent Circuit Diagram
Page 11
No. 5348-11/17
LC75371M
Fader Block Equivalent Circuit Diagram
Page 12
No. 5348-12/17
LC75371M
Sample Calculation of the Loudness Circuit External Constants
First, see the LC75371M 10-dB step internal equivalent circuit shown on page 9. Figure 1 below shows a version of that
circuit to which the loudness circuit external components have been added, and which has been simplified for this
calculation. The sample calculation below uses this circuit diagram to acquire a 5-dB boost at f = 100 Hz.
(f = 100 Hz, 5-dB boost)
Assuming that the resistors and capacitors in Figure 1 have the following values:
R1 = R2 = 50 kΩ
R3 = 5 kΩ
And C1 = Z1 and C2 = Z2.
Then:
From the above equations we find:
Z1 = 891.5 kΩ and Z2 = 880 Ω.
Therefore, the specifications will be met if capacitors that have these impedances at f = 1 kHz are connected externally.
The result is that C1 = 178.5 pF and C2 = 0.18 µF.
Figure 1
R2 (R3 + Z2)
R2 + R3 + Z2
R1 · Z1
R1 + Z1
V
OUT
=
(at = 1 kHz)
= –20 dB
+
R2 (R3 + Z2)
R2 + R3 + Z2
R2 (R3 + 10 · Z2)
R2 + R3 + 10 · Z2
R1 · 10 · Z1
R1 + 10 · Z1
V
OUT
=
(at = 100 Hz)
= –15 dB
+
R2 (R3 + 10 · Z2)
R2 + R3 + 10 · Z2
Page 13
No. 5348-13/17
LC75371M
Control System Timing and Data Format
The LC75371M is controlled by applying data in the stipulated format to the CE, CL, and DI pins. The data consists of
40 bits, of which 8 bits are the chip address and 32 bits are the data.
Note: The bits D19 and D28 to D31 are LSI test bits, and must be set to 0.
Page 14
No. 5348-14/17
LC75371M
Page 15
No. 5348-15/17
LC75371M
Page 16
No. 5348-16/17
LC75371M
Page 17
No. 5348-17/17
LC75371M
This catalog provides information as of December, 1997. Specifications and information herein are subject to
change without notice.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Usage Notes
1. The states of the internal analog switches are undefined when power is first applied. Use an external muting circuit or
other technique to mute the outputs until correct control data has been set up in the LC75371M.
2. Either cover the lines connected to the CL, DI, and CE pins with the ground pattern or use shielded cable for those
lines to prevent the high-frequency digital signals on those lines from entering the analog system.
3. Muting by input switching must be used in conjunction with the volume control setting when the maximum volume
control attenuation (the VOL = –∞ position) is used.
4. Since there is significant sample-to-sample variation in the magnitude of the main volume switching noise, request a
switching noise verification sample to verify the maximum switching noise.
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