Datasheet LC74798M, LC74798 Datasheet (SANYO)

Page 1

Overview

The LC74798 and LC74798M are on-screen display controller CMOS ICs that display characters and patterns on the TV screen under microprocessor control. These ICs include a built-in PDC/VPS/UDT interface circuit.

Features

• Display format: 24 characters by 12 rows (Up to 288 characters)

• Character format: 12 (horizontal) × 18 (vertical) dots

• Character sizes: Three sizes each in the horizontal and vertical directions

• Characters in font: 128

• Initial display positions: 64 horizontal positions and

64 vertical positions

• Blinking: Specifiable in character units

• Blinking types: Two periods supported: 1.0 second and

0.5 second

• Blanking: Over the whole font (12 × 18 dots)

• Background color

— 8 colors (internal synchronization mode): 4fSC — 6 colors (internal synchronization mode): 2fSC — Blue background only: NTSC

• Line background color

— Three lines can be set up. — 8 line background colors (in internal synchronization

mode): 4fSC

— 6 line background colors (in internal synchronization

mode): 2fSC

• External control input: 8-bit serial input format

• On-chip sync separator and AFC circuits

• On-chip PDC/VPS/UDT interface circuit

• Video outputs: PAL and NTSC format composite video

outputs

• Package: DIP30SD (400 mil)

MFP30S (375 mil)

Package Dimensions

unit: mm

3193-DIP30SD

unit: mm

3216-MFP30S

CMOS IC

51898RM (OT) No. 5833-1/32

SANYO: DIP30SD

[LC74798]

SANYO: MFP30S

[LC74798M]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

On-Screen Display Controller IC

LC74798, 74798M

Ordering number : EN5833

Page 2

Pin Assignment

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LC74798, 74798M

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No. 5833-3/32

LC74798, 74798M

Pin Descriptions

Pin No. Pin name Function Notes

Ground Ground connection (digital system ground)1

VSS1

Crystal oscillator (MUTE input)

These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the Xtal

OUT

pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)

Crystal oscillator input switching (CHABLK output)

Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character · frame) output. This is a 3-value output.

Xtal

OUT

(MUTE)

CTRL1

(CHABLK)

Enable input 2

Enable input for the PDC/VPS data output. Data output is enabled when this input is low. A pull-up resistor is built in and the input has hysteresis characteristics.

5 CS2

Clock input 2

Clock input for the PDC/VPS data output. A pull-up resistor is built in and the input has hysteresis characteristics.

6 SCLK2

Data output

PDC/VPS data output. (This can be either an n-channel open-drain output or a CMOS output.)

7DOUT

External synchronizing signal judgment output

Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs the crystal oscillator clock when CS1 and RST are low. (This signal is not output on command resets.)

SYNC

JDG

Enable input 1

Enable input for the OSD serial data input. Serial data input is enabled when this pin is low. A pull-up resistor is built in and the input has hysteresis characteristics.

9 CS1

Clock input 1

Serial data input enable pin. A pull-up resistor is built in and the input has hysteresis characteristics.

10 SCLK1

Data input 1 Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics.11 SIN1 Power supply Composite video signal level adjustment power supply (analog system power supply)12

VDD2

Charge pump output Charge pump output. Connect a low-pass filter to this pin.13

OUT

Oscillator control voltage input VCO oscillator control voltage input. (For data slicing)14 VCOIN Ground Ground (VCO ground)15

VSS3

Oscillator range adjustment VCO oscillator range adjustment resistor connection16

VCO

Oscillator control voltage input 2 VCO oscillator control voltage input. For character display.17

VCOIN2

Power supply (+5 V) Power supply (+5 V: VCO power supply)18

VDD3

Video signal output Composite video signal output19

OUT

Ground Ground (analog system ground)20

VSS2

Video signal input Composite video signal input21

Video signal input SECAM chrominance signal input22

Power supply (+5 V) Power supply (+5 V: digital system power supply)23

VDD1

Sync separator circuit input Video signal input to the internal sync separator circuit24

SYN

Sync separator circuit adjustment Internal sync separator circuit adjustment25 SEPC

Composite synchronizing signal output

Internal sync separator circuit composite synchronizing signal output. Can be switched to function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is high.

SEP

OUT

Vertical synchronizing signal input

Inputs the vertical synchronizing signal created by integrating the SEP

OUT

pin output signal. An integration circuit must be connected between this pin and the SEP

OUT

pin. This pin

must be tied to V

1 if unused. This pin is valid when CTL3 is set high.

SEP

Background color phase adjustment Background color phase adjustment resistor connection28 CDLR

Reset input

System reset input. A pull-up resistor is built in and the input has hysteresis characteristics.

29 RST

Power supply (+5 V) Power supply (+5 V: digital system power supply)30

VDD1

Note *: A capacitor of at least 2000 pF must be connected between the VDD1 power supply and VSS1.

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No. 5833-4/32

LC74798, 74798M

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max VDD1 and VDD2V

– 0.3 to VSS+ 7.0 V

Maximum input voltage V

All input pins VSS– 0.3 to VDD+ 0.3 V

Maximum output voltage V

OUT

, SEP

OUT

, SYNC

JDG

VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max Ta = 25°C 350 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C

Specifications

Absolute Maximum Ratings

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

1VDD1 and VDD2 4.5 5.0 5.5 V

2VDD2 4.5 5.0 1.27 VDD1V

Input high-level voltage

1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE 0.8 VDD1V

1 + 0.3 V

2 CTRL1 0.7 VDD1V

1 + 0.3 V

Input low-level voltage

1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE VSS– 0.3 0.2 VDD1V

2 CTRL1 VSS– 0.3 0.3 VDD1V

Pull-up resistance R

RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE

25 50 90 kΩ

Applies to pins set up by options. Composite video signal input VIN1CVINand CVCR: VDD1 = 5 V 2.0 Vp-p voltage V

2 SYNIN: VDD1 = 5 V 1.5 2.0 2.5 Vp-p

Input voltage V

Xtal

(when used for external clock input)

0.10 5.0 Vp-p

= 2fsc or 4fsc: VDD1 = 5 V

Oscillator frequencies F

OSC

Xtal

and Xtal

OUT

oscillator pins (2fsc : PAL) 8.867 MHz

Xtal

and Xtal

OUT

oscillator pins (4fsc : PAL) 17.734 MHz

Allowable Operating Ranges

Note: Applications must be especially cautious about noise when using the XtalINinput pin in clock input mode.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Input off leakage current I

leak

1CVINand CV

1µA

Output off leakage current I

leak

2CV

OUT

1µA

Output high-level voltage V

OUT

, SEP

OUT

, CP

OUT

, and SYNC

JDG

3.5 V

1 = 4.5 V, IOH= –1.0 mA

Output low-level voltage V

OUT

, SEP

OUT

, CP

OUT

, and SYNC

JDG

1.0 V

1 = 4.5 V, IOL= –1.0 mA

H3.35.0V

Three-value output voltage V

CHABLK: VDD1 = 5.0 V M 1.8 2.3 V

L00.8V

RST, CS1, CS2, SIN, SCLK1, SCLK2, CTRL1, MUTE,

1µA

Input current

SEP

, VCOIN, and VCOIN2, VIN= VDD1

CTRL1, SEPIN, VCOIN, and VCOIN2, VIN= VSS1–1 µA

1: With all outputs open

40 mA

Operating mode current drain

Xtal : 17.734 MHz, VCO : 27 MHz

IDD2VDD2 : VDD2 = 5 V 20 mA

OUT:VDD

1 = 5.0 V,

(1) 0.80 V

SYNC level V

VDD2 = 5.0 V

(2) 1.00 V (3) 1.40 V

OUT:VDD

1 = 5.0 V,

(1) 1.37 V

Pedestal level V

VDD2 = 5.0 V

(2) 1.57 V (3) 1.97 V

OUT:VDD

1 = 5.0 V,

(1) 1.07 V

Color burst low level V

CBL

VDD2 = 5.0 V

(2) 1.27 V (3) 1.67 V

OUT:VDD

1 = 5.0 V,

(1) 1.67 V

Color burst high level V

CBH

VDD2 = 5.0 V

(2) 1.87 V (3) 2.27 V

Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.

Continued on next page.

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No. 5833-5/32

LC74798, 74798M

Continued from preceding page.

Notes: (1): When the sync level = 0.8 V

(2): When the sync level = 1.0 V (3): When the sync level = 1.4 V The values in parentheses for the background high and low levels are for blue background mode.

Note: The OSD timing applies when the CMOS output circuit type is used.

Parameter Symbol Conditions

Ratings

Unit

min typ max

OUT:VDD

1 = 5.0 V,

(1) 1.23 (1.16) V

Background color low level V

RSL

VDD2 = 5.0 V

(2) 1.43 (1.36) V (3) 1.83 (1.76) V

OUT:VDD

1 = 5.0 V,

(1) 2.37 (2.01) V

Background color high level V

RSH

VDD2 = 5.0 V

(2) 2.57 (2.21) V (3) 2.97 (2.61) V

OUT:VDD

1 = 5.0 V,

(1) 1.50 V

Frame level 0 V

2 = 5.0 V

(2) 1.70 V (3) 2.10 V

OUT:VDD

1 = 5.0 V,

(1) 2.08 V

Frame level 1 V

2 = 5.0 V

(2) 2.28 V (3) 2.68 V

OUT:VDD

1 = 5.0 V,

(1) 2.65 V

Character level V

CHA

VDD2 = 5.0 V

(2) 2.85 V (3) 3.25 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

OSD write (See figure 1.)

Minimum input pulse width

W (SCLK)

SCLK1 200 ns

W (CS1)

CS1 (The period when CS1 is high) 1 µs

Data setup time

SU (CS1)

CS1 200 ns

SU (SIN)

SIN1 200 ns

Data hold time

h (CS1)

CS1 2 µs

h (SIN)

SIN1 200 ns

One word write time

word

The 8-bit data write time 4.2 µs

The RAM data write time 1 µs PDC/VPS write (For the n-channel open-drain output circuit type. See figure 2)

CKCY

SCLK2 2 µs

Minimum input pulse width t

CKL

SCLK2 1 µs

CKH

SCLK2 1 µs

Setup time t

ICK

SCLK2 10 µs

Output delay time t

CKO

DOUT 0.5 µs

Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V

Page 6

Figure 1 OSD Serial Data Input Timing

Figure 2 PDC/VPS Serial Output Test Conditions (For the n-channel open-drain output circuit type.)

Note: DOUT goes to the high-impedance state while CS2 is high.

No. 5833-6/32

LC74798, 74798M

Page 7

System Block Diagram

No. 5833-7/32

LC74798, 74798M

HSYNC peak hold

(HSYNC slicing)

Data output

buffer

Output control

Data peak hold

circuit

(data slicing)

Pedestal clamp

Sync

discrimination

Composite

sync signal

separation

control

Data slicer

Serial

↓

parallel

converter

8-bit

latch

command

decoder

Horizontal

character

size

Vertical

character

size

Horizontal

size

counter

Vertical

size

counter

Horizontal

dot

counter

Horizontal

display

position

Vertical

display

position

Vertical

dot

counter

Blinking and

reverse

video control

Blinking and

reverse

video control

Display

control

RAM write

address

counter

Display RAM

Decoder

Character output

control

Background control

Video output control

Vertical

display

position

Horizontal

display

position

Line

control

counter

Decoder

Font ROM

Shift register

Character

control

counter

Timing generator

Sync signal

generator

AFC circuit

for character

display

AFC circuit

data slicing

Page 8

Display Control Commands

Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 COMMAND0: Display memory (VRAM) write address setup command 2 COMMAND1: Display character data write command 3 COMMAND2: Vertical display start position and vertical character size setup command 4 COMMAND3: Horizontal display start position and horizontal character size setup command 5 COMMAND4: Display control setup command 6 COMMAND5: Display control setup command 7 COMMAND6: Synchronizing signal detection setup command 8 COMMAND7 to COMMAND12: Display control setup commands 9 COMMAND13 to COMMAND17: VPS/PDC control commands

No. 5833-8/32

LC74798, 74798M

Display Control Command Table

First byte Second byte

Command

Command identification code

Data Data

7654321076543210 COMMAND0 1000V3V2V1V0000H4H3H2H1H0 (Write address setup) COMMAND1 10010000atc6c5c4c3c2c1c0 (Character write) COMMAND2 (Vertical character size 1010VSVSVSVS0FSVPVPVPVPVPVP and vertical display start position) 21 20 11 10 5 43210 COMMAND3 (Horizontal character size 1011HSHSHSHS00HPHPHPHPHPHP and horizontal display start position) 21 20 11 10 5 43210 COMMAND4 1100TSTRAMOSCSYS0BLKBLKBLKBKBKRVDSP (Display control) MOD ERS STP RST 2 1 0 1 0 ON COMMAND5 1101NP1NP0NONINT0RSHHLFBCLCBPHPHPH (Display control) LV2 INT 2 1 0 COMMAND6 1110SELMODDISMUT0RNRNRNSNSNSNSN (Synchronizing signal detection) 0 0 LIN 2 1 03210 COMMAND7 111100000CINCINVNPVSPMSKMSKEGL (Display control) SEL CTL SEL SEL ERS SEL COMMAND8 111100010LNALNALNALNALPALPALPA (Display control) 3210210 COMMAND9 111100100LNBLNBLNBLNBLPBLPBLPB (Display control) 3210210 COMMAND10 111100110LNCLNCLNCLNCLPCLPCLPC (Display control) 3210210 COMMAND11 1111010000VSPVSPLNCMODLNBMOD (Display control) DCK SLC SEL 3 SEL 2 COMMAND12 111101010VINVINSELHLFSELSELCTL (Display control) NP 2 22 TON 2 1 3 COMMAND13 111101100CPACPA0VPMVPMVPMVPM (VPS/PDC control) 10 3210 COMMAND14 111101110VMWVMWHBSHBSBMSEMSDCE (VPS/PDC control) SE2 SEL 2 1 COMMAND15 1111100000ECVECVECVECVECVECV (VPS/PDC control) 15 14 13 12 11 5 COMMAND16 111110010ECPECPECPECPECPECPECP (VPS/PDC control) 19 18 17 16 15 14 13 COMMAND17 1111101000ECPECPECPECPECPECP (VPS/PDC control) 25 24 23 22 21 20

Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74798/M locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74798/M is set to the COMMAND0 (display memory write address setup mode) state.

Page 9

COMMAND0 (Display memory write address setup command)

COMMAND1 (Display character data write setup command)

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LC74798, 74798M

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 0 5— 0 4— 0

3V3

0 1

2V2

0 1

1V1

0 1

0V0

0 1

Command 0 identification code. Sets the display memory write address.

Display memory line address (0 to B hexadecimal)

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6— 0 5— 0

4H4

0 1

3H3

0 1

2H2

0 1

1H1

0 1

0H0

0 1

Display memory column address (0 to 17 hexadecimal)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 0 5— 0 4— 1 3— 0 2— 0 1— 0 0— 0

Command 1 identification code. Sets up display character data write mode.

When this command is input, the LC74798/M locks in the display character data write mode until the CS pin goes high

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LC74798, 74798M

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7at

0 Character attribute off 1 Character attribute on

6c6

0 1

5c5

0 1

4c4

0 1

3c3

0 1

2c2

0 1

1c1

0 1

0c0

0 1

Character code (00 to 7F hexadecimal)

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

COMMAND2 (Vertical display start position and vertical character size setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 0 5— 1 4— 0

3 VS21

0 1

2 VS20

0 1

1 VS11

0 1

0 VS10

0 1

Command 2 identification code. Sets the vertical display start position and the vertical character size.

Second line vertical character size

First line vertical character size

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6FS

0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc

VP5 0

(MSB) 1

4 VP4

0 1

3 VP3

0 1

2 VP2

0 1

1 VP1

0 1

VP0 0

(LSB) 1

The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H.

If VS is the vertical display start position then:

VS = H ×(2 ∑ 2nVPn

)

n=0

H: the horizontal synchronization pulse period

Character

display area

01 0 1H/dot 2H/dot 1 3H/dot 1H/dot

VS21

VS20

01 0 1H/dot 2H/dot 1 3H/dot 1H/dot

VS11

VS10

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LC74798, 74798M

COMMAND3 (Horizontal display start position and horizontal size setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 0 5— 1 4— 0

3 HS21

0 1

2 HS20

0 1

1 HS11

0 1

0 HS10

0 1

Command 3 identification code. Sets the horizontal display start position and the horizontal character size.

Second line horizontal character size

First line horizontal character size

01 0 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot

HS21

HS20

01 0 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot

HS11

HS10

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6— 0

HP5 0

(MSB) 1

4 HP4

0 1

3 HP3

0 1

2 HP2

0 1

1 HP1

0 1

HP0 0

(LSB) 1

If HS is the horizontal start position then:

HS = Tc ×(2 ∑ 2nVPn

)

n=0

Tc: Period of the oscillator in operating mode.

The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc.

Page 12

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 BLK2

0 Character display area 1 Video display area

5 BLK1

0 1

4 BLK0

0 1

3 BK1

0 Blinking period: About 0.5 s 1 Blinking period: About 1.0 s

2 BK0

0 Blinking off 1 Blinking on

1RV

0 Reverse video off 1 Reverse video on

0 DSPON

0 Character display off 1 Character display on

Changes the blanking size

Switches the blinking period

Blinking in reverse video mode switches the display between normal character display and reverse video display

Specifies the size for complete fill in

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LC74798, 74798M

COMMAND4 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 0

3 TSTMOD

0 Normal operating mode 1 Test mode

2 RAMERS

0 1 Erase display RAM. (The RAM data is set to 7F hexadecimal.)

1 OSCSTP

0 Do not stop the crystal and VCO oscillators

1 Stop the crystal and VCO oscillators

0 SYSRST

0 1 Reset all registers and turn display off

Command 4 identification code. Display character data write setup.

This bit must be set to 0

Erasing RAM takes about 500 µs. (This operation must be executed in the DSPOFF state.)

Valid in external synchronization mode when character display is off. It will no longer be possible to detect VPS/PDC data

The registers are reset when the CS pin is low, and the reset state is cleared when CS is set high

01 0 Blanking off Character size 1 Frame size Complete fill in size

BLK1

BLK0

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LC74798, 74798M

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 RSHLV2

0 Background color level 1 (level that is different from blue) 1 Background color level 2 (level that is identical to the blue level)

5HLFINT

0 Normal mode 1 Partial internal synchronization mode

4 BCL

0 Background color on 1 No background color (Only the background level is set)

3CB

0 Color burst signal output 1 Color burst signal output stopped

2 PH2

1 PH1

0 PH0

Only valid in internal synchronization mode

Only valid when BCL is high

Background color specification

*: When 2fsc is used.

Switches the background color signal level

COMMAND5 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 0 4— 1

3 NP1

0NTSC 1PAL

2 NP0

0 525 lines 1 625 lines

1 NON

0 Interlaced 1 Noninterlaced

0INT

0 External synchronization 1 Internal synchronization

Command 5 identification code. Display control setup.

Switches between NTSC and PAL

Modified by the external input signal V

Switches between interlaced and noninterlaced video

Switches between external and internal synchronization

PH2 PH1 PH0 Background color (phase)

000 Cyan* 0 0 1 Yellow* 0 1 0 Red* 011 Blue* 1 0 0 Cyan blue 1 0 1 Green* 1 1 0 Orange 1 1 1 Magenta*

Page 14

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LC74798, 74798M

COMMAND6 (Synchronizing signal detection setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 0

3 SEL0

0 1

2 MOD0

0 1

1DISLIN

0 12 lines 1 10 lines

0 MUT

0 Normal output 1CV

is cut and CV

OUT

is held at the pedestal level

Command 6 identification code. Sets up synchronizing signal control.

Switches the SEP

OUT

(pin 26) output

Switches the number of lines displayed

OUT

switching

01 0 DAV Sliced data width 1 CSYNC ST.PULSE

SEL0

MOD0

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 RN2

0 1

5 RN1

0 1

4 RN0

0 1

3 SN3

0 1

2 SN2

0 1

1 SN1

0 1

0 SN0

0 1

External synchronizing signal detection control. Signal present → signal absent transition detection. Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H).

External synchronizing signal detection control. Signal absent → signal present transition detection. Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H).

RN2 RN1 RN0 Number of times HSYNC detected

0 0 0 32 times 0 0 1 4 times 0 1 0 8 times 1 0 0 16 times

SN3 SN2 SN1 SN0 Number of times HSYNC detected

0 0 0 0 Not detected 0001 32 times 0010 64 times 0 1 0 0 128 times 1 0 0 0 256 times

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LC74798, 74798M

COMMAND7 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 0 1— 0 0— 0

Command 7 identification code. Display control setup.

Extended command 0 identification code

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 CINSEL

0 Blank area (the logical OR of the character and frame signals) 1 Video signal display area

5 CINCTL

0CV

: off

1CV

: on

4 VNPSEL

0 V falling edge detection 1 V rising edge detection

3 VSPSEL

0 VSEP: about 8.9 µs (for NTSC) 1 VSEP: about 17.8 µs (for NTSC)

2 MSKERS

0 Mask valid 1 Mask invalid

1 MSKSEL

0 3H (NTSC) 1 20H (NTSC)

0EGL

0 Frame level 0 only (V

BK0

)

1 Two-stage frame level (V

BK0

and V

BK1

)

CVCRon/off switching

Switches the V acquisition polarity in external mode when internal V separation is used

Switches the internal V separation period

Clears the HSYNC and VSYNK masks

Switches the VSYNC mask

Switches the frame level. (Only valid when BLK0 is 0 and BLK1 is 1.)

on signal switching

Page 16

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COMMAND8 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 0 1— 0 0— 1

Command 7 identification code. Display control setup.

Extended command 1 identification code

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNA3

5 LNA2

4 LNA1

3 LNA0

2 LPA2

1 LPA1

0 LNA0

Specifies the background color

Specifies the line whose background is to be changed. (This specification is illegal for the same line as LNA*, LNB*, and LNC*)

LNA3 LNA2 LNA1 LNA0 Specified line

0 0 0 0 Do not change the line background 0001 Line 1 0010 Line 2 0011 Line 3 0100 Line 4 0101 Line 5 0110 Line 6 0111 Line 7 1000 Line 8 1001 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12

*: When 2fsc is used.

LPA2 LPA1 LPA0 Background color (phase)

000 Cyan* 0 0 1 Yellow* 010 Red* 011 Blue* 1 0 0 Cyan blue 1 0 1 Green* 1 1 0 Orange 1 1 1 Magenta*

Page 17

No. 5833-17/32

LC74798, 74798M

COMMAND9 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 0 1— 1 0— 0

Command 7 identification code. Display control setup.

Extended command 2 identification code

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNB3

5 LNB2

4 LNB1

3 LNB0

2 LPB2

1 LPB1

0 LNB0

Specifies the background color

Specifies the line whose background is to be changed. (This specification is illegal for the same line as LNA*, LNB*, and LNC*)

LNB3 LNB2 LNB1 LNB0 Specified line

*: When 2fsc is used.

LPB2 LPB1 LPB0 Background color (phase)

000 Cyan* 0 0 1 Yellow* 010 Red* 011 Blue* 1 0 0 Cyan blue 1 0 1 Green* 1 1 0 Orange 1 1 1 Magenta*

Page 18

No. 5833-18/32

LC74798, 74798M

COMMAND10 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 0 1— 1 0— 1

Command 7 identification code. Display control setup.

Extended command 3 identification code

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNC3

5 LNC2

4 LNC1

3 LNC0

2 LPC2

1 LPC1

0 LNC0

Specifies the background color

Specifies the line whose background is to be changed. (This specification is illegal for the same line as LNA*, LNB*, and LNC*)

LNC3 LNC2 LNC1 LNC0 Specified line

*: When 2fsc is used.

LPC2 LPC1 LPC0 Background color (phase)

000 Cyan* 0 0 1 Yellow* 010 Red* 011 Blue* 1 0 0 Cyan blue 1 0 1 Green* 1 1 0 Orange 1 1 1 Magenta*

Page 19

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LC74798, 74798M

COMMAND11 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 1 1— 0 0— 0

Command 7 identification code. Display control setup.

Extended command 4 identification code

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6— 0

5 VSPDCK

0 Character display VCO operating 1 Character display VCO stopped

4 VSPSLC

0 Data slice VCO operating 1 Data slice VCO stopped

3 LNCSEL

0 Normal line background color operation

2 MOD3

0 The LNCSEL = 1 setting specifications

1 LNBSEL

0 Normal line background color operation

0 MOD2

0 The LNBSEL = 1 setting specifications

Character display VCO control

Data slice VCO control

Switches the RV mode background color for the line specified by LNB* for characters specified for RV display

Valid when LNCSEL is high

Switches the RV mode background color for the line specified by LNB* for characters specified for RV display

Valid when LNBSEL is high

RV characters have the background color specified by PH* and the RV character background color is white

RV characters have the background color specified by PH* and characters are white

RV characters have the background color specified by PH* and the RV character background color is white.

RV characters have the background color specified by PH* and characters are white

Page 20

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LC74798, 74798M

COMMAND12 (Display control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 1 1— 0 0— 1

Command 7 identification code. Display control setup.

Extended command 5 identification code

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 VINNP

0 Negative CSYNC input polarity 1 Positive CSYNC input polarity

5VIN2

0 Normal input 1 CSYNC input to the SEP

4 SEL22

3 HLFTON

2 SEL2

1 SEL1

0 Vertical synchronization signal input (external synchronization) 1 Frame signal input

0 CTL3

0 Internal V separation used 1 Internal V separation not used (external V separation)

CSYNC input polarity selection

SEP

pin input switching

SYNC

JDG

pin (pin 8) output switching. The halftone output line specification depends on background color specification (the logical or of the 3-line specification) SYNCDET2: Used for character display LOCK2: Used for character display

SEPIN (pin 27) input switching. Only valid when CTL3 is high.

V separation switching

SEL22 SEL2 HLFTOM Output

0 0 0 SYNC

JDG

0 0 1 Halftone 010 O/E 011 LOCK 1 0 0 SYNDET2 1 0 1 SENDET 1 1 0 LOCK2

Page 21

No. 5833-21/32

LC74798, 74798M

COMMAND13 (VPS/PDC control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 1 1— 1 0— 0

Command 7 identification code. Display control setup.

Extended command 6 identification code

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 CPA1

5 CPA0

4— 0

3 VPM3

2 VPM2

1 VPM1

0 VPM0

Data acquisition clock switching

CPA1 CPA0 Clock

00No.4 01No.3 10No.2 11No.1

VPM3 VPM2 VPM1 VPM0 Operating mode

0000 VPS 0 0 0 1 8/30/2 (PDC) 0 0 1 0 Automatic PDC/VPS switching 0 0 1 1 8/30/1 (UDT) 0 1 0 0 Header time 1 0 1 0 1 Header time 2 0 1 1 0 Header time 3 0 1 1 1 Header time 4 1 0 0 0 Status display 1 1 0 0 1 Status display 2 1 0 1 0 Status display 3 1 0 1 1 Status display 4 1 1 0 0 PAL Pulse 1 1 0 1 Automatic PDC/VPS switching 2

Page 22

No. 5833-22/32

LC74798, 74798M

COMMAND14 (VPS/PDC control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 0 2— 1 1— 1 0— 1

Command 7 identification code. Display control setup.

Extended command 7 identification code

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

• Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 VMWSE2

0 V mask period start - From the retrace period 1 V mask period start - From 10H before the retrace period

5 VMWSEL

0 The V mask period is the retrace period 1 The V mask period is 9H

4 HBS2

0 Discrimination mode 1 1 Discrimination mode 2

3 HBS1

0 Discrimination mode 1 1 Discrimination mode 2

2BMS

1EMS

0 Data hold

0 DCE

CPOUT pin (pin 13) V mask period switching

Clock line

Framing code

When set to 0, if there are no errors in bytes for which error checking is turned on, those bytes are written to P-S. When set to 1, all bytes are written to P-S regardless of the error status.

Specifies handling of bytes for which error checking is set to off but in which an error occurred when error checking is turned on.

Error checking setting for unused data bytes. Biphase (VPS), Hamming (PDC), and odd parity (header).

Error check valid (Error checking can be turned on or off on a per-byte basis.)

Error check invalid (Applications can select whether data for which an error is detected is held or writing on a per-byte basis.)

Data write (When the error bit is 0 in VPS mode.)

Error checking enabled for unused data bytes. VPS: bytes 3, 4, and 6 to 10, PDCC (8/30/2): bytes 7 to 12, header 1: bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35

Error checking disabled for unused data bytes. VPS: bytes 3, 4, and 6 to 10, PDCC (8/30/2): bytes 7 to 12, header 1: bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35

CPOUT pin (pin 13) V mask period switching 2

Page 23

No. 5833-23/32

LC74798, 74798M

COMMAND15 (VPS/PDC control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 1 2— 0 1— 0 0— 0

Command 7 identification code. Display control setup.

Extended command 8 identification code

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6— 0

5 ECV15

0 Byte 15 biphase error check on (Data hold) 1 Byte 15 biphase error check off (Data write)

4 ECV14

0 Byte 14 biphase error check on (Data hold) 1 Byte 14 biphase error check off (Data write)

3 ECV13

0 Byte 13 biphase error check on (Data hold) 1 Byte 13 biphase error check off (Data write)

2 ECV12

0 Byte 12 biphase error check on (Data hold) 1 Byte 12 biphase error check off (Data write)

1 ECV11

0 Byte 11 biphase error check on (Data hold) 1 Byte 11 biphase error check off (Data write)

0 ECV5

0 Byte 5 biphase error check on (Data hold) 1 Byte 5 biphase error check off (Data write)

Specification when the VPS data BMS bit is 0. The item in parentheses is the specification when the VPS data BMS bit is 1.

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LC74798, 74798M

COMMAND16 (VPS/PDC control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 1 2— 0 1— 0 0— 1

Command 7 identification code. Display control setup.

Extended command 9 identification code

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 ECP19

5 ECP18

4 ECP17

3 ECP16

2 ECP15

1 ECP14

0 ECP13

Specification when the PDC data (8/30/2) BMS bit is 0. The item in parentheses is the specification when the BMS bit is 1. The item in curl braces lists the odd parity check on/off bytes for header modes 1, 2, 3, and 4 and status mode 1, 2, 3, and 4.

Byte 19 Hamming error check on (Data hold) {Bytes 44, 28, 36, 20, 32, 42, 32, and 42}

Byte 19 Hamming error check off (Data write) {Bytes 44, 28, 36, 20, 32, 42, 32, and 42}

Byte 18 Hamming error check on (Data hold) {Bytes 43, 27, 35, 19, 31, 41, 31, and 41}

Byte 18 Hamming error check off (Data write) {Bytes 43, 27, 35, 19, 31, 41, 31, and 41}

Byte 17 Hamming error check on (Data hold) {Bytes 42, 26, 34, 18, 30, 40, 30, and 40}

Byte 17 Hamming error check off (Data write) {Bytes 42, 26, 34, 18, 30, 40, 30, and 40}

Byte 16 Hamming error check on (Data hold) {Bytes 41, 25, 33, 17, 29, 39, 29, and 39}

Byte 16 Hamming error check off (Data write) {Bytes 41, 25, 33, 17, 29, 39, 29, and 39}

Byte 15 Hamming error check on (Data hold) {Bytes 40, 24, 32, 16, 28, 38, 28, and 38}

Byte 15 Hamming error check off (Data write) {Bytes 40, 24, 32, 16, 28, 38, 28, and 38}

Byte 14 Hamming error check on (Data hold) {Bytes 39, 23, 31, 15, 27, 37, 27, and 37}

Byte 14 Hamming error check off (Data write) {Bytes 39, 23, 31, 15, 27, 37, 27, and 37}

Byte 13 Hamming error check on (Data hold) {Bytes 38, 22, 30, 14, 26, 36, 26, and 36}

Byte 13 Hamming error check off (Data write) {Bytes 38, 22, 30, 14, 26, 36, 26, and 36}

Page 25

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LC74798, 74798M

COMMAND17 (VPS/PDC control setup command)

• First byte

Contents

Notes

0 to 7 State Function

7— 1 6— 1 5— 1 4— 1 3— 1 2— 0 1— 1 0— 0

Command 7 identification code. Display control setup.

Extended command A identification code

• Second byte

Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6— 0

5 ECP25

4 ECP24

0 Byte 24 Hamming error check on (Data hold) 1 Byte 24 Hamming error check off (Data write)

3 ECP23

0 Byte 23 Hamming error check on (Data hold) 1 Byte 23 Hamming error check off (Data write)

2 ECP22

1 ECP21

0 ECP20

Specification when the PDC data (8/30/2) BMS bit is 0. The item in parentheses is the specification when the BMS bit is 1. The item in curly braces lists the odd parity check off bytes for header modes 1, 2, 3, and 4 and status mode 1, 2, 3, and 4.

Byte 22 Hamming error check on (Data hold) {Bytes -, -, -, -, 35, 45, 35, and 45}

Byte 22 Hamming error check off (Data write) {Bytes -, -, -, -, 35, 45, 35, and 45}

Byte 21 Hamming error check on (Data hold) {Bytes -, -, -, -, 34, 44, 34, and 44}

Byte 21 Hamming error check off (Data write) {Bytes -, -, -, -, 34, 44, 34, and 44}

Byte 20 Hamming error check on (Data hold) {Bytes 45, 29, 37, 21, 33, 43, 33, and 43}

Byte 20 Hamming error check off (Data write) {Bytes 45, 29, 37, 21, 33, 43, 33, and 43}

Byte 25 Hamming error check on (Data hold)

Byte 25 Hamming error check off (Data write)

Page 26

PDC/VPS Output Data Format

Data is output in order starting with bit 7 of byte 1.

No. 5833-26/32

LC74798, 74798M

Output data

PDC 8/30 mode

VPS mode Header time mode 1 (3) Header time mode 2 (4)

Format 1 Format 2

Data update bits *: Set to 0 when data is updated, and set to 1 when not updated.

Byte 1 Bit 7 byte 15 bit 0 byte 16 bit 0 byte 11 bit 0 byte 38 bit 0 byte 22 bit 0

6111(30)1(14)1 522222 433333 3 4 byte 17 bit 0 4 4 4 251555 162666 073777

Byte 2 Bit 7 byte 16 bit 0 byte 18 bit 0 byte 12 bit 0 byte 39 bit 0 byte 23 bit 0

6111(31)1(15)1 522222 433333 3 4 byte 19 bit 0 4 4 4 251555 162666 073777

Byte 3 Bit 7 byte 17 bit 0 byte 20 bit 0 byte 13 bit 0 byte 40 bit 0 byte 24 bit 0

6111(32)1(16)1 522222 433333 3 4 byte 21 bit 0 4 4 4 251555 162666 073777

Byte 4 Bit 7 byte 18 bit 0 byte 22 bit 0 byte 14 bit 0 byte 41 bit 0 byte 25 bit 0

6111(33)1(17)1 522222 433333 3 4 byte 23 bit 0 4 4 4 251555 162666 073777

Byte 5 Bit 7 byte 19 bit 0 byte 14 bit 0 byte 5 bit 0 byte 42 bit 0 byte 26 bit 0

6111(34)1(18)1 522222 433333 3 4 byte 15 bit 0 4 4 4 251555 162666 073777

Byte 6 Bit 7 byte 20 bit 0 byte 24 bit 0 byte 15 bit 0 byte 43 bit 0 byte 27 bit 0

6111(35)1(19)1 522222 433333 3 4 byte 25 bit 0 4 4 4 251555 162666 073777

Continued on next page.

Page 27

No. 5833-27/32

LC74798, 74798M

Continued from preceding page.

Output data

PDC 8/30 mode

VPS mode Header time mode 1 (3) Header time mode 2 (4)

Format 1 Format 2

Byte 7 Bit 7 byte 21 bit 0 byte 13 bit 0 1 byte 44 bit 0 byte 28 bit 0

6 1 1 1 (36) 1 (20) 1 5221 22 4331 33 3411 44 2511 55 1611 66 0711 77

Byte 8 Bit 7 byte 13 bit 0 Error byte 16 Error byte 11 byte 45 bit 0 byte 29 bit 0

6 1 information 1 17 information 1 12 (37) 1 (21) 1 5 2 18 13 2 2 4 3 19 14 3 3 3420544 2 5 21 15 5 5 16220 66 07230 77

Byte 9 Bit 7 byte 14 bit 0 Error 14 Error byte 38 (30) Error byte 22 (14)

6 1 information 2 15 information 2 39 (31) information 2 23 (15) 5 2 24 40 (32) 24 (16) 4 3 25 41 (33) 25 (17) 3 4 13 42 (34) 26 (18) 2 5 0 43 (35) 27 (19) 1 6 0 44 (36) 28 (20) 0 7 0 45 (37) 29 (21)

Byte 10 Bit 7 byte 22 bit 0

61 52 43 34 25 16 07

Byte 11 Bit 7 byte 23 bit 0

61 52 43 34 25 16 07

Byte 12 Bit 7 byte 24 bit 0

61 52 43 34 25 16 07

Byte 13 Bit 7 byte 25 bit 0

61 52 43 34 25 16 07

Bits for which data is not set are set to 1.

Page 28

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LC74798, 74798M

Data is output in order starting with bit 7 of byte 1.

1, 2 : 8/30/2 3, 4 : 8/30/1

Output data

Status display Status display

PAL Puls

mode 1 (3) mode 2 (4)

Data update bits *: Set to 0 when data is updated.

Byte 1 Bit 7 byte 26 bit 0 byte 36 bit 0 bit 0

6 (26) 1 (36) 1 1 5222 4333 3444 2555 1666 0777

Byte 2 Bit 7 byte 27 bit 0 byte 37 bit 0 bit 8

6 (27) 1 (37) 1 9 52210 43311 34412 25513 1660 0770

Byte 3 Bit 7 byte 28 bit 0 byte 38 bit 0

6 (28) 1 (38) 1 522 433 344 255 166 077

Byte 4 Bit 7 byte 29 bit 0 byte 39 bit 0

6 (29) 1 (39) 1 522 433 344 255 166 077

Byte 5 Bit 7 byte 30 bit 0 byte 40 bit 0

6 (30) 1 (40) 1 522 433 344 255 166 077

Byte 6 Bit 7 byte 31 bit 0 byte 41 bit 0

6 (31) 1 (41) 1 522 433 344 255 166 077

Byte 7 Bit 7 byte 32 bit 0 byte 42 bit 0

6 (32) 1 (42) 1 522 433 344 255 166 077

Continued on next page.

Page 29

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LC74798, 74798M

Output data

Status display Status display

PAL Puls

mode 1 (3) mode 2 (4)

Byte 8 Bit 7 byte 33 bit 0 byte 43 bit 0

6 (33) 1 (43) 1 522 433 344 255 166 077

Byte 9 Bit 7 byte 34 bit 0 byte 44 bit 0

6 (34) 1 (44) 1 522 433 344 255 166 077

Byte 10 Bit 7 byte 35 bit 0 byte 45 bit 0

6 (35) 1 (45) 1 522 433 344 255 166 077

Byte 11 Bit 7 Error byte 26 (26) Error byte 36 (36)

6 information 1 27 (27) information 1 37 (37) 5 28 (28) 38 (38) 4 29 (29) 39 (39) 3 30 (30) 40 (40) 2 31 (31) 41 (41) 1 32 (32) 42 (42) 0 33 (33) 43 (43)

Byte 12 Bit 7 Error byte 34 (34) Error byte 44 (44)

6 information 2 35 (35) information 2 45 (45) 500 400 300 200 100 000

Byte 13 Bit 7

6 5 4 3 2 1 0

Continued from preceding page.

Page 30

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LC74798, 74798M

Display Screen Structure

The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced from the 288 maximum when enlarged characters are displayed. Display memory addresses are specified as row (0 to B hexadecimal) and column (0 to 17 hexadecimal) addresses.

Display Screen Structure (display memory addresses)

24 Characters

12 Rows

Page 31

Composite Video Signal Output Levels (internally generated levels)

OUT

output level waveform (VDD2 = 5.00 V)

No. 5833-31/32

LC74798, 74798M

Output level Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V]

CHA

: Character 2.65 2.85 3.25

RSH

: Background color high 2.37 (2.01) 2.57 (2.21) 2.97 (2.61)

CBH

: Color burst high 1.67 1.87 2.27

RSL

: Background color low 1.23 (1.16) 1.43 (1.36) 1.83 (1.76)

1 : Frame 2.08 2.28 2.68

0 : Frame 1.50 1.70 2.10

: Pedestal 1.37 1.57 1.97

CBL

: Color burst low 1.07 1.27 1.67

: Sync 0.80 1.00 1.40

Note: VDD2 = 5.00V. The values in parentheses for V

RSH

and V

RSL

are the values for a blue background.

Page 32

PS No. 5833-32/32

LC74798, 74798M

This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.