Datasheet LC74794M, LC74794 Datasheet (SANYO)

Page 1

Overview

The LC74794 and LC74794M are CMOS LSIs for onscreen display, a function that displays characters and patterns on a TV screen under microprocessor control. They feature a built-in PDC/VPS/UDT interface circuit. These LSIs support 12 × 18 dot characters and can display 12 lines by 24 characters of text.

Features

• Display format: 24 characters by 12 rows (Up to 288 characters)

• Character format: 12 (horizontal) × 18 (vertical) dots

• Character sizes: Three sizes each in the horizontal and vertical directions

• Characters in font: 128

• Initial display positions: 64 horizontal positions and 64 vertical positions

• Blinking: Specifiable in character units

• Blinking types: Two periods supported: 1.0 second and

0.5 second

• Blanking: Over the whole font (12 × 18 dots)

• Background color — Background coloring: 8 colors (internal synchronization

mode): 4fsc

— Background coloring: 6 colors (internal synchronization

mode): 2fsc

— Blue background only: NTSC

• Line background color — Can be set for 3 lines — Line background coloring: 8 colors (internal synchro-

nization mode): 4fsc

— Line background coloring: 6 colors (internal synchro-

nization mode): 2fsc

• External control input: 8-bit serial input format

• On-chip sync separator and AFC circuits

• PDC/VPS/UDT interface circuit

• Composite video output in the PAL or NTSC format

Package Dimensions

unit: mm

3196-DIP30SD

unit: mm

3216A-MFP30S

CMOS LSI

Ordering number : EN*5557

22897HA (OT)/No. 5557-1/30

Preliminary

SANYO: DIP30SD

[LC74794]

SANYO: MFP30S

[LC74794M]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

On-Screen Display Controller LSI

LC74794, 74794M

Page 2

Pin Assignment

No. 5557-2/30

LC74794, 74794M

Pin Functions

Pin no. Pin Function Notes

1 V

1 Ground Ground connection (digital system ground)

2 Xtal

Crystal oscillator

These pins are used either to connect a crystal and capacitor to form an external crystal

Xtal

OUT

(MUTE input)

oscillator to generate internal synchronizing signals, or to input an external clock signal (2fsc

(MUTE)

or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin. When the MUTE pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in so the input has hysteresis characteristics.)

Switches the mode between external clock input and crystal oscillator operation. A low level

CTRL1 Crystal oscillator input switching selects crystal oscillator operation and a high level selects external clock input. As a mask

(CHABLK) (CHABLK output) option, the CTRL1 input pin can be set to function as the CHABLK (character · border)

output. This is a 3-value output.

5 CS2 Enable input 2

PDC/VPS data output enable input. Data output is enabled by a low-level input. (A pull-up resistor is built in so the input has hysteresis characteristics.)

6 SCLK2 Clock input 2

Clock input for PDC/VPS data output (A pull-up resistor is built in so the input has hysteresis characteristics.)

7 DOUT Data output

PDC/VPS data output (This is either an n-channel open-drain output or a CMOS output.)

Outputs the state of the external synchronizing signal presence/absence judgment.

8 SYNC

JDG

External synchronizing signal judgment Outputs a high level when synchronizing signals are present. output Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not

output on command resets.)

Continued on next page.

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No. 5557-3/30

LC74794, 74794M

Continued from preceding page.

Pin no. Pin Function Notes

Enable input for OSD serial data input

9 CS1 Enable input 1 Serial data input is enabled by a low-level input.

(A pull-up resistor is built in so the input has hysteresis characteristics.)

10 SCLK1 Clock input 1

Serial data clock input

(A pull-up resistor is built in so the input has hysteresis characteristics.) 11 SIN1 Data input 1 Serial data input (A pull-up resistor is built in so the input has hysteresis characteristics.) 12 V

2 Power supply Composite video signal level adjustment power supply (analog system power supply)

13 CP

OUT

Charge pump output The charge pump output. Connect a low-pass filter to this pin.

14 VCO

Oscillator control voltage input VCO control voltage input

15 V

3 Ground Ground (VCO ground)

16 V

3 Power supply (+5 V) Power supply (+5 V: VCO power supply)

17 VCO

Oscillator range adjustment Connection for the VCO range adjustment resistor 18 DAV Data present output Outputs a low level when PDC/VPS data has been received. 19 CV

OUT

Video signal output Composite video signal output 20 V

2 Ground Ground (analog system ground)

21 CV

Video signal input Composite video signal input 22 CV

Video signal input SECAM chrominance signal input 23 V

1 Power supply (+5 V) Power supply (+5 V: digital system power supply)

24 SYN

Sync separator circuit input Internal sync separator circuit video signal input 25 SEPC Sync separator circuit adjustment Internal sync separator circuit adjustment input

Composite synchronizing signal output for the built-in sync separator circuit. Can be

26 SEP

OUT

Composite synchronizing signal output switched to function as an output for the signal (high or ST. pulse) due to MOD0 by setting

SEL0 high. Inputs the vertical synchronizing signal created by integrating the SEP

OUT

pin output

27 SEPINVertical synchronizing signal input

signal. An integration circuit must be connected to the SEP

OUT

pin. This pin must be tied to VDD1

if unused.

28 CDLR Background color phase adjustment Background color phase adjustment resistor connection 29 RST Reset input

System reset input A pull-up resistor is built in so the input has hysteresis characteristics.

30 V

1 Power supply (+5 V) Power supply (+5 V: digital system power supply)

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No. 5557-4/30

LC74794, 74794M

Parameter Symbol Conditions Ratings Unit

Supply voltage V

VDD1 and VDD2 VSS– 0.3 to VSS+ 7.0 V

Input voltage V

All input pins VSS– 0.3 to VDD+ 0.3 V

Output voltage V

OUT

DAV, DOUT, SEP

OUT

, and SYNC

JDG

VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max 350 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

1 VDD1 and VDD2 4.5 5.0 5.5 V

2 VDD2 5.5 5.0 1.27 VDD1 V

RST, CS1, CS2, SIN1, SCLK1, SCLK2,

0.8 VDD1 VDD1 + 0.3 V

Input high-level voltage

and MUTE

2 CTRL1 0.7 VDD1 VDD1 + 0.3 V

RST, CS1, CS2, SIN1, SCLK1, SCLK2,

VSS– 0.3 0.2 VDD1 V

Input low-level voltage

and MUTE

2 CTRL1 VSS– 0.3 0.3 VDD1 V

Pull-up resistance R

RST, CS1, CS2, SIN1, SCLK1, SCLK2,

25 50 90 kΩ

and MUTE

Composite video signal input voltage

1 CVINand CVCR; VDD1 = 5 V 2.0 Vp-p

2 SYNIN; VDD1 = 5 V 1.5 2.0 2.5 Vp-p

Input voltage V

Xtal

(in external clock input mode)

0.10 5.0 Vp-p

fin = 2 fsc or 4 fsc ; V

1 = 5 V

Oscillator frequency

OSC

1 XtalINand Xtal

OUT

oscillator pins (2 fsc: PAL) 8.867 MHz

OSC

2 XtalINand Xtal

OUT

oscillator pins (4 fsc: PAL) 17.734 MHz

Allowable Operating Ranges at Ta = –30 to +70°C

Note: When the XtalINpin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Input off leakage current I

leak

1 CVINand CV

1 µA

Output off leakage current I

leak

2 CV

OUT

1 µA

Output high-level voltage V

DAV, DOUT, SEP

OUT

, CP

OUT

, SYNC

JDG

;

3.5 V

1 = 4.5 V, IOH= –1.0 mA

Output low-level voltage V

DAV, DOUT, SEP

OUT

, CP

OUT

, SYNC

JDG

;

1.0 V

1 = 4.5 V, IOL= 1.0 mA

CHABLK ; V

1 = 5.0 V H 3.3 5.0 V

Three-value output voltage V

M 1.8 2.3 V L 0 0.8 V

RST, CS1, CS2, SIN, SCLK1, SCLK2,

CTRL1, MUTE, SEPIN, and VCO

1 µA

Input current

= VDD1

CTRL1, SEPIN, and VCOIN; VIN= VSS1 –1 µA

1; with all outputs open

40 mA

Operating current drain

Xtal : 17.734 MHz, VCO : 27 MHz

2 VDD2; VDD2 = 5 V 20 mA

OUT

; VDD1 = 5.0 V ➀ 0.80 V

SYNC level V

VDD2 = 5.0 V ➁ 1.00 V

➂ 1.30 V

OUT

; VDD1 = 5.0 V ➀ 1.37 V

Pedestal level V

VDD2 = 5.0 V ➁ 1.57 V

➂ 1.87 V

OUT

; VDD1 = 5.0 V ➀ 1.07 V

Color burst low level V

CBL

VDD2 = 5.0 V ➁ 1.27 V

➂ 1.57 V

Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.

Continued on next page.

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No. 5557-5/30

LC74794, 74794M

Parameter Symbol Conditions

Ratings

Unit

min typ max

OUT

; VDD1 = 5.0 V ➀ 1.67 V

Color burst high level V

CBH

VDD2 = 5.0 V ➁ 1.87 V

➂ 2.17 V

OUT

; VDD1 = 5.0 V ➀ 1.23 (1.16) V

Background color low level V

RSL

VDD2 = 5.0 V ➁ 1.43 (1.36) V

➂ 1.73 (1.66) V

OUT

; VDD1 = 5.0 V ➀ 2.37 (2.01) V

Background color high level V

RSH

VDD2 = 5.0 V ➁ 2.57 (2.21) V

➂ 2.87 (2.51) V

OUT

; VDD1 = 5.0 V ➀ 1.50 V

Frame level 0 V

0 VDD2 = 5.0 V ➁ 1.70 V

➂ 2.00 V

OUT

; VDD1 = 5.0 V ➀ 2.08 V

Frame level 1 V

1 VDD2 = 5.0 V ➁ 2.28 V

➂ 2.58 V

OUT

; VDD1 = 5.0 V ➀ 2.65 V

Character level V

CHA

VDD2 = 5.0 V ➁ 2.85 V

➂ 3.15 V

Continued from preceding page.

Notes:➀ When the sync level is 0.8 V.

➁ When the sync level is 1.0 V. ➂ When the sync level is 1.3 V.

The values in parentheses for the background color high and low levels are the values for a blue background.

Note: Timings follow those for OSD write when the CMOS output circuit is used.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Minimum input pulse width

W(SCLK)

SCLK1 200 ns

W(CS1)

CS1 (The period when CS1 is high) 1 µs

Data setup time

SU(CS1)

CS1 200 ns

SU(SIN)

SIN1 200 ns

Data hold time

h(CS1)

CS1 2 µs

h(SIN)

SIN1 200 ns

One word write time

word

The time to write 8 bits of data 4.2 µs

The RAM data write time 1 µs

Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V

OSD write (See Figure 1.)

Parameter Symbol Conditions

Ratings

Unit

min typ max

CKCY

SCLK2 2 µs

Minimum input pulse width t

CKL

SCLK2 1 µs

CKH

SCLK2 1 µs

Setup time t

ICK

SCLK2 10 µs

Output delay time t

CKO

DOUT 0.5 µs

PDC/VPS reads (For the n-channel open-drain output circuit. See Figure 2.)

Page 6

Figure 1 OSD Serial Data Input Timing

Figure 2 PDC/VPS Serial Output Test Conditions (For the n-channel open-drain output)

Note: DOUT goes to the high-impedance state while CS2 is high.

No. 5557-6/30

LC74794, 74794M

Page 7

System Block Diagram

No. 5557-7/30

LC74794, 74794M

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No. 5557-8/30

LC74794, 74794M

Display Control Commands

Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 COMMAND0: Display memory (VRAM) write address setup command 2 COMMAND1: Display character data write command 3 COMMAND2: Vertical display start position and vertical character size setup command 4 COMMAND3: Horizontal display start position and horizontal character size setup command 5 COMMAND4: Display control setup command 6 COMMAND5: Display control setup command 7 COMMAND6: Synchronizing signal detection setup command 8 COMMAND7 to COMMAND12: Display control setup commands 9 COMMAND13 to COMMAND17: VPS/PDC commands

Display Control Command Table

Once written, the command identification code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74794/M locks into the display character data write mode, and another first byte cannot be written. When the CS1 pin is set high, the LC74794/M is set to the COMMAND0 (display memory write address setup mode) state.

First byte Second byte

Command

Command identification code

Data Data

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

COMMAND0 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 Write address setup

COMMAND1 1 0 0 1 0 0 0 0 at c6 c5 c4 c3 c2 c1 c0 Character write

COMMAND2 1 0 1 0 VS VS VS VS 0 FS VP VP VP VP VP VP Vertical character size and 21 20 11 10 5 4 3 2 1 0 vertical display start position

COMMAND3 1 0 1 1 HS HS HS HS 0 HP HP HP HP HP HP Horizontal character size and 21 20 11 10 5 4 3 2 1 0 horizontal display start position

COMMAND4 1 1 0 0 TST RAM OSC SYS 0 BLK BLK BLK BK BK RV DSP Display control MOD ERS STP RST 2 1 0 1 0 ON

COMMAND5 1 1 0 1 NP1 NP0 NON INT 0 0 HLF BCL CB PH PH PH Display control INT 2 1 0

COMMAND6 1 1 1 0 SEL MOD DIS MUT 0 RN RN RN SN SN SN SN Synchronizing signal detection 0 0 LIN 2 1 0 3 2 1 0

COMMAND7 1 1 1 1 0 0 0 0 0 CIN CIN VNP VSP MSK MSK EGL Display control SEL CTL SEL SEL ERS SEL

COMMAND8 1 1 1 1 0 0 0 1 0 LNA LNA LNA LNA LPA LPA LPA Display control 3 2 1 0 2 1 0

COMMAND9 1 1 1 1 0 0 1 0 0 LNB LNB LNB LNB LPB LPB LPB Display control 3 2 1 0 2 1 0

COMMAND10 1 1 1 1 0 0 1 1 0 LNC LNC LNC LNC LPC LPC LPC Display control 3 2 1 0 2 1 0

COMMAND11 1 1 1 1 0 1 0 0 0 0 0 0 LNC MOD LNB MOD Display control SEL 3 SEL 2

COMMAND12 1 1 1 1 0 1 0 1 0 0 0 0 0 SEL SEL CTL Display control 2 1 3

COMMAND13 1 1 1 1 0 1 1 0 0 CPA CPA 0 VPM VPM VPM VPM VPS/PDC control 1 0 3 2 1 0

COMMAND14 1 1 1 1 0 1 1 1 0 0 0 HBS HBS BMS EMS DCE VPS/PDC control 2 1

COMMAND15 1 1 1 1 1 0 0 0 0 0 ECV ECV ECV ECV ECV ECV VPS/PDC control 15 14 13 12 11 5

COMMAND16 1 1 1 1 1 0 0 1 0 ECP ECP ECP ECP ECP ECP ECP VPS/PDC control 19 18 17 16 15 14 13

COMMAND17 1 1 1 1 1 0 1 0 0 0 ECP ECP ECP ECP ECP ECP VPS/PDC control 25 24 23 22 21 20

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No. 5557-9/30

LC74794, 74794M

COMMAND0 (Display memory write address setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 0 4 — 0

3 V3

0 1

2 V2

0 1

1 V1

0 1

0 V0

0 1

Command 0 identification code Sets the display memory write address.

Display memory line address (0 to B hexadecimal)

COMMAND1 (Display character data write setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 0 4 — 1 3 — 0 2 — 0 1 — 0 0 — 0

Command 1 identification code Sets up display character data write mode.

When this command is input, the LC74794/M locks in the display character data write mode until the CS1 pin goes high.

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification code 6 — 0 5 — 0

4 H4

0 1

3 H3

0 1

2 H2

0 1

1 H1

0 1

0 H0

0 1

Display memory column address (0 to 17 hexadecimal)

Page 10

No. 5557-10/30

LC74794, 74794M

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 at

0 Character attribute off 1 Character attribute on

6 c6

0 1

5 c5

0 1

4 c4

0 1

3 c3

0 Character code (00 to 7F hexadecimal) 1

2 c2

0 1

1 c1

0 1

0 c0

0 1

Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 FS

0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc

VP5

(MSB) 1

4 VP4

0 1

3 VP3

0 1

2 VP2

0 1

1 VP1

0 1

VP0

(LSB) 1

COMMAND2 (Vertical display start position and vertical character size setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 1 4 — 0

3 VS21

0 1

Second line vertical character size

2 VS20

0 1

1 VS11

0 1

First line vertical character size

0 VS10

0 1

Command 2 identification code Sets the vertical display start position and the vertical character size

If VS is the vertical display start position then:

VS = H × (2 Σ 2nVPn)

n = 0

H: the horizontal synchronization pulse period

VS20

0 1

VS21

0 1H/dot 2H/dot 1 3H/dot 1H/dot

VS10

0 1

VS11

0 1H/dot 2H/dot 1 3H/dot 1H/dot

The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H.

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No. 5557-11/30

LC74794, 74794M

COMMAND3 (Horizontal display start position and horizontal size setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 1 4 — 1

3 HS21

0 1

Second line horizontal character size

2 HS20

0 1

1 HS11

0 1

First line horizontal character size

0 HS10

0 1

Command 3 identification code Sets the horizontal display start position and the horizontal character size.

HS20

0 1

HS21

0 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot

HS10

0 1

HS11

0 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0

HP5

(MSB) 1

4 HP4

0 1

3 HP3

0 1

2 HP2

0 1

1 HP1

0 1

HP0

(LSB) 1

If HS is the horizontal start position then:

HS = Tc × (2 Σ 2nHPn)

n = 0

Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating

mode.

The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc.

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LC74794, 74794M

COMMAND4 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 0 4 — 0

3 TSTMOD

0 Normal operating mode

This bit must be set to 0.

1 Test mode

2 RAMERS

0 1 Erase display RAM. (Set the RAM data to 7F hexadecimal.)

1 OSCSTP

0 Do not stop the crystal and LC oscillators. 1 Stop the crystal and LC oscillators.

0 SYSRST

0 1 Reset all registers and turn display off.

Command 4 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 BLK2

0 Character display area

Specifies the size for complete fill-in

1 Video display area

5 BLK1

0 1

Changes the blanking size

4 BLK0

0 1

3 BK1

0 Blinking period: About 0.5 s

Switches the blinking period

1 Blinking period: About 1.0 s

2 BK0

0 Blinking off 1 Blinking on

1 RV

0 Reverse video off 1 Reverse video on

0 DSPON

0 Character display off 1 Character display on

Blinking in reverse video mode switches the display between normal character display and reverse video display.

Erasing RAM takes about 500 µs. (This operation must be executed in the DSPOFF state.)

Valid in external synchronization mode when character display is off.

The registers are reset when the CS1 pin is low, and the reset state is cleared when CS1 is set high.

BLK0

0 1

BLK1

0 Blanking off Character size 1 Border size Complete fill in

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COMMAND5 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 0 4 — 1

3 NP1

0 1

Switches between NTSC and PAL.

2 NP0

0 1

( ) external input V

1 NON

1 Interlaced 0 Noninterlaced

0 INT

0 External synchronization 1 Internal synchronization

Command 5 identification code Display control setup

Switches between interlaced and noninterlaced video.

Switches between external and internal synchronization

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0

5 HLFINT

0 Normal mode 1 No background coloring (Only the background level is set)

4 BCL

0 Background coloring on

Only valid in internal synchronization mode.

1 No background coloring (Only the background level is set)

3 CB

0 Color burst signal output

Only valid when BCL is high.

1 Color burst signal output stopped

2 PH2

1 PH1

0 PH0

Background color specification

*: When 2 fsc is used.

PH2 PH1 PH0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

NP0

0 1

NPP1

0 NTSC (525) NTSC (625) 1 PAL (525) PAL (625)

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LC74794, 74794M

COMMAND6 (Synchronizing signal detection setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 0

3 SEL0

0 Sync separator signal

Switches the SEP

OUT

(pin 19) output.

1 Output signal set by MOD0

2 MOD0

0 High-level output

Only valid when SEL0 is high.

1 ST pulse signal

1 DISLIN

0 12 lines

Switches the number of lines displayed.

1 10 lines

0 MUT

0 Normal output

OUT

switching

1 CV

is cut and CV

OUT

is held at the pedestal level.

Command 6 identification code Sets up synchronizing signal control.

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 RN2

0 1

5 RN1

0 1

4 RN0

0 1

3 SN3

0 1

2 SN2

0 1

1 SN1

0 1

0 SN0

0 1

External synchronizing signal detection control Signal absent → signal present transition detection Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H).

External synchronizing signal detection control Signal present → signal absent transition detection Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H).

RN2 RN1 RN0 Number of times HSYNC detected

0 0 0 0 times 0 0 1 4 times 0 1 0 8 times 1 0 0 16 times

SN3 SN2 SN1 SN0 Number of times HSYNC detected

0 0 0 0 Not detected 0 0 0 1 32 times 0 0 1 0 64 times 0 1 0 0 128 times 1 0 0 0 256 times

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LC74794, 74794M

COMMAND7 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 0

Extended command 0 identification code

1 — 0 0 — 0

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 CINSEL

0 Blank area (the logical OR of the character and frame signals)

on signal switching

1 Video signal display area

5 CINCTL

0 CV

CR:

off

Turns CV

on or off.

1 CV

CR:

: on

4 VNPSEL

0 V falling edge detection 1 V rising edge detection

3 VSPSEL

0 VSEP: about 8.9 µs (NTSC)

Switches the internal V separation period.

1 VSEP: about 17.8 µs (NTSC)

2 MSKERS

0 Mask valid

Clears the HSYNC and VSYNK masks.

1 Mask invalid

1 MSKSEL

0 3H (NTSC)

Switches the VSYNC mask.

1 20H (NTSC)

0 EGL

0 Border level 0 only (VBK0) 1 Two-stage border level (VBK0 and VBK1)

Switches the V acquisition polarity in external mode when internal V separation is used.

Switches the border level. (Only valid when BLK0 is 0 and BLK1 is 1.)

Command 7 identification code Display control setup

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COMMAND8 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 0

Extended command 1 identification code

1 — 0 0 — 1

Command 7 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNA3

5 LNA2

4 LNA1

3 LNA0

2 LPA2

1 LPA1

0 LPA0

Specifies the line whose background is to be changed (Specifying the same line with LNA*, LNB*, and LNC* is not allowed.)

Specifies the background color.

LPA2 LPA1 LPA0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

LNA3 LNA2 LNA1 LNA0 Specified line

0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12

*: When 2 fsc is used.

Page 17

No. 5557-17/30

LC74794, 74794M

COMMAND9 (Display control setup command) First byte

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNB3

5 LNB2

4 LNB1

3 LNB0

2 LPB2

1 LPB1

0 LPB0

Specifies the line whose background is to be changed. (Specifying the same line with LNA*, LNB*, and LNC* is not allowed.)

Specifies the background color.

LPB2 LPB1 LPB0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

LNB3 LNB2 LNB1 LNB0 Specified line

*: When 2 fsc is used.

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 0

Extended command 2 identification code

1 — 1 0 — 0

Command 7 identification code Display control setup

Page 18

No. 5557-18/30

LC74794, 74794M

COMMAND10 (Display control setup command) First byte

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNC3

5 LNC2

4 LNC1

3 LNC0

2 LPC2

1 LPC1

0 LPC0

Specifies the line whose background is to be changed. (Specifying the same line with LNA*, LNB*, and LNC* is not allowed.)

Specifies the background color.

LPC2 LPC1 LPC0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

LNC3 LNC2 LNC1 LNC0 Specified line

*: When 2 fsc is used.

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 0

Extended command 3 identification code

1 — 1 0 — 1

Command 7 identification code Display control setup

Page 19

No. 5557-19/30

LC74794, 74794M

COMMAND11 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 1

Extended command 4 identification code

1 — 0 0 — 0

Command 7 identification code Display control setup

Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0 5 — 0 4 — 0

0 Normal line background color operation

3 LNCSEL

RV characters have the color of the PH* specified background color and RV characters have a white background.

0 The specifications when LNCSEL is set to 1.

2 MOD3

RV characters have the background color specified by PH* and the RV characters themselves are white.

0 Normal line background color operation

1 LNBSEL

RV characters have the color of the PH* specified background color and RV characters have a white background.

0 The specifications when LNBSEL is set to 1.

0 MOD2

RV characters have the background color specified by PH* and the RV characters themselves are white.

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Switches the background color in RV mode for RV specified characters on LNB* specified lines.

Valid when LNCSEL is high.

Switches the background color in RV mode for RV specified characters on LNB* specified lines.

Valid when LNBSEL is high.

Page 20

No. 5557-20/30

LC74794, 74794M

COMMAND12 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 1

Extended command 5 identification code

1 — 0 0 — 1

Command 7 identification code Display control setup

Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0 5 — 0 4 — 0 3 — 0

2 SEL2

0 External synchronizing signal judgment output signal

SYNC

JDG

(pin 8) output switching

1 O/E signal

1 SEL1

0 Internal slice data

Signal input from SEP

(pin 27) when set to 1

1 External slice data

0 CTL3

0 Use internal V separation.

V separation switching

1 Do not use internal V separation.

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Page 21

No. 5557-21/30

LC74794, 74794M

COMMAND13 (VPS/PDC control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 1

Extended command 6 identification code

1 — 1 0 — 0

Command 7 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 CPA1

5 CPA0

4 — 0

3 VPM3

2 VPM2

1 VPM1

0 VPM0

Data acquisition clock switching

CPA1 CPA0 Clock

0 0 No.1 0 1 No.2 1 0 No.3 1 1 No.4

VPM3 VPM2 VPM1 VPM0 Operating mode

0 0 0 0 VPS 0 0 0 1 8/30/2 (PDC) 0 0 1 0 Automatic PDC and VPS switching 0 0 1 1 8/30/1 (UDT) 0 1 0 0 Header time 1 0 1 0 1 Header time 2 0 1 1 0 Header time 3 0 1 1 1 Header time 4 1 0 0 0 Status display 1 1 0 0 1 Status display 2 1 0 1 0 Status display 3 1 0 1 1 Status display 4

Page 22

No. 5557-22/30

LC74794, 74794M

COMMAND14 (VPS/PDC control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0 2 — 1

Extended command 7 identification code

1 — 1 0 — 1

Command 7 identification code Display control setup

Second byte

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0 5 — 0

4 HBS2

0 Discrimination mode 1

Clock line

1 Discrimination mode 2

3 HBS1

0 Discrimination mode 1

Framing code

1 Discrimination mode 2 0

Error checking enabled (Error checking can be turned on or off on a per-byte

2 BMS

basis.)

Error checking disabled (Applications can select whether to hold or write data with errors on a per-byte basis.)

1 EMS

0 Data hold 1 Data write (In VPS mode, the error bit is set to 0.)

Error checking turned on for data unused bytes.

VPS: bytes 3, 4, and 6 to 10. PDCC (8/30/2): bytes 7 to 12. Header 1: bytes 14 to 37. Header 2: bytes 14 to 29, Header 3: bytes 14 to 21. Status 1 (3):

0 DCE

bytes 7 to 25. Status 2 (4): bytes 7 to 35. Error checking turned off for data unused bytes.

VPS: bytes 3, 4, and 6 to 10. PDCC (8/30/2): bytes 7 to 12. Header 1: bytes 14 to 37. Header 2: bytes 14 to 29, Header 3: bytes 14 to 21. Status 1 (3): bytes 7 to 25. Status 2 (4): bytes 7 to 35.

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

When 0, bytes for which error checking is specified and that have no errors are written to P-S. When 1, all bytes are written to P-S regardless of errors.

The handling of bytes for which error checking is turned off when error checking is enabled.

Error checking specification for bytes whose data is unused. Bi-phase (VPS), Hamming (PDC), or odd parity (header)

Page 23

No. 5557-23/30

LC74794, 74794M

COMMAND15 (VPS/PDC control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 1 2 — 0

Extended command 8 identification code

1 — 0 0 — 0

Command 7 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0

5 ECV15

0 Byte 15 bi-phase error check on (data held) 1 Byte 15 bi-phase error check off (data written)

4 ECV14

0 Byte 14 bi-phase error check on (data held) 1 Byte 14 bi-phase error check off (data written)

3 ECV13

0 Byte 13 bi-phase error check on (data held) 1 Byte 13 bi-phase error check off (data written)

2 ECV12

0 Byte 12 bi-phase error check on (data held) 1 Byte 12 bi-phase error check off (data written)

1 ECV11

0 Byte 11 bi-phase error check on (data held) 1 Byte 11 bi-phase error check off (data written)

0 ECV5

0 Byte 5 bi-phase error check on (data held) 1 Byte 5 bi-phase error check off (data written)

Settings when the VPS data BMS = 0. Settings in parentheses apply when BMS = 1.

Page 24

No. 5557-24/30

LC74794, 74794M

COMMAND16 (VPS/PDC control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 1 2 — 0

Extended command 9 identification code

1 — 0 0 — 1

Command 7 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

Byte 19 Hamming error check on (data held)

6 ECP19

{Byte 44, 28, 36, 20, 32, 42, 32, and 42}

Byte 19 Hamming error check off (data written) {Byte 44, 28, 36, 20, 32, 42, 32, and 42}

Byte 18 Hamming error check on (data held)

5 ECP18

{Byte 43, 27, 35, 19, 31, 41, 31, and 41}

Byte 18 Hamming error check off (data written) {Byte 43, 27, 35, 19, 31, 41, 31, and 41}

Byte 17 Hamming error check on (data held)

4 ECP17

{Byte 42, 26, 34, 18, 30, 40, 30, and 40}

Byte 17 Hamming error check off (data written) {Byte 42, 26, 34, 18, 30, 40, 30, and 40}

Byte 16 Hamming error check on (data held)

3 ECP16

{Byte 41, 25, 33, 17, 29, 39, 29, and 39}

Byte 16 Hamming error check off (data written) {Byte 41, 25, 33, 17, 29, 39, 29, and 39}

Byte 15 Hamming error check on (data held)

2 ECP15

{Byte 40, 24, 32, 16, 28, 38, 28, and 38}

Byte 15 Hamming error check off (data written) {Byte 40, 24, 32, 16, 28, 38, 28, and 38}

Byte 14 Hamming error check on (data held)

1 ECP14

{Byte 39, 23, 31, 15, 27, 37, 27, and 37}

Byte 14 Hamming error check off (data written) {Byte 39, 23, 31, 15, 27, 37, 27, and 37}

Byte 13 Hamming error check on (data held)

0 ECP13

{Byte 38, 22, 30, 14, 26, 36, 26, and 36}

Byte 13 Hamming error check off (data written) {Byte 38, 22, 30, 14, 26, 36, 26, and 36}

Settings when the PDC data (8/30/2) BMS = 0. Settings in parentheses apply when BMS = 1. The items in curly brackets are the bytes for which the odd parity check is turned on and off in header modes 1, 2, 3, and 4 and status modes 1, 2, 3, and 4, respectively.

Page 25

No. 5557-25/30

LC74794, 74794M

COMMAND17 (VPS/PDC control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 1 2 — 0

Extended command A identification code

1 — 1 0 — 0

Command 7 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0

0 Byte 25 Hamming error check on (data held)

5 ECP25

1 Byte 25 Hamming error check off (data written)

0 Byte 24 Hamming error check on (data held)

4 ECP24

1 Byte 24 Hamming error check off (data written)

0 Byte 23 Hamming error check on (data held)

3 ECP23

1 Byte 23 Hamming error check off (data written)

Byte 22 Hamming error check on (data held)

2 ECP22

{Byte ,,, 35, 45, 35, and 45}

Byte 22 Hamming error check off (data written) {Byte ,,, 35, 45, 35, and 45}

Byte 21 Hamming error check on (data held)

1 ECP21

{Byte ,,, 34, 44, 34, and 44}

Byte 21 Hamming error check off (data written) {Byte ,,, 34, 44, 34, and 44}

Byte 20 Hamming error check on (data held)

0 ECP20

{Byte 45, 29, 37, 21, 33, 43, 33, and 43}

Byte 20 Hamming error check off (data written) {Byte 45, 29, 37, 21, 33, 43, 33, and 43}

Settings when the PDC data (8/30/2) BMS = 0. Settings in parentheses apply when BMS = 1. The items in curly brackets are the bytes for which the odd parity check is turned off in header modes 1, 2, 3, and 4 and status modes 1, 2, 3, and 4, respectively.

Page 26

PDC/VPS Output Data Formats

Data is read out in order starting with bytes 1 and 7

No. 5557-26/30

LC74794, 74794M

Output data

PDC 8/30 mode

VPS mode Header time mode 1 (3) Header time mode 2 (4)

Format1 Format2

Data update bits *: The value is 0 when data is updated and 1 when not updated.

Byte 1 Bit 7 byte 15 bit 0 byte 16 bit 0 byte 11 bit 0 byte 38 bit 0 byte 22 bit 0

6 1 1 1 (30) 1 (14) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte 17 bit 0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7

Byte 2 Bit 7 byte 16 bit 0 byte 18 bit 0 byte 12 bit 0 byte 39 bit 0 byte 23 bit 0

6 1 1 1 (31) 1 (15) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte 19 bit 0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7

Byte 3 Bit 7 byte 17 bit 0 byte 20 bit 0 byte 13 bit 0 byte 40 bit 0 byte 24 bit 0

6 1 1 1 (32) 1 (16) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte 21 bit 0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7

Byte 4 Bit 7 byte 18 bit 0 byte 22 bit 0 byte 14 bit 0 byte 41 bit 0 byte 25 bit 0

6 1 1 1 (33) 1 (17) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte 23 bit 0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7

Byte 5 Bit 7 byte 19 bit 0 byte 14 bit 0 byte 5 bit 0 byte 42 bit 0 byte 26 bit 0

6 1 1 1 (34) 1 (18) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte 15 bit 0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7

Byte 6 Bit 7 byte 20 bit 0 byte 24 bit 0 byte 15 bit 0 byte 43 bit 0 byte 27 bit 0

6 1 1 1 (35) 1 (19) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte 25 bit 0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7

Continued on next page.

Page 27

No. 5557-27/30

LC74794, 74794M

Output data

PDC 8/30 mode

VPS mode Header time mode 1 (3) Header time mode 2 (4)

Format1 Format2

Byte 7 Bit 7 byte 21 bit 0 byte 13 bit 0 1 byte 44 bit 0 byte 28 bit 0

6 1 1 1 (36) 1 (20) 1 5 2 2 1 2 2 4 3 3 1 3 3 3 4 1 1 4 4 2 5 1 1 5 5 1 6 1 1 6 6 0 7 1 0 7 7

Byte 8 Bit 7 byte 13 bit 0 Error byte 16 Error byte 11 byte 45 bit 0 byte 29 bit 0

6 1 information 1 17 information 1 12 (37) 1 (21) 1 5 2 18 13 2 2 4 3 19 14 3 3 3 4 20 5 4 4 2 5 21 15 5 5 1 6 22 0 6 6 0 7 23 0 7 7

Byte 9 Bit 7 byte 14 bit 0 Error byte 14 Error byte 38 (30) Error byte 22 (14)

6 1 information 2 15 information 39 (31) information 23 (15) 5 2 24 40 (32) 24 (16) 4 3 25 41 (33) 25 (17) 3 4 13 42 (34) 26 (18) 2 5 0 43 (35) 27 (19) 1 6 0 44 (36) 28 (20) 0 7 0 45 (37) 29 (21)

Byte 10 Bit 7 byte 22 bit 0

6 1 5 2 4 3 3 4 2 5 1 6 0 7

Byte 11 Bit 7 byte 23 bit 0

6 1 5 2 4 3 3 4 2 5 1 6 0 7

Byte 12 Bit 7 byte 24 bit 0

6 1 5 2 4 3 3 4 2 5 1 6 0 7

Byte 13 Bit 7 byte 25 bit 0

6 1 5 2 4 3 3 4 2 5 1 6 0 7

Continued from preceding page.

Bits for which there is no data setting are 1.

Page 28

No. 5557-28/30

LC74794, 74794M

Data is read out in order starting with bytes 1 and 7 1, 2 : 8/30/2 3, 4 : 8/30/1

Output data

Status display Status display

mode 1 (3) mode 2 (4)

Data update bits *: The value is 0 when data is updated.

Byte 1 Bit 7 byte 26 bit 0 byte 36 bit 0

6 (26) 1 (36) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 2 Bit 7 byte 27 bit 0 byte 37 bit 0

6 (27) 1 (37) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 3 Bit 7 byte 28 bit 0 byte 38 bit 0

6 (28) 1 (38) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 4 Bit 7 byte 29 bit 0 byte 39 bit 0

6 (29) 1 (39) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 5 Bit 7 byte 30 bit 0 byte 40 bit 0

6 (30) 1 (40) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 6 Bit 7 byte 31 bit 0 byte 41 bit 0

6 (31) 1 (41) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 7 Bit 7 byte 32 bit 0 byte 42 bit 0

6 (32) 1 (42) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Output data

Status display Status display

mode 1 (3) mode 2 (4)

Byte 8 Bit 7 byte 33 bit 0 byte 43 bit 0

6 (33) 1 (43) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 9 Bit 7 byte 34 bit 0 byte 44 bit 0

6 (34) 1 (44) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 10 Bit 7 byte 35 bit 0 byte 45 bit 0

6 (35) 1 (45) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7

Byte 11 Bit 7 Error byte 26 (26) Error byte 36 (36)

6 information 1 27 (27) information 1 37 (37) 5 28 (28) 38 (38) 4 29 (29) 39 (39) 3 30 (30) 40 (40) 2 31 (31) 41 (41) 1 32 (32) 42 (42) 0 33 (33) 43 (43)

Byte 12 Bit 7 Error byte 34 (34) Error byte 44 (44)

6 information 2 35 (35) information 2 45 (45) 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 0 0

Byte 13 Bit 7

6 5 4 3 2 1 0

Bits for which there is no data setting are 1.

Page 29

No. 5557-29/30

LC74794, 74794M

Display Screen Structure

The display consists of 12 lines of 24 characters each. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced from the normal total of 288 when enlarged characters are displayed. Display memory addresses are specified as row (0 to b hexadecimal) and column (0 to 17 hexadecimal) addresses.

Display Screen Structure (display memory addresses) 24 characters × 12 rows

Page 30

No. 5557-30/30

LC74794, 74794M

This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:

➀

Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:

➁

Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

Composite Video Signal Output Levels (internally generated levels)

OUT

output level waveform (VDD2 = 5.0 V)

Output level Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V]

CHA

: Character 2.65 2.85 3.15

RSH

: Background color high 2.37 (2.01) 2.57 (2.21) 2.87 (2.51)

CBH

: Color burst high 1.67 1.87 2.17

RSL

: Background color low 1.23 (1.16) 1.43 (1.36) 1.73 (1.66)

1: Border 2.08 2.28 2.58

0: Border 1.50 1.70 2.00

: Pedestal 1.37 1.57 1.87

CBL

: Color burst low 1.07 1.27 1.57

: Sync 0.80 1.00 1.30

Note: VDD2 = 5.0 V. Values in parentheses for V

RSH

and V

RSL

apply when the background color is blue.

Datasheet LC74794M, LC74794 Datasheet (SANYO)

Specifications and Main Features

Frequently Asked Questions

User Manual