Datasheet LC74785M, LC74785 Datasheet (SANYO)

Page 1

Overview

The LC74785 and LC74785M are on-chip EDS CMOS LSIs for on-screen display, a function that displays characters and patterns on a TV screen under microprocessor control. These LSIs support 12 × 18 dot characters and can display 12 lines by 24 characters of text.

Features

• Display format: 24 characters by 12 rows (Up to 288 characters)

• Character format: 12 (horizontal) × 18 (vertical) dots

• Character sizes: Three sizes each in the horizontal and vertical directions

• Characters in font: 128

• Initial display positions: 64 horizontal positions and 64 vertical positions

• Blinking: Specifiable in character units

• Blinking types: Two periods supported: About 1.0 second and about 0.5 second

• Blanking: Over the whole font (12 × 18 dots)

• Background color — Background coloring: 8 colors (internal synchronization

mode): 4fsc

— Background coloring: 6 colors (internal synchronization

mode): 2fsc

• Line background color — Can be set for 3 lines — Line background coloring: 8 colors (internal synchro-

nization mode): 4fsc

— Line background coloring: 6 colors (internal synchro-

nization mode): 2fsc

• External control input: 8-bit serial input format

• On-chip sync separator circuit

• EDS support

• Video output — NTSC-format composite output

• Package 24-pin plastic DIP (300 mil) 24-pin plastic SOP (375 mil)

Package Dimensions

unit: mm

3067-DIP24S

unit: mm

3045B-MFP24

CMOS LSI

Ordering number : EN5520A

63097HA (OT) No. 5520-1/24

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

On-Screen Display Controller LSI

LC74785, LC74785M

SANYO: DIP24S

[LC74785]

SANYO: MFP24

[LC74785M]

Page 2

Pin Assignment

Pin Functions

No. 5520-2/24

LC74785, LC74785M

Pin No. Pin Function Notes

1 V

1 Ground Ground connection (digital system ground)

2 Xtal

Xtal

OUT

(MUTE)

CTRL1

(CHABLK)

5 LN21 Data output 6 OSC

LC oscillator

7 OSC

OUT

8 SYNC

JDG

Enable input pin for the OSD serial data input function.

9 CS1 Enable input Serial data input is enabled when this pin is low.

A pull-up resistor is built in. (The input has hysteresis characteristics.)

10 SCLK Clock input

Input for the serial data input clock. A pull-up resistor is built in. (The input has hysteresis characteristics.)

11 SIN Data input

Serial data input. A pull-up resistor is built in. (The input has hysteresis characteristics.)

12 V

2 Power supply

Composite video signal level adjustment power supply (analog system power supply)

13 CV

OUT

Video signal output Composite video signal output

14 V

2 Ground Ground connection (analog system ground)

Crystal oscillator

(MUTE input)

Crystal oscillator input switching

(CHABLK output)

External synchronizing signal judgment output

These pins are used either to connect the crystal and capacitor used to form an external crystal oscillator used to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the Xtalout pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)

Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character border) output. This is a 3-value output.

Connections for the coil and capacitor that form the character output dot clock generation oscillator.

Line 21H pulse output (Even fields when MOD1 is low, both fields when MOD1 is high)

Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs a field discrimination pulse (O/E pulse) when SEL2 is high.(HLFTON: Valid when 0) HLFTON: A signal in the range specified by LNA*, LNB*, and LNC* is output when HLFTON is high.) Outputs the dot clock (LC oscillator) when CS1 is high and RST is low. (This signal is not output on command resets.) Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not output on command resets.)

Continued on next page.

Page 3

No. 5520-3/24

LC74785, LC74785M

Pin No. Pin Function Notes

15 CV

Video signal input Composite video signal input

16 V

1 Power supply Power supply (+5 V: digital system power supply)

17 SYN

Sync separator circuit input Video signal input for the built-in sync separator circuit

18 CDLR Background color phase adjustment Background color phase adjustment. Connect to ground through a resistor and a capacitor.

19 SEP

OUT

Composite synchronizing signal output

20 SEP

21 CS2 Enable input

22 CPDT Data output

23 RST Reset input 24 V

1 Power supply (+5 V) Power supply (+5 V: digital system power supply)

Video signal output for the built-in sync separator circuit. Can be switched to function as an output for signal (high or ST. pulse) due to MOD0 by setting SEL0 high.

Inputs the vertical synchronizing signal created by integrating the SEP

OUT

pin output signal. An integration circuit must be connected to the SEP

OUT

pin. This pin must be tied to

1 if unused. This pin can be switched to function as the frame signal input mode

by setting SEL1 high. (This is valid when CTL3 is set to 1.)

Vertical synchronizing signal input

EDS data output enable input. EDS data output is enabled when this pin is low. A pull-up resistor is built in. (The input has hysteresis characteristics.)

EDS data output (This pin can be either an n-channel open-drain output or a CMOS output.)

System reset input A pull-up resistor is built in. (The input has hysteresis characteristics.)

Continued from preceding page.

Note: Both VDD1 pins must be connected to the power supply.

Note: When the Xtal

pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.

Parameter Symbol Conditions Ratings Unit

Supply voltage V

VDD1 and VDD2 VSS–0.3 to VSS+7.0 V

Input voltage V

All input pins VSS–0.3 to VDD+0.3 V

Output voltage V

OUT

LN21, CPDT, SEP

OUT

, and SYNC

JDG

VSS–0.3 to VDD+0.3 V Allowable power dissipation Pd max Ta = 25°C 350 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

1 VDD1 4.5 5.0 5.5 V

2 VDD2 4.5 5.0 1.27VDD1 V

RST, CS1, CS2, SIN, SCLK, SEP

0.8V

1 VDD1 + 0.3 V

Input high-level voltage

and MUTE

2 CTRL1 0.7VDD1 VDD1 + 0.3 V

RST, CS1, CS2, SIN, SCLK, SEP

– 0.3 0.2VDD1 V

Input low-level voltage

and MUTE

2 CTRL1 VSS– 0.3 0.3VDD1 V

Pull-up resistance R

Applies to pins set for the RST, CS1, CS2,

25 50 90 kΩ

SIN, SCLK, and MUTE pin options.

Composite video signal input voltage

1 CVIN; VDD1 = 5 V 2.0 Vp-p

2 SYNIN; VDD1 = 5 V 1.5 2.0 2.5 Vp-p

Input voltage V

Xtal

(When external clock input is used)

0.10 5.0 Vp-p

= 2 fsc or 4 fsc ; VDD1 = 5 V

OSC

The Xtal

and Xtal

OUT

oscillator pins

7.159 MHz

(2 fsc: NTSC)

Oscillator frequency

OSC

The Xtal

and Xtal

OUT

oscillator pins

14.318 MHz

(4 fsc: NTSC)

OSC

The OSC

and OSC

OUT

oscillator pins

5 10 MHz

(LC oscillator)

Allowable Operating Ranges at Ta = –30 to +70°C

Page 4

No. 5520-4/24

LC74785, LC74785M

Parameter Symbol Conditions

Ratings

Unit

min typ max

Input off leakage current I

leak

1 CV

1 µA

Output off leakage current I

leak

2 CV

OUT

1 µA

Output high-level voltage V

LN21, SYNC

JDG

, CPDT, and SEP

OUT

;

3.5 V

1 = 4.5 V, IOH= –1.0 mA

Output low-level voltage V

LN21, SYNC

JDG

, CPDT, and SEP

OUT

;

1.0 V

1 = 4.5 V, IOL= 1.0 mA

CHABLK; V

1 = 5.0 V H 3.3 5.0 V

Three-value output voltage V

M 1.8 2.3 V L 0 0.8 V

Input current

RST, CS1, CS2, SIN, SCLK, CTRL1,

1 µA

SEP

, and MUTE; VIN= VDD1

CTRL1 and OSCIN; VIN= VSS1 –1 µA

Operating mode current drain

1; All outputs open, Xtal: 7.159 MHz,

30 mA

LC: 8 MHz

2 VDD2: VDD2 = 5 V 20 mA

0.70 0.82 0.94 V

SYNC level V

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

0.89 1.01 1.13 V

1.18 1.30 1.42 V

1.32 1.44 1.56 V

Pedestal level V

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

1.52 1.64 1.76 V

1.81 1.93 2.05 V

0.98 1.10 1.22 V

Color burst low level V

CBL

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

1.17 1.29 1.41 V

1.46 1.58 1.70 V

1.63 1.75 1.87 V

Color burst high level V

CBH

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

1.83 1.95 2.07 V

2.11 2.23 2.35 V

1.17 1.29 1.41 V

Background color other than blue low level V

RSL

0 CV

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

1.36 1.48 1.60 V

1.65 1.77 1.89 V

2.33 2.45 2.57 V

Background color other than blue high level V

RSH

0 CV

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

2.52 2.64 2.76 V

2.81 2.93 3.05 V

1.08 1.20 1.32 V

Blue background color 1low level V

RSL

1 CV

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

1.27 1.39 1.51 V

1.56 1.68 1.80 V

1.49 1.61 1.83 V

Blue background color 2 low level V

RSL

2 CV

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

1.68 1.80 1.92 V

1.97 2.09 2.21 V

RSH

1.97 2.09 2.21 V

Blue background color 1, 2 high level CV

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

2.17 2.29 2.41 V

RSH

2.46 2.58 2.70 V

1.40 1.52 1.64 V

Frame level 0 V

0 CV

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

1.60 1.72 1.84 V

1.89 2.01 2.13 V

1.97 2.09 2.21 V

Frame level 1 V

1 CV

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

2.17 2.29 2.41 V

2.46 2.58 2.70 V

2.55 2.67 2.79 V

Character level V

CHA

OUT

; VDD1 = 5.0 V, VDD2 = 5.0 V *

2.75 2.87 2.99 V

3.04 3.16 3.28 V

Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.

Note: 1. When the sync level is 0.8 V

2. When the sync level is 1.0 V

3. When the sync level is 1.3 V

Page 5

No. 5520-5/24

LC74785, LC74785M

Parameter Symbol Conditions

Ratings

Unit

min typ max

Minimum input pulse width

W(SCLK)

SCLK 200 ns

W(CS1)

CS1 (The period when CS1 is high) 1 µs

Data setup time

SU(CS1)

CS1 200 ns

SU(SIN)

SIN 200 ns

Data hold time

h(CS1)

CS1 2 µs

h(SIN)

SIN 200 ns

One word write time

word

The time to write 8 bits of data 4.2 µs

The RAM data write time 1 µs

Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V

OSD write (See Figure 1.)

Parameter Symbol Conditions

Ratings

Unit

min typ max

CKCY

SCLK 2 µs

Minimum input pulse width t

CKL

SCLK 1 µs

CKH

SCLK 1 µs

Setup time t

ICK

SCLK 10 µs

Output delay time t

CKO

CPDT 0.5 µs

EDS read (For the n-channel open-drain circuit, see Figure 2.)

Figure 1 OSD Serial Data Input Timing

Figure 2 EDS Serial Output Test Conditions (For the n-channel open-drain circuit.)

Note: The CMOS output circuit follows the OSD timing.

First byte

Note: CPDT goes to the high-impedance state when CS2 is high.

Second byte

Page 6

Figure 3 O/E and LN21 Output Timing

No. 5520-6/24

LC74785, LC74785M

Note: The O/E signal is output from the SYNC

JDG

pin when SEL2 is high.

LN21 is output for even fields when MOD1 is low and for both fields when MOD1 is high.

(Line number)

Odd field

Pulse output when MOD1 is high

Pulse output when MOD1 is low or high

Even field

(Line number)

Page 7

No. 5520-7/24

LC74785, LC74785M

Figure 4 Transferring caption data from the LC74785/M to the decoder LSI (microcontroller): Method 1

(Basic LC74785/M usage)

Note: When extracting closed caption character data when MOD1 is high (NTSC-TV), applications must determine whether the current field is odd or

even by checking the signal level output from the SYNC

JDG

pin (with SEL2 set high) when a falling edge is detected on LN21.

A pulse is output at line 21 in even fields when MOD1 is low.

A pulse is output at line 21 in both fields when MOD1 is High.

Caption data is transferred to the data output buffer.

High-impedance

The previous data is output.

The 16 bits of caption data is output LSB first

in synchronization with SCLK falling edges.

CS2 is switched from high to low after the decoder LSI (microcontroller) detects a falling edge on LN21.

Page 8

No. 5520-8/24

LC74785, LC74785M

The timing of the transfer of caption data to the data output buffer is synchronized with the falling edge of the pulse output from LN21. Therefore, the software processing shown below is required if the decoder LSI (microcontroller) does not detect LN21 falling edges.

Since data is output to the output buffer once (during the even field) when MOD1 is low, the data transfer control operation from the decoder LSI (microcontroller) must be performed at least twice in a single frame (about 32 ms).

If a transfer control operation is performed twice in the same frame, the CPDT output on the second operation will be 16 bits of zero data. This allows the decoder LSI to determine that the data for the next frame has not been transferred yet.

Note: If CS2 remains low, the hardware will not be able to transfer the data to the output buffer. Therefore, the decoder LSI (microcontroller) must reset CS2

to high from low after it completes a data transfer control operation.

Transfer method 2 cannot be used if MOD1 is high (NTSC-TV).

Transfer of 16 data bits

Activity within a given frame (MOD1: low)

Data in which all

16 bits are zero

Figure 5 Transferring caption data from the LC74785/M to the decoder LSI (microcontroller): Method 2

(When it is not possible to allocate a port on the decoder LSI (microcontroller) to detect

falling edges on LN21.)

Page 9

System Block Diagram

No. 5520-9/24

LC74785, LC74785M

Data output

buffer

Data peak hold

(data slice)

HSYNC peak hold

(HSYNC slice)

Synchroniza-

tion

determination

Character

output dot

clock

generator

Composite

sync signal

separation

control

Timing generator

Synchronizing

signal generator

Shift register

Font ROM

Decoder

Character output control

Background control

Video output control

Pedestal clamp

Output control

Data slicer

Serial to

parallel

converter

8-bit latch

command

decode

Horizontal

character

size register

Vertical

character

size register

Horizontal

display

position

detector

Vertical

display

position

Blinking and

reverse video

control

Display

control

Decoder

RAM write

address

counter

Display RAM

Horizontal

size counter

Vertical size

counter

Horizontal dot

counter

Vertical dot

counter

Vertical

display

position

detector

Horizontal

display

position

detector

Character

control

counter

Line control

counter

Blinking and

reverse video

control circuit

Page 10

Display Control Commands

Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported.

1 COMMAND0: Display memory (VRAM) write address setup command 2 COMMAND1: Display character data write command 3 COMMAND2: Vertical display start position and vertical character size setup command 4 COMMAND3: Horizontal display start position and horizontal character size setup command 5 COMMAND4: Display control setup command 6 COMMAND5: Display control setup command 7 COMMAND6: Synchronizing signal detection setup command 8 COMMAND7: Display control setup command 9 COMMAND8: Display control setup command 10COMMAND9: Display control setup command 11COMMAND10: Display control setup command

Display Control Command Table

Once written, the command identification code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74785/M locks into the display character data write mode, and another first byte cannot be written.

When the CS1 pin is set high, the LC74785/M is set to the COMMAND0 (display memory write address setup mode) state.

No. 5520-10/24

LC74785, LC74785M

First byte Second byte

Command

Command identification code

Data Data

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

COMMAND0 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 Write address setup

COMMAND1 1 0 0 1 0 0 0 0 at c6 c5 c4 c3 c2 c1 c0 Character write

COMMAND2 1 0 1 0 VS VS VS VS 0 FS VP VP VP VP VP VP Vertical character size and 21 20 11 10 5 4 3 2 1 0 vertical display start position

COMMAND3 1 0 1 1 HS HS HS HS 0 LC HP HP HP HP HP HP Horizontal character size and 21 20 11 10 5 4 3 2 1 0 horizontal display start position

COMMAND4 1 1 0 0 TST RAM OSC SYS 0 BLK BLK BLK BK BK RV DSP Display control MOD ERS STP RST 2 1 0 1 0 ON

COMMAND5 1 1 0 1 0 HLF NON INT 0 0 0 BCL CB PH PH PH Display control TON 2 1 0

COMMAND6 1 1 1 0 SEL MOD DIS MUT 0 RN RN RN SN SN SN SN Synchronizing signal detection 0 0 LIN 2 1 0 3 2 1 0

COMMAND7 1 1 1 1 0 0 SEL CTL 0 0 0 VNP VSP MSK MSK EGL Display control 1 3 SEL SEL ERS SEL

COMMAND8 1 1 1 1 0 1 SEL MOD 0 LNA LNA LNA LNA LPA LPA LPA Display control 2 1 3 2 1 0 2 1 0

COMMAND9 1 1 1 1 1 0 LNB MOD 0 LNB LNB LNB LNB LPB LPB LPB Display control SEL 2 3 2 1 0 2 1 0

COMMAND10 1 1 1 1 1 1 LNC MOD 0 LNC LNC LNC LNC LPC LPC LPC Display control SEL 3 3 2 1 0 2 1 0

Page 11

COMMAND0 (Display memory write address setup command) First byte

No. 5520-11/24

LC74785, LC74785M

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 0 4 — 0

3 V3

0 1

2 V2

0 1

1 V1

0 1

0 V0

0 1

Command 0 identification code Sets the display memory write address.

Display memory line address (0 to B hexadecimal)

COMMAND1 (Display character data write setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 0 4 — 1 3 — 0 2 — 0 1 — 0 0 — 0

Command 1 identification code Sets up display character data write mode.

When this command is input, the LC74785/M locks in the display character data write mode until the CS1 pin goes high.

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification code 6 — 0 5 — 0

4 H4

0 1

3 H3

0 1

2 H2

0 1

1 H1

0 1

0 H0

0 1

Display memory column address (0 to 17 hexadecimal)

Page 12

No. 5520-12/24

LC74785, LC74785M

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 at

0 Character attribute off 1 Character attribute on

6 c6

0 1

5 c5

0 1

4 c4

0 1

3 c3

0 Character code (00 to 7F hexadecimal) 1

2 c2

0 1

1 c1

0 1

0 c0

0 1

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 FS

0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc

VP5

(MSB) 1

4 VP4

0 1

3 VP3

0 1

2 VP2

0 1

1 VP1

0 1

VP0

(LSB) 1

COMMAND2 Vertical display start position and vertical character size setup command First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 1 4 — 0

3 VS21

0 1

Second line vertical character size

2 VS20

0 1

1 VS11

0 1

First line vertical character size

0 VS10

0 1

Command 2 identification code Sets the vertical display start position and the vertical character size

If VS is the vertical display start position then:

VS = H × (2 Σ 2

VPn)

n = 0

H: the horizontal synchronization pulse period

VS20

0 1

VS21

0 1H/dot 2H/dot 1 3H/dot 1H/dot

VS10

0 1

VS11

0 1H/dot 2H/dot 1 3H/dot 1H/dot

The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H.

Character display

area

Page 13

No. 5520-13/24

LC74785, LC74785M

COMMAND3 (Horizontal display start position and horizontal size setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 0 5 — 1 4 — 1

3 HS21

0 1

Second line horizontal character size

2 HS20

0 1

1 HS11

0 1

First line horizontal character size

0 HS10

0 1

Command 3 identification code Sets the horizontal display start position and the horizontal character size.

HS20

0 1

HS21

0 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot

HS10

0 1

HS11

0 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 LC

0 Use the LC oscillator for the dot clock 1 Use the crystal oscillator for the dot clock

HP5

(MSB) 1

4 HP4

0 1

3 HP3

0 1

2 HP2

0 1

1 HP1

0 1

HP0

(LSB) 1

If HS is the horizontal start position then:

HS = Tc × (2 Σ 2nHPn)

n = 0

Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating

mode.

The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc.

Selects the dot clock used for character display in the horizontal direction.

Page 14

No. 5520-14/24

LC74785, LC74785M

COMMAND4 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 0 4 — 0

3 TSTMOD

0 Normal operating mode

This bit must be set to 0.

1 Test mode

2 RAMERS

0 1 Erase display RAM. (Set the RAM data to 7F hexadecimal.)

1 OSCSTP

0 Do not stop the crystal and LC oscillators. 1 Stop the crystal and LC oscillators.

0 SYSRST

0 1 Reset all registers and turn display off.

Command 4 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 BLK2

0 Character display area

Specifies the size for complete fill in

1 Video display area

5 BLK1

0 1

Changes the blanking size

4 BLK0

0 1

3 BK1

0 Blinking period: About 0.5 s

Switches the blinking period

1 Blinking period: About 1.0 s

2 BK0

0 Blinking off 1 Blinking on

1 RV

0 Reverse (character reversing) off 1 Reverse (character reversing) on

0 DSPON

0 Character display off 1 Character display on

Blinking in reverse video mode switches the display between normal character display and reverse video display.

Erasing RAM takes about 500 µs. (This operation must be executed in the DSPOFF state.)

Valid in external synchronization mode when character display is off.

The registers are reset when the CS1 pin is low, and the reset state is cleared when CS1 is set high,

BLK0

0 1

BLK1

0 Blanking off Character size 1 Border size Full character size

Page 15

No. 5520-15/24

LC74785, LC74785M

COMMAND5 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 0 4 — 1 3 — 0

2 HLFTON

0 External synchronizing signal judgment output signal 1 A signal in the range specified by LNA*, LNB*, and LNC* is output.

1 NON

0 Interlaced 1 Noninterlaced

0 INT

0 External synchronization 1 Internal synchronization

Command 5 identification code Display control setup

Switches between interlaced and noninterlaced video.

Switches the SYNC

JDG

(pin 8) output.

Switches between external and internal synchronization

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0 5 — 0

4 BCL

0 Background coloring on

Only valid in internal synchronization mode.

1 No background coloring (Only the background level is set)

3 CB

0 Color burst signal output.

Only valid when BCL is high.

1 Color burst signal output stopped.

2 PH2

1 PH1

0 PH0

Background color specification

*: When 2 fsc is used.

PH2 PH1 PH0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

Page 16

No. 5520-16/24

LC74785, LC74785M

COMMAND6 (Synchronizing signal detection setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 0

3 SEL0

0 Sync separator signal

Switches the SEP

OUT

(pin 19) output.

1 Output signal set by MOD0

2 MOD0

0 High-level output

Only valid when SEL0 is high.

1 ST pulse signal

1 DISLIN

0 12 lines

Switches the number of lines displayed.

1 10 lines

0 MUT

0 Normal output

OUT

switching

1 CV

is cut and CV

OUT

is held at the pedestal level.

Command 6 identification code Sets up synchronizing signal control.

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 RN2

0 1

5 RN1

0 1

4 RN0

0 1

3 SN3

0 1

2 SN2

0 1

1 SN1

0 1

0 SN0

0 1

External synchronizing signal detection control Signal absent → signal present transition detection Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H).

External synchronizing signal detection control Signal present → signal absent transition detection Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H).

RN2 RN1 RN0 Number of times HSYNC detected

0 0 0 0 times 0 0 1 4 times 0 1 0 8 times 1 0 0 16 times

SN3 SN2 SN1 SN0 Number of times HSYNC detected

0 0 0 0 Not detected 0 0 0 1 32 times 0 0 1 0 64 times 0 1 0 0 128 times 1 0 0 0 256 times

Page 17

No. 5520-17/24

LC74785, LC74785M

COMMAND7 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0

Extended command 0 identification code

2 — 0 1 SEL1

0 Vertical synchronizing signal (external V separation) input 1 Frame signal input

0 CTL3

0 Use internal V separation.

Switches V separation.

1 Do not use internal V separation.

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit 6 — 0 5 — 0

4 VNPSEL

0 V falling edge detection 1 V rising edge detection

3 VSPSEL

0 VSEP: about 8.9 µs

Switches the internal V separation period.

1 VSEP: about 17.8 µs

2 MSKERS

0 Mask valid

Clears the HSYNC and VSYNK masks.

1 Mask invalid

1 MSKSEL

0 3H

Switches the VSYNC mask.

1 20H

0 EGL

0 Border level 0 only (VBK0) 1 Two-stage border level (VBK0 and VBK1)

Switches the V acquisition polarity in external mode when internal V separation is used.

Switches the border level. (Only valid when BLK0 is 0 and BLK1 is 1.)

Switches the SEP

(pin 20) input.

Only valid when CTL3 is high.

Command 7 identification code Display control setup

Page 18

No. 5520-18/24

LC74785, LC74785M

COMMAND8 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 0

Extended command 1 identification code

2 — 1 1 SEL2

0 External synchronizing signal judgment output signal 1 O/E signal

0 MOD1

0 Even field line 21 data extraction (VCR) 1 Line 21 data extraction on both odd and even fields (NTSC-TV)

Command 8 identification code Display control setup

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNA3

5 LNA2

4 LNA1

3 LNA0

2 LPA2

1 LPA1

0 LPA0

Specifies the line whose background is to be changed (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.)

Specifies the background color.

LPA2 LPA1 LPA0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

LNA3 LNA2 LNA1 LNA0 Specified line

0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12

*: When 2 fsc is used.

Switches line 21 data extraction.

Switches the SYNC

JDG

(pin 8) output

Valid when HLFTON is low.

Page 19

No. 5520-19/24

LC74785, LC74785M

COMMAND9 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 1

Extended command 2 identification code

2 — 0

1 LNBSEL

0 Normal line background color operation

0 MOD2

0 LNBSEL: 1 setting specification

Valid when LNBSEL is high

RV characters have the background color specified by PH*, characters are white.

Command 9 identification code Display control setup

RV characters have the background color specified by PH* or the RV character background color is white.

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNB3

5 LNB2

4 LNB1

3 LNB0

2 LPB2

1 LPB1

0 LPB0

Switches the RV mode background color for the line specified by LNB* for characters specified for RV display.

Specifies the background color.

LPB2 LPB1 LPB0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

LNB3 LNB2 LNB1 LNB0 Specified line

*: When 2 fsc is used.

Page 20

No. 5520-20/24

LC74785, LC74785M

COMMAND10 (Display control setup command) First byte

Contents

Notes

0 to 7 State Function

7 — 1 6 — 1 5 — 1 4 — 1 3 — 1

Extended command 2 identification code

2 — 0

1 LNCSEL

0 Normal line background color operation

0 MOD3

0 LNCSEL: 1 setting specification

Valid when LNCSEL is high

RV characters have the background color specified by PH*, characters are white.

Command 10 identification code Display control setup

RV characters have the background color specified by PH* or the RV character background color is white.

Second byte

Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.

Contents

Notes

0 to 7 State Function

7 — 0 Second byte identification bit

6 LNC3

5 LNC2

4 LNC1

3 LNC0

2 LPC2

1 LPC1

0 LPC0

Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.)

Switches the RV mode background color for the line specified by LNC* for characters specified for RV display.

Specifies the background color.

LPC2 LPC1 LPC0 Background color (phase)

0 0 0 Cyan * 0 0 1 Yellow * 0 1 0 Red * 0 1 1 Blue * 1 0 0 Cyan - blue 1 0 1 Green * 1 1 0 Orange 1 1 1 Magenta *

LNC3 LNC2 LNC1 LNC0 Specified line

*: When 2 fsc is used.

Page 21

Display Screen Structure

The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses.

Display Screen Structure (display memory addresses)

No. 5520-21/24

LC74785, LC74785M

24 Characters

12 Rows

Page 22

Composite Video Signal Output Levels (internally generated levels)

OUT

output level waveform (VDD2 = 5.00 V)

No. 5520-22/24

LC74785, LC74785M

Output level Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V]

CHA

: Character 2.67 2.87 3.16

RSH

High for background

2.45 2.64 2.93

colors other than blue

RSH

1,2

High for blue back-

2.09 2.29 2.58

ground colors 1 and 2

1: Border 1 2.09 2.29 2.58

CBH

High for the color

1.75 1.95 2.23

burst signal

RSL

Low for blue back-

1.61 1.80 2.09

ground color 2

0: Border 0 1.52 1.72 2.01

: Pedestal level 1.44 1.64 1.93

RSL

Low for background

1.29 1.48 1.77

colors other than blue

RSL

Low for blue back-

1.20 1.39 1.68

ground color 1

CBL

Low for the color

1.10 1.29 1.58

burst signal

: Sync 0.82 1.01 1.30

Note: VDD2 = 5.0 V.

Page 23

Sample Application Circuit (When the LC74785/M is used in conjunction with a single-chip Y/C circuit.)

No. 5520-23/24

LC74785, LC74785M

External system clock input

Crystal oscillator

External system clock input (when the pin 3 and 4 functions are modified by mask options)

Note: When a sync tip level of 1.3 V DC (CVINinput signal: sync tip = 1.3 V) is selected for the internal generated video signals by option settings, the

electrolytic capacitor connected to SYN

must be connected with the correct polarity.

When V

1 is 5.0 V, the SYNINinput video signal pedestal level is clamped at about 2.5 V DC.

Microprocessor

MicroprocessorMicroprocessor

Page 24

No. 5520-24/24

LC74785, LC74785M

This catalog provides information as of June, 1997. Specifications and information herein are subject to change without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:

➀

Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:

➁

Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

Datasheet LC74785M, LC74785 Datasheet (SANYO)

Specifications and Main Features

Frequently Asked Questions

User Manual