Memory Organization (display RAM and control RAM)
Both memory addresses and data are 16-bit quantities.
The locations at addresses 000 (000 hexadecimal) to 175 (0AF hexadecimal) hold display memory (RAM) data.
The locations at addresses 176 (0B0 hexadecimal) to 191 (0BF hexadecimal) hold display control register data.
No. 5396-6/15
LC74751
Bit DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA
Notes
Address F E D C B A 9 8 7 6 5 4 3 2 1 0
000
0 0 0 0 0 0 0 0 ATTR C6 C5 C4 C3 C2 C1 C0
(000h)
ATTR Character code Display RAM
175
0 0 0 0 0 0 0 0 ATTR C6 C5 C4 C3 C2 C1 C0
(0AFh)
176
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B0h) A 9 8 7 6 5 4 3 2 1 0 First character in the first line
177
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B1h) A 9 8 7 6 5 4 3 2 1 0 First character in the second line
178
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B2h) A 9 8 7 6 5 4 3 2 1 0 First character in the third line
179
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B3h) A 9 8 7 6 5 4 3 2 1 0 First character in the fourth line
180
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B4h) A 9 8 7 6 5 4 3 2 1 0 First character in the fifth line
181
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B5h) A 9 8 7 6 5 4 3 2 1 0 First character in the sixth line
182
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B6h) A 9 8 7 6 5 4 3 2 1 0 First character in the seventh line
183
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B7h) A 9 8 7 6 5 4 3 2 1 0 First character in the eighth line
184
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B8h) A 9 8 7 6 5 4 3 2 1 0 First character in the ninth line
185
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B9h) A 9 8 7 6 5 4 3 2 1 0 First character in the tenth line
186
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0BAh) A 9 8 7 6 5 4 3 2 1 0 First character in the eleventh line
187
0 0 0 0 0
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0BBh) A 9 8 7 6 5 4 3 2 1 0 First character in the twelfth line
188
0 0 0 0
HSZ HSZ HSZ HSZ HSZ HSZ
HP5 HP4 HP3 HP2 HP1 HP0
Horizontal display position
(0BCh) 31 30 21 20 11 10 Horizontal character size
189
0 0 0 0
VSZ VSZ VSZ VSZ VSZ VSZ
VP5 VP4 VP3 VP2 VP1 VP0
Vertical display position
(0BDh) 31 30 21 20 11 10 Vertical character size
190
0 0 0 0
INT/ LC/ 2fsc/ OSC DSP
MUTE
SYS SIG SIG PHASE PHASE PHASE
Video signal and other items
(0BEh) NON XTAL 4fsc STP ON RST MD1 MD0 2 1 0
191
0 0 0 0
TST VSN
0
BLK BLK RVS BLINK BLINK BLINK EXT/
CBOFF BCOL Control register
(0BFh) MOD SEP 1 0 ON 2 1 0 INT