Datasheet LC74732W, LC74731W Datasheet (SANYO)

Ordering number : ENN*6526

63000RM (OT) No. 6526-1/38

Overview

The LC74731W and LC74732W are on-screen display
CMOS ICs that display characters and patterns on a TV
screen under the control of a microcontroller. These ICs
display 16 × 16-dot characters and up to 12 lines of text
with 24 characters per line.

Features

• Text structure: 12 lines × 24 characters (Up to 288

characters)

• Character format: 16 × 16 dots

Character display clock frequency: about 9 MHz

• Character sizes: Four sizes each in the horizontal and
vertical directions with the size set in line units.

• Number of characters supported:
LC74731W:256 (internal)
LC74732W:512 (internal)
Up to 8192 using an external ROM (for Japanese)
[Reference] JIS X0298 (1990): 6877 characters

JIS level 1 kanji: 2965 characters
JIS level 2 kanji: 3388 characters
Special characters: 524 characters

• Display start positions: 128 positions each in the
horizontal and vertical directions

• Blinking, reverse video, reversed blinking, and character
outlining: May be specified in individual character units.

• Blinking types: Two types with periods of about 1.0 and
about 0.5 seconds.

• Blanking: The whole font area (16 ×16 dots) can be
blanked in line units
(Four types: no blanking, character size blanking,
character plus outlining size blanking, and whole area up
to adjacent character blanking)

• Line spacing control: Zero to seven scan lines, in line
units

• Character color: Eight colors in character units (in
internal synchronization mode): 2 fsc and 4 fsc
(Black, red, green, yellow, blue, magenta, cyan, and
white)

• Character background color: Eight colors (in internal
synchronization mode): 2 fsc and 4 fsc
(Black, red, green, yellow, blue, magenta, cyan, and
transparent)

• Screen background color: Eight colors (in internal
synchronization mode): 2 fsc and 4 fsc
(Black, red, green, yellow, blue, magenta, cyan, and
white)

• External control inputs: Serial interface with an 8-bit
data size.

• Built-in sync separator circuit

• Video outputs: NTSC, PAL, PALM, PALN, NTSC

4.43, and PAL 60 composite video signal outputs

• Supports Y/C input

Package Dimensions

Preliminary

LC74731W,74732W

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

On-Screen Display Controller

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

10.0

12.0

1.25

0.5

1.25

1.25 0.5 1.250.18

12.0

116

17

32

33

48

49

64

10.0

0.5

1.7max

0.5

0.1

0.15

SANYO: SQFP64

[LC74731W,74732W]

Pin Assignment

No. 6526-2/38

LC74731W,74732W

1VSS1

48

A6

2XTALin

47

A7

3XTALout

46

A8

4CTRL1

45

A9

5OSCin

44

A10

6OSCout

43

A11

7MUTE

42

A12

8CDLR

41

A13

9SYNCjdg/Rout

40

A14

10CHARA/Gout

39

A15

11BLANK/Bout

38

A16

12IEOUT/BLKout

37

A17

13OUTMOD

36

V

DD

1

14CS

35

RST

15SIN

(V) 34

SEPin

16SCLK

33

SEPout

(H)

Cout

Cin

-NC-

-NC-

V

SS

2

-NC-

CVcr

SYNin

V

DD

2

-NC-

Cbias

Yout

Yin

CVout

CVin

HFTin

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

63D162D261D360D459D558D657D756CE55OE54A053A152A251A350A449

A5

64

D0

No. 6526-3/38

LC74731W,74732W

Pin Functions

Pin No. Pin Function Description

1V

SS

1 Ground Ground connection. (Digital system ground)

2 Xtalin

Crystal oscillator connections

Connections for the crystal element and capacitors that form the internal sync signal generating

3 Xtalout

crystal oscillator. Xtalin can also be used to input an external clock signal. (2fsc or 4fsc)

4 CTRL1

Switches the crystal oscillator Selects external clock input mode or crystal oscillator mode. Low: crystal oscillator mode, high:
input external clock input mode.

5 OSCin

LC oscillator connections Connections for the coil and capacitor that form the character output dot clock generation oscillator.

6 OSCout

This is an active-low input with hysteresis characteristics (MORE+).
When low, the

7 MUTE Muting control input

CVout, Yout, and Cout outputs are set to either,

(1) CSYNC, CSYNC, PE, or
(2) PE PE, PE.

In the initial state, (1) is selected. This setting is switched by commands.

8 CDLR

Background color phase

Connection for the resistor used to adjust the background color phase

adjustment

Outputs the result of the judgment as to whether or not the external sync signal is present.

9

SYNCJDG External sync signal judgment A high level is output when a sync signal is present.

/Rout output (Rout output) The dot clock (LC oscillator) is output when RST is low.

(The IC can be set up to not output this signal during resets by commands.)

10 CHARA/Gout

Character output

Character signal output

(Gout output)

11 BLANK/Bout Blank output (Bout output) Blank signal output pin
12 IEout/BLKout

Internal/external output

Internal synchronization (high)/external synchronization (low) state output pin

(BLKout output)

13 OUTMOD Output switching input

Switches between output from pins 9 to 12 and input to pin 32.
Low: normal operation, high: RGB output supported

Serial data input enable

14 CS Enable input Serial data input is enabled when low.

more+ (Hysteresis input characteristics)

15 SIN Data input

Serial data input
more+ (Hysteresis input characteristics)

16 SCLK Clock input

Serial data input clock input
more+ (Hysteresis input characteristics)

17 V

DD

2 Power supply Composite video signal level adjustment power supply. (Analog system power supply)
18 COUT Color signal output Color (C) signal output
19 NC This pin must either be left open or connected to ground.
20 CIN Color signal input Color (C) signal input
21 CBIAS Chrominance bias output Chrominance signal bias level output
22 NC This pin must be either left open or connected to ground.
23 YOUT Luminance signal output Luminance signal (Y) output
24 NC This pin must be either left open or connected to ground.
25 YIN Luminance signal input Luminance signal (Y) input
26 V

SS

2 Ground Ground
27 CVOUT Video signal output Composite video signal output
28 NC This pin must either be left open or connected to ground.
29 CVIN Video signal input Composite video signal input
30 CVCR Video signal input SECAM chrominance signal input
31 HFTin Halftone signal input Halftone signal input
32 SYNin Sync separator circuit input Video signal input to the internal sync separator circuit
33 SEPout Composite sync signal output Composite sync signal output from the internal sync separator circuit

34 SEPin Vertical sync signal input

Vertical sync signal input
MORE+ (Hysteresis input characteristics)

35 RST Reset input

System reset input
A built-in pull-up resistor can be included in this pin’s input circuit. (Hysteresis input characteristics)

36 V

DD

1 Power supply (+5 V) Power supply (+5 V: digital system power supply)

Continued on next page.

No. 6526-4/38

LC74731W,74732W

Continued from preceding page.

Pin No. Pin Function Description

37 A17 Address output 17 ROM address output 17
38 A16 Address output 16 ROM address output 16
39 A15 Address output 15 ROM address output 15
40 A14 Address output 14 ROM address output 14
41 A13 Address output 13 ROM address output 13
42 A12 Address output 12 ROM address output 12
43 A11 Address output 11 ROM address output 11
44 A10 Address output 10 ROM address output 10
45 A9 Address output 9 ROM address output 9
46 A8 Address output 8 ROM address output 8
47 A7 Address output 7 ROM address output 7
48 A6 Address output 6 ROM address output 6
49 A5 Address output 5 ROM address output 5
50 A4 Address output 4 ROM address output 4
51 A3 Address output 3 ROM address output 3
52 A2 Address output 2 ROM address output 2
53 A1 Address output 1 ROM address output 1
54 A0 Address output 0 ROM address output 0
55 OE Output enable ROM output enable output. This is an active-low output.
56 CE Chip enable ROM chip enable output. This is an active-low output.
57 D7 Data input 7 ROM data input 7. MORE+ (Hysteresis input characteristics)
58 D6 Data input 6 ROM data input 6. MORE+ (Hysteresis input characteristics)
59 D5 Data input 5 ROM data input 5. MORE+ (Hysteresis input characteristics)
60 D4 Data input 4 ROM data input 4. MORE+ (Hysteresis input characteristics)
61 D3 Data input 3 ROM data input 3. MORE+ (Hysteresis input characteristics)
62 D2 Data input 2 ROM data input 2. MORE+ (Hysteresis input characteristics)
63 D1 Data input 1 ROM data input 1. MORE+ (Hysteresis input characteristics)
64 D0 Data input 0 ROM data input 0. MORE+ (Hysteresis input characteristics)

No. 6526-5/38

LC74731W,74732W

Specifications

Maximum Ratings at Ta = 25°C

Parameter Symbol Conditions

Ratings

Unit

min max

Supply voltage V

DDVDD

1 and VDD2V

SS

– 0.3 VSS+ 6.5 V

Input voltage V

IN

All input pins VSS– 0.3 VDD1 + 0.3 V

Output voltage V

OUT

SYNCJDG, BLANK, CHARA, SEPOUT, A0 to A17,

V

SS

– 0.3 VDD1 + 0.3 V

CE, and OE
Allowable power dissipation Pdmax — 275 mW
Operating temperature Topr –30 +70 °C
Storage temperature Tstg –40 +125 °C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

V

DD

1VDD1 4.5 5.0 5.5 V

V

DD

2VDD2 4.5 5.0 6.5 V

Supply voltage

V

DD

1VDD1 2.7 5.0 5.5 V

[Only for RGB output]

V

DD

2VDD2 2.7 5.0 6.5 V

V

IH

1 CS, SIN, SCLK, SEPIN, and MUTE

0.8 VDD1

— 5.5 V

High-level input voltage

V

IH

2 RST

0.8 VDD1

—

VDD1 + 0.3

V

V

IH

3 CTRL1 and OUTMOD

0.7 VDD1

—

VDD1 + 0.3

V

V

IH

4 D0 to D7

0.8 VDD1

— 5.5 V

V

IL

1 RST, CS, SIN, SCLK, SEPIN, and MUTE VSS– 0.3 —

0.2 VDD1

V

Low-level input voltage V

IL

2 CTRL1 and OUTMOD VSS– 0.3 —

0.3 VDD1

V

V

IL

3 D0 to D7 VSS– 0.3 —

0.2 VDD1

V

Pull-up resistor R

PU

RST, CS, SIN, SCLK, and MUTE (when the pull-up

25 50 90 kΩ

resistor option is specified)
Composite video signal input

VIN1 CVIN and CVCR VDD1 = 5 V — 2.0 — Vp-p

voltage

V

IN

2 SYNIN VDD1 = 5 V 1.5 2.0 2.5 Vp-p

Input voltage V

IN

3

XtalIN (when an external clock input is used)

VDD1 = 5 V — — 5.0 Vp-p

fin = 2 fsc, 4 fsc

The XtalIN and XtalOUT oscillator pins (2 fsc: NTSC) 7.159 MHz

F

OSC1

The XtalIN and XtalOUT oscillator pins (4 fsc: NTSC) 14.318 MHz
Oscillator frequency The XtalIN and XtalOUT oscillator pins (2 fsc: PAL) — 8.867 — MHz

The XtalIN and XtalOUT oscillator pins (4 fsc: PAL) — 17.734 — MHz

F

OSC2

The OSCin and OSCout oscillator pins (LC oscillator) — 10 — MHz

Recommended Operating Conditions

Note: If the Xtalin pin is used in clock input mode, applications must take adequate input noise prevention and reduction measures.

No. 6526-6/38

LC74731W,74732W

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max

Input off leakage current Ileak1 CV

IN

, CVCR, CIN, and Y

IN

—— 1µA

Output off leakage current Ileak2 CV

OUT

, C

OUT

, and Y

OUT

—— 1µA

V

OH

11

SYNCJDG, SETPOUT, V

DD

1 = 5.5 to 4.5 V

0.9 V

DD

1——V

BLANK, CHARA, and IEOUT I

OH

= –1.0 mA

V

OH

12

SYNCJDG, SETPOUT, V

DD

1 = 4.4 to 2.7 V

0.9 V

DD

1——V

High-level output voltage

BLANK, CHARA, and IEOUT I

OH

= –0.5 mA

V

OH

21 A0 to A17, OE, and CE

V

DD

1 = 5.5 to 4.5 V

0.9 V

DD

1——V

I

OH

= –1.0 mA

V

OH

22 A0 to A17, OE, and CE

V

DD

1 = 4.4 to 2.7 V

0.9 V

DD

1——V

I

OH

= –0.5 mA

V

OL

11

SYNCJDG, SEPOUT, V

DD

1 = 5.5 to 4.5 V

— — 0.1 V

DD

1V

BLANK, CHARA, and IEOUT I

OL

= 1.0 mA

V

OL

12

SYNCJDG, SEPOUT, V

DD

1 = 4.4 to 2.7 V

— — 0.1 V

DD

1V

Low-level output voltage

BLANK, CHARA, and IEOUT I

OL

= 0.5 mA

V

OL

21 A0 to A17, OE, and CE

V

DD

1 = 5.5 to 4.5 V

— — 0.1 V

DD

1V

I

OL

= 1.0 mA

V

OL

22 A0 to A17, OE, and CE

V

DD

1 = 4.4 to 2.7 V

— — 0.1 V

DD

1V

I

OL

= 0.5 mA

I

IH

RST, CS, SIN, SCLK, CTRL1,

V

IN

= VDD1——1µA

Input current

MUTE, and OUTMOD

I

IL

CS, SIN, SCLK, CTRL1, and

V

IN

= VSS1 –1——µA

OUTMOD

All outputs: open

Operating current drain

I

DD

1VDD1 Xtal: 17.734 MHz — — 40 mA

LC: 10 MHz

IDD2VDD2V

DD

2 = 5 V 20 mA

Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.

Continued on next page.

No. 6526-7/38

LC74731W,74732W

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max

(1) 0.80

SYNC level V

SN

(2) 1.00 V
(3) 1.40
(1) 1.37

Pedestal level V

PD

(2) 1.57

V
(3) 1.97
(1) 1.07

Color burst low level V

CBL

(2) 1.27

V
(3) 1.67
(1) 1.67

Color burst high level V

CBH

(2) 1.87

V
(3) 1.27

CVOUT

(1) 1.23

Background color 1 low level V

RSL

1

(1): When SYNC – LEVEL = 0.8 V

VDD1 = 5.0 V

(2) 1.43

V

(2): When SYNC – LEVEL = 1.0 V

VDD2 = 5.0 V

(3) 1.83

(3): When SYNC – LEVEL = 1.4 V

(1) 2.37

Background color 1 high level V

RSH

1

(2) 2.57

V
(3) 2.97
(1) 1.52

Background color 2 low level V

RSL

2

(2) 1.72

V
(3) 2.12
(1) 2.01

Background color 2 high level V

RSH

2

(2) 2.21

V
(3) 2.61
(1) 1.50

Outlining level 1 VBK1

(2) 1.70

V
(3) 2.10
(1) 1.80

Outlining level 2 VBK2

(2) 2.00

V
(3) 2.40
(1) 2.08

Outlining level 3 VBK3

(2) 2.28

V
(3) 2.68
(1) 2.65

Character level 1 V

CHA

1

(2) 2.85

V
(3) 3.25
(1) 2.23

Character level 3 V

CHA

3

(2) 2.43

V
(3) 2.83

Continued from preceding page.

Supplementary Materials

Figure 1 OSD Serial Data Input Timing

No. 6526-8/38

LC74731W,74732W

tw(cs)

CS

t

su

(cs) tw(sclk) tw(sclk) th(cs)

SCLK

t

su

(sin) th(sin)

SIN

t

word

t

wt

SCLK

01 567 01 5467

CS

Parameter Symbol Conditions

Ratings

Unit

min typ max

Minimum input pulse width

t

w

(sclk) SCLK 200 — — ns

t

w

(cs) CS (the period when CS is high) 1 — — µs

Data setup time

t

su

(cs) CS 200 — — ns

t

su

(sin) SIN 200 — — ns

Data hold time

t

h

(cs) CS 2 — — µs

t

h

(sin) SIN 200 — — ns

One word write time

t

word

The time to write 8 bits of data 4.2 — — µs

t

wt

RAM data write time 1 — — µs

OSD Write (See figure 1.) at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V

System Block Diagram

No. 6526-9/38

LC74731W,74732W

OSC IN

SYNC JDG

RST

OUTMOD

IEOUT

BLANK

CHARA

MUTE

SCLK

SIN

CS

SEP

C

SEP OUT

OSC OUT

SEP IN

SYN IN

VDD1, VDD2

VSS1, VSS2

CV OUTCDLR

C

IN Cbias

Yout

Yin

CV

INCTRL1 Xtal IN Xtal OUT CVCR Cout

Serial to

parallel

converter

Character

output

dot clock

oscillator

Synchronous

judgment

Composite

sync

separator

control

Sync

separator

circuit

8-bit

latch and

command

decoder

Horizontal

character

size register

Horizontal

size counter

Vertical

size counter

Timing generator

Horizontal

dot counter

Horizontal

display position

detection

Vertical

display position

detection

Character

control counter

Sync signal generator

Character output control

Background control

Video output control

Line control

counter

Vertical

dot counter

Blinking and

reverse video

control circuit

Vertical

character

size register

Horizontal

display

position register

Vertical

display

position register

Blinking and

reverse video

control register

Display control

register

RAM write

address counter

Display RAM

Decoder

Font ROM

Shift register

Decoder

A0 to A17,

OE, CE

D0 to D7

No. 6526-10/38

LC74731W,74732W

Display Control Commands

Display Control Commands

Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of
a command identification code in the first byte and command data in the following bytes.

First byte Second byte

Command

Command identification code

Data Data

7654321076543210

COMMAND0

1000V3V2V1V0000H4H3H2H1H0

(Write address setup)

at2 at1 CB2 CB1 CB0 CC2 CC1 CC0

COMMAND1 (Character write) 1001IRSD2SD1SD0000C12C11C10C9C8

C7 C6 C5 C4 C3 C2 C1 C0

COMMAND20

101000RRM1 RRM0 0 VP6 VP5 VP4 VP3 VP2 VP1 VP0

(Vertical display start position)
COMMAND21

101001000HP6HP5HP4HP3HP2HP1HP0

(Horizontal display start position)
COMMAND22

1010100SRM0000VS1VS0HS1HS0

(Character size)
COMMAND23

1010110

LSZUD

00

LSZB5 LSZA4 LSZ93 LSZ82 LSZ71 LSZ60

(Character size - in line units)
COMMAND3

1011

TSTMOD RAMERS OSCSTP SYSRST

0

LCSOFF XN53S BLKSEL

LC FS BK

DSPON

(Display control)
COMMAND4

1100NP2NP1NP0I/N0

HLFINT

BCL1 BCL0 CB PH2 PH1 PH0

(Display control)
COMMAND50

110100DISLIN I/E 0 RN2 RN1 RN0 SN3 SN2 SN1 SN0

(Sync signal detection 1)
COMMAND51

110101MUT1 MUT0 0 O RNE0 SJN3 SJN2 SJN1 SJC1 SJC0

(Sync signal detection 2)
COMMAND52

110110

EVEBSS LSPSS

0

CINSEL CINCTL VNPSEL VSPSEL MSKERS MSKSEL EGLSEL

(Display control)
COMMAND53

110111

RSLG1 RSLG0

00

CTL3 SPOSEL PALAL4 IHSEL VSSEL HSSEL

(Display control)
COMMAND60

1110000BRM0

BXBLV1 BXBLV0 BXWLV1 BXWLV0 ATSEL BLK1 BLK0

(Outlining setting)
COOMAND61

1110010

LFCUD

00

LFCB5 LFCA4 LFC93 LFC82 LFC71 LFC60

(Outlining setting - in line units)
COMMAND62

1110100GRM0OBXC1 GS1 GS0 GY2 GY1 GY0

(Line spacing)
COMMAND63

1110110

LGYUD

00

LGYB5 LGYA4 LGY93 LGY82 LGY71 LGY60

(Line spacing - in line units)
COMMAND70

1111000LRM00

BKLC1 BKLC0 CHLC1 CHLC0 RSLC1 RSLC0

(Display level)
COMMAND71

1111010

LCLUD

00

LCLB5 LCLA4 LCL93 LCL82 LCL71 LCL60

(Display level - in line units)
COMMAND72

111110

LHTDAT LHTUD

00LHTB5 LHTA4 LHT93 LHT82 LHT71 LHT60

(Halftone - in line units)
COMMAND73

111111000

DASSS GBSEL OUTSEL HSPSW XONSS BLK01 BLK00

(RGB control)

Note that when the display character data write command (COMMAND1) is written, tthese ICs lock into the display character data write mode, and another
first byte cannot be written.
When the CS pin is set high, the these ICs are set to the COMMAND0 (display memory write address setup mode) state.

COMMAND0 (Display memory write address setup command)

No. 6526-11/38

LC74731W,74732W

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 0 identification code
6 — 0 Display memory write address setup
5—0
4—0

3V3

0 Display memory line address (0 to B (hexadecimal))
1

2V2

0
1

1V1

0
1

0V0

0
1

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification code
6—0
5—0

4H4

0 Display memory line address (0 to 17 (hexadecimal))
1

3H3

0
1

2H2

0
1

1H1

0
1

0H0

0
1

No. 6526-12/38

LC74731W,74732W

COMMAND1 (Display character data write setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7—1
6 — 0 Command 1 identification code
5 — 0 Display character data write settings
4—1

3IR

0 Internal ROM Switching between internal and external ROM
1 External ROM

2 SD2

0 White-on-black (convex) display Character frame specification
1 Black-on-white (concave) display

1 SD1

0 Character frame start: off
1 Character frame start: on

0 SD0

0 Character frame stop: off
1 Character frame stop: on

• Second byte (1)

DA0 to 7 Register

Content

Notes

State Function

0

Character attribute 2: off Blinking specification

7 at2

(Character frame upper side: off) Selected by COM60 second byte and ATSEL.

1

Character attribute 2: on
(Character frame upper side: on)

0

Character attribute 1: off Reverse video specification

6 at1

(Character frame lower side: off) Selected by COM60 second byte and ATSEL.

1

Character attribute 1: on
(Character frame lower side: on)

5 cb2

0 cb2 cb1 cb0 Character background color Character background color specification
1(B G R)

4 cb1

0 0 0 0 Black
1 0 0 1 Red
0 0 1 0 Green

0 1 1 Yellow

3 cb0

1 0 0 Blue

1 1 0 1 Magenta

1 1 0 Cyan
1 1 1 Transparent

2 cc2

0 cc2 cc1 cc0 Character color Character color specification
1(B G R)

1 cc1

0 0 0 0 Black
1 0 0 1 Red
0 0 1 0 Green

0 1 1 Yellow

0 cc0

1 0 0 Blue

1 1 0 1 Magenta

1 1 0 Cyan
1 1 1 White

Note that when this command is input, the
LC74731W/74732W lock into the display character
data write mode until the CS pin is set high.

No. 6526-13/38

LC74731W,74732W

• Second byte (2)

DA0 to 7 Register

Content

Notes

State Function
7—0
6—0
5—0

4 c12

0 Character code (00xx to 1Fxx (hexadecimal)) External ROM upper address
1

3 c11

0
1

2 c10

0
1

1 c09

0
1

0 c08

0
1

• Second byte (3)

Note that all registers are set to 0 when these ICs are reset by the RST pin.

Continuous mode (cleared by setting CS high) operates as follows according to IR.
When internal ROM is specified: 1-1 1-2-1 1-2-2 1-2-3 1-2-3 1-2-3 1-2-3

When external ROM is specified: 1-1 1-2-1 1-2-2 1-2-3 1-2-2 1-2-3 1-2-2 1-2-3

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function

7 c07

0 Character code (00 to FF (hexadecimal)) External ROM lower address
1 FE (hexadecimal): Space character Internal ROM address

6 c06

0 FF (hexadecimal): Transparent space character
1

5 c05

0
1

4 c04

0
1

3 c03

0
1

2 c02

0
1

1 c01

0
1

0 c00

0
1

No. 6526-14/38

LC74731W,74732W

COMMAND20 (Vertical display start position setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 2 identification code
6 — 0 Vertical display position and vertical direction character size
5 — 1 settings
4—0
3 — 0 Extended command 0 identification code
2—0

1 RRM1

0 RRM1 RRM0 Continuous RAM write mode specification
1 0 0 Initial value (depends on IR)
0 0 1 1-2-1 1-2-2 1-2-3 Fixed

0 RRM0

1

1 0 1-2-2 1-2-3 Fixed
1 1 1-2-3 Fixed

• Second byte

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6

VP6

0 If VS is the vertical display start position then:

The vertical display start position is set by the 7 bits

(MSB)

1

VP0 to VP6.

5 VP5

0 The weight of bit 1 is 2H.
1 H: the horizontal synchronization pulse period

4 VP4

0 α = 20H (525H systems)
1 = 25H (625H systems)

3 VP3

0
1

2 VP2

0
1

1 VP1

0
1

0

VP0

0

(LSB)

1

6

VS = α + H × (2∑2nVPn)

n=0

HSYNC

HS

VS

Character display area

VSYNC

No. 6526-15/38

LC74731W,74732W

COMMAND21 (Horizontal display start position setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 2 identification code
6 — 0 Horizontal display position setup and horizontal direction
5 — 1 character size settings
4—0
3 — 0 Extended command 1 identification code
2—1
1—0
0—0

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6

HP6

0 If HS is the horizontal start position then: The horizontal display start position is set by the 7

(MSB)

1 bits HP0 to HP6.

5 HP5

0 The weight of bit 1 is 2Tc.
1

4 HP4

0 Tc: Period of the oscillator connected to OSCIN/OSCOUT in
1 operating mode.

3 HP3

0
1

2 HP2

0
1

1 HP1

0
1

0

HP0

0

(LSB)

1

6

HS =Tc × (2∑ 2nHPn)

n=0

No. 6526-16/38

LC74731W,74732W

COMMAND22 (Character size setting command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 2 identification code
6 — 0 Horizontal display position setup and horizontal direction
5 — 1 character size settings
4—0
3 — 1 Extended command 2 identification code
2—0
1—0

0 SRM

0 Continuous mode: off Character size continuous mode specification
1 Continuous mode: on

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0
5—0
4—0

3 VS1

0 VS1 VS0 Character size Vertical direction character size, in line units
100 1×
001 2×

2 VS0

1

10 3×
11 4×

1 HS1

0 HS1 HS0 Character size Horizontal direction character size, in line units
100 1×
001 2×

0 HS0

1

10 3×
11 4×

No. 6526-17/38

LC74731W,74732W

COMMAND23 (Character size and line setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 2 identification code
6 — 0 Horizontal display position setup and horizontal direction
5 — 1 character size settings
4—0
3 — 1 Extended command 3 identification code
2—1
1—0

0 LSZUD

0 Lower lines: 0 to 5 (hexadecimal) Upper/lower line specification
1 Upper lines: 6 to B (hexadecimal)

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 LSZB5

0 Line 6 (line 12) specification: off

The line shown in parentheses is specified when

1 Line 6 (line 12) specification: on

LSZUD is 1.

4 LSZA4

0 Line 5 (line 11) specification: off
1 Line 5 (line 11) specification: on

3 LSZ93

0 Line 4 (line 10) specification: off
1 Line 4 (line 10) specification: on

2 LSZ82

0 Line 3 (line 9) specification: off
1 Line 3 (line 9) specification: on

1 LSZ71

0 Line 2 (line 8) specification: off
1 Line 2 (line 8) specification: on

0 LSZ60

0 Line 1 (line 7) specification: off
1 Line 1 (line 7) specification: on

No. 6526-18/38

LC74731W,74732W

COMMAND3 (Display control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 3 identification code
6 — 0 Display character data write settings
5—1
4—1

3 TSTMOD

0 Normal operating mode This bit must always be 0.
1 Test mode

2 RAMERS

0 The RAM erase operation takes about 500 µs. (It
1 Erase display RAM (sets the data to FF (hexadecimal)) must be executed in the DSPOFF state.)

1 OSCSTP

0 Do not stop the crystal and LC oscillator circuits. This setting is valid in external synchronization
1 Stop the crystal and LC oscillator circuits. mode when character display is off.

0 SYSRST

0 The reset occurs when the CS pin is low, and is
1 Reset all registers. This turns the display off. cleared when CS is set high.

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6 LCSOFF

0 Normal operation Switches the LC oscillator STOP control
1 LC oscillator STOP: Disabled

5 XN53S

0 Normal Switches the crystal oscillator capability
1 Switching

4 BLKSEL

0 Character display area Specifies the character size that fills the whole
1 Video display area character area.

3LC

0 The LC oscillator is used as the dot clock. Selects the dot clock used for character display in
1 The crystal oscillator is used as the dot clock. the horizontal direction.

2FS

0 Crystal oscillator frequency: 2 fsc Sets the crystal oscillator frequency.
1 Crystal oscillator frequency: 4 fsc

1BK

0 Blinking period: 0.5 s Switches the blinking period.
1 Blinking period: 1 s

0 DSPON

0 Character display: off
1 Character display: on

No. 6526-19/38

LC74731W,74732W

COMMAND4 (Display control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 4 identification code
6 — 1 Display control settings
5—0
4—0

3 NP2

0 NP2 NP1 NP0 Signal format Switches the signal format
1 0 0 0 NTSC

2 NP1

0 0 0 1 PAL-M
1 0 1 0 PAL
0 0 1 1 PAL-N

1 NP0 1 1 0 0 NTSC4.43

1 0 1 PAL60

0 I/N

0 Interlaced Switches between interlaced and noninterlaced
1 Noninterlaced

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6 HLFINT

0 Normal mode
1 Semi-internal synchronization mode

5 BCL1

0 BCL1 BCL0 Only valid in internal synchronization mode.
1 0 0 Background color shown
0 0 1 No background color (RSL1)

4 BCL0

1

1 0 No background color (CBH)
1 1 No background color (RSH1)

3CB

0 The color burst signal is output. Only valid when BCL is high.
1 Color burst signal output is stopped.

2 PH2

0 PH2 PH1 PH0 Background color Background color specification
1BGR

1 PH1

0 0 0 0 Black (RSLx)
1 0 0 1 Red
0 0 1 0 Green

0 1 1 Yellow

0 PH0

1 0 0 Blue

1 1 0 1 Magenta

1 1 0 Cyan
1 1 1 White (RSHx)

No. 6526-20/38

LC74731W,74732W

COMMAND50 (Sync signal detection 1 setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 5 identification code
6 — 1 Sync signal control settings
5—0
4—1
3 — 0 Extended command 0 identification code
2—0

1 DISLIN

0 12 lines Switches the number of lines displayed.
1 10 lines

0 I/E

0 External synchronization

Switches between internal and external

1 Internal synchronization

synchronization

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6 RN2

0 RN2 RN1 RN0 Number of times HSYNC detected
1 0 0 0 0 times (32 times)

5 RN1

0 0 0 1 4 times (64 times)
1 0 1 0 8 times (128 times)

4 RN0

0 1 0 0 16 times (256 times)
1

3 SN3

0 SN3 SN2 SN1 SN0 Number of times HSYNC detected
1 0 0 0 0 Not detected

2 SN2

0 0 0 0 1 32 times
1 0 0 1 0 64 times

1 SN1

0 0 1 0 0 128 times
1 1 0 0 0 256 times

0 SN0

0
1

External sync signal detection control
Recognition of the transition from the no signal
state to the signal present state.
Sets the sampling period in which the sync signal
can be detected continuously in the horizontal sync
signal period (1H).
The values in parentheses apply when RNE0
(COM51) is 1.

External sync signal detection control
Recognition of the transition from the signal
present state to the no signal state.
Sets the sampling period time in which the sync
signal cannot be detected continuously in the
horizontal sync signal period (1H).

No. 6526-21/38

LC74731W,74732W

COMMAND51 (Sync signal detection 2 setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 5 identification code
6 — 1 Display control settings
5—0
4—1
3 — 0 Extended command 1 identification code
2—1

1 MUT1

0 MUT1 MUT0 Output Video signal output muting function selection
1 0 0 CSYNC Valid when the MUTE pin is low.

0 MUT0

001PE
1 1 0 A0-17 “Z”

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

0

Sync signal no signal to signal present discrimination - Normal

5 RNE0

values

1

Sync signal no signal to signal present discrimination - Values
shown in parentheses

4 SJNS3

0 SJNS3 SJNS2 SJNS1 Times
1 0 0 0 None

3 SJNS2

00014
10108
001116

10032

2 SJNS1

1

10164
1 1 0 128
1 1 1 256

1 SJCS1

0 SJCS1 SJCS0 PAL NTSC
1 0 0 677 ns (1/3) 558 ns (1/2)

0 SJCS0

0 0 1 903 ns (1/4) 838 ns (1/3)
1 1 0 450 ns (1/2) 1117 ns (1/4)

Noise ignoring circuit setting for sync signal
recognition for the no signal to signal present
transition

If more than the number of horizontal signals
shown at the left are input during a 1H period, the
circuit recognizes a no signal state.

Synchronization discrimination
Selects the clock used to delimit the HSYNI signal.

Changes the judgment criterion values for sync
signal recognition for the no signal to signal
present transition. (COM50)

No. 6526-22/38

LC74731W,74732W

COMMAND52 (Display control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 5 identification code
6 — 1 Display control settings
5—0
4—1
3 — 1 Extended command 2 identification code
2—0

1 EVEBSS

0 Normal Switches the ENBVI signal
1 Always high

0 LSPSS

0 Normal LCSTOP control signal
1 HT12 “on” HT34 “off”

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6 CINSEL

0 Blank area (the logical OR of the character and outlining signals) Switches the CV

CR

on state signal

1 Video signal display area

5 CINCTL

0CV

CR

: off CVCRon/off switching

1CV

CR

: on

4 VNPSEL

0 V signal falling edges detected

Switches the V signal acquisition polarity when

1 V signal rising edges detected

external mode/internal V separation is used

3 VSPSEL

0 VSEP: About 8.9 µs (NTSC) Switches the internal vertical separation time
1 VSEP: About 17.8 µs (NTSC)

2 MSKERS

0 Mask enabled Clears the HSYNC and VSYNC masks
1 Mask disabled

1 MSKSEL

0 3H (NTSC) Switches the VSYNC mask
1 20H (NTSC)

0 EGL

0 Outlining level 0 only (VBK0) Switches the outlining level (Only valid when BLK0
1 Two-stage outlining level (VBK0, VBK1) is 0 and BLK1 is 1.)

No. 6526-23/38

LC74731W,74732W

COMMAND53 (Display control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 5 identification code
6 — 1 Display control settings
5—0
4—1
3 — 1 Extended command 3 identification code
2—1

1 RSLG1

0 RSLG1 RSLG0 Switches the screen background color level
1 0 0 NO1 RS1

0 RDLG0

0 0 1 NO2 RS2
1 1 0 NO3 RS3

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

SYnin: CVIDEO (Built-in sync separator circuit) SYNin: HSYNC
SEPin: None (internal vertical separation) SEPin: VSYNC

or

:VSYNC
SYNin: HD SYNin: CSYNC (internal vertical separation)
SEPin: CSYNC (internal vertical separation) SEPin: None

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 CTL3

0 Internal vertical separation circuit Switches the VSYNC signal input
1 External input

4 SP0SEL

0 CSYNC (sync separator output) Switches the SEPout pin output
1 Halftone output

3 PALAL4

0 Normal
1 Always use 4 fsc timing (PAL)

2 IHSEL

0 SYNin pin input signal

Switches the internal vertical separation input

1 SEPin pin input signal

signal

1 VSSEL

0 Negative polarity Switches the SEPin input polarity
1 Positive polarity

0 HSSEL

0 Negative polarity

Switches the SYNin input polarity (Invalid for

1 Positive polarity

CVIDEO input)

No. 6526-24/38

LC74731W,74732W

COMMAND60 (Outlining control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 6 identification code
6 — 1 Display control settings
5—1
4—0
3 — 0 Extended command 0 identification code
2—0
1—0

0 BRM

0 Normal mode Specifies continuous mode
1 Continuous mode

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6 BXBLV1

0 BXBLV1 BXBLV0 Character frame - black level specification
1 0 0 NO1 BK1 In line units

5 BXBLV0

0 0 1 NO2 BK2
1 1 0 NO3 BK3

4 BXWLV1

0 BXWLV1 BXWLV0 Character frame - white level specification
1 0 0 NO1 CHA1 In line units

3 BXWLV0

0 0 1 NO2 CHA2
1 1 0 NO3 CHA3

2 ATSEL

0 Reverse video, blinking Setup for the at1 and at2 function
1 Character frame specified In line units

1 BLK1

0 BLK1 BLK0 Mode Outlining mode specification
1 0 0 Normal In line units
0 0 1 Character size

0 BLK0

1

1 0 Outlining size
1 1 Full area size

No. 6526-25/38

LC74731W,74732W

COMMAND61 (Outlining control and line specification setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 6 identification code
6 — 1 Display control settings
5—1
4—0
3 — 0 Extended command 1 identification code
2—1
1—0

0 LFCUD

0 Lower lines (0 to 5 (hexadecimal)) Outlining control line specification
1 Upper lines (6 to B (hexadecimal))

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 LFCB5

0 Line 6 (line 12) setting: off Outlining line setting
1 Line 6 (line 12) setting: on The values in parentheses apply when LFCUD is 1.

4 LFCA4

0 Line 5 (line 11) setting: off
1 Line 5 (line 11) setting: on

3 LFC93

0 Line 4 (line 10) setting: off
1 Line 4 (line 10) setting: on

2 LFC82

0 Line 3 (line 9) setting: off
1 Line 3 (line 9) setting: on

1 LFC71

0 Line 2 (line 8) setting: off
1 Line 2 (line 8) setting: on

0 LFC60

0 Line 1 (line 7) setting: off
1 Line 1 (line 7) setting: on

No. 6526-26/38

LC74731W,74732W

COMMAND62 (Line spacing control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 6 identification code
6 — 1 Display control settings
5—1
4—0
3 — 1 Extended command 2 identification code
2—0
1—0

0 GRM

0 Normal mode Continuous mode specification
1 Continuous mode

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 BXC1

0 Display outside the character area Box left/right display specification
1 Forces display within the character area In line units

4 GS1

0 GS1 GS0 Mode In line units
1 0 0 Normal (character background color)
0 0 1 Full area and reverse invalid (other than ±1)

3 GS0

1

1 0 Transparent 1 (all)
1 1 Transparent 2 (other than ±1)

2 GY2

0 GY2 GY1 GY0 Line spacing In line units
10000

1 GY1

0001±1
10102
00113

1004

0 GY0

1

1015
1106
1117

No. 6526-27/38

LC74731W,74732W

COMMAND63 (Line spacing control - line specification setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 6 identification code
6 — 1 Display control settings
5—1
4—0
3 — 1 Extended command 3 identification code
2—1
1—0

0 LGYUD

0 Lower lines (0 to 5 (hexadecimal)) Line spacing control - line specification
1 Upper lines (6 to B (hexadecimal))

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 LGYB5

0 Line 6 (line 12) setting: off Line setting for line spacing control
1 Line 6 (line 12) setting: on The values in parentheses apply when LGYUD is 1.

4 LGYA4

0 Line 5 (line 11) setting: off
1 Line 5 (line 11) setting: on

3 LGY93

0 Line 4 (line 10) setting: off
1 Line 4 (line 10) setting: on

2 LGY82

0 Line 3 (line 9) setting: off
1 Line 3 (line 9) setting: on

1 LGY71

0 Line 2 (line 8) setting: off
1 Line 2 (line 8) setting: on

0 LGY60

0 Line 1 (line 7) setting: off
1 Line 1 (line 7) setting: on

No. 6526-28/38

LC74731W,74732W

COMMAND70 (Display control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 7 identification code
6 — 1 Display control settings
5—1
4—1
3 — 0 Extended command 0 identification code
2—0
1—0

0 LRM

0 Normal mode Continuous mode specification
1 Continuous mode

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 BKLC1

0 BKLC1 BKLC0

Character color and character background color:

1 0 0 NO1 BK1 black level specification

4 BKLC0

0 0 1 NO2 BK2

In line units

1 1 0 NO3 BK3

3 CHLC1

0 CHLC1 CHLC0

Character color and character background color:

1 0 0 NO1 CHA1 white level specification

2 CHLC0

0 0 1 NO2 CHA2

In line units

1 1 0 NO3 CHA3

1 RSLC2

0 RSLC1 RSLC0

Character color and character background color:

1 0 0 NO1 RS1 color level specification

0 RSLC1

0 0 1 NO2 RS2

In line units

1 1 0 NO3 RS3

No. 6526-29/38

LC74731W,74732W

COMMAND71 (Display levels - line specification setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 7 identification code
6 — 1 Display control settings
5—1
4—1
3 — 0 Extended command 1 identification code
2—1
1—0

0 LCLUD

0 Lower lines (0 to 5 (hexadecimal)) Display levels - line specification
1 Upper lines (6 to B (hexadecimal))

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 LCLB5

0 Line 6 (line 12) setting: off Display level line setting
1 Line 6 (line 12) setting: on The values in parentheses apply when LCLUD is 1.

4 LCLA4

0 Line 5 (line 11) setting: off
1 Line 5 (line 11) setting: on

3 LCL93

0 Line 4 (line 10) setting: off
1 Line 4 (line 10) setting: on

2 LCL82

0 Line 3 (line 9) setting: off
1 Line 3 (line 9) setting: on

1 LCL71

0 Line 2 (line 8) setting: off
1 Line 2 (line 8) setting: on

0 LCL60

0 Line 1 (line 7) setting: off
1 Line 1 (line 7) setting: on

No. 6526-30/38

LC74731W,74732W

COMMAND72 (Halftone - line specification setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 7 identification code
6 — 1 Display control setup
5—1
4—1
3 — 1 Extended command 2 identification code
2—0

1 LHTDAT

0 Halftone: off Halftone control
1 Halftone: on

0 LHTUD

0 Lower lines (0 to 5 (hexadecimal)) Halftone line specification
1 Upper lines (6 to B (hexadecimal))

• Second byte

Note that all registers are set to 0 when these ICs are reset by the RST pin.

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit
6—0

5 LHTB5

0 Line 6 (line 12) setting: off

Halftone line setting

1 Line 6 (line 12) setting: on

The values in parentheses apply when LHTUD is 1.

4 LHTA4

0 Line 5 (line 11) setting: off
1 Line 5 (line 11) setting: on

3 LHT93

0 Line 4 (line 10) setting: off
1 Line 4 (line 10) setting: on

2 LHT82

0 Line 3 (line 9) setting: off
1 Line 3 (line 9) setting: on

1 LHT71

0 Line 2 (line 8) setting: off
1 Line 2 (line 8) setting: on

0 LHT60

0 Line 1 (line 7) setting: off
1 Line 1 (line 7) setting: on

No. 6526-31/38

LC74731W,74732W

COMMAND73 (RGB control setup command)

• First byte

DA0 to 7 Register

Content

Notes

State Function
7 — 1 Command 7 identification code
6 — 1 Display control setup
5—1
4—1
3 — 1 Extended command 3 identification code
2—1
1—0
0—0

• Second byte

DA0 to 7 Register

Content

Notes

State Function
7 — 0 Second byte identification bit

6 DASSS

0 Normal Switches the XTALIN amplifier input
1 CLKD = CLKX Only valid when RGB output is specified.
0 Background color: off Switches the background color in RGB output mode

5 GBSEL

1 Background color: on

The background color is specified by COM4 second
byte.

4 OUTSEL

0 Switches the P9 to P12 outputs
1 RGB output switching The logical OR with the OUTMOD input.

3 HSPSW

0 Internal Sync separator used Switches the SYNin input
1 Internal Sync separator not used The logical OR with the OUTMOD input.

2 XONSS

0 Operation depends on the CTRL1 pin

Enables or disables the feedback resistor for the

1 Feedback resistor disconnected

XTALIN clock.

1 BLK02

0 BLK01 BLK00 Switches the BLKout output
1 0 0 CHA + BK + CHAB Box is always on.
0 0 1 CHA +BK only Always on when GBSEL = 1.

0 BLK01

1

1 0 CHA only
1 1 BK only

Display Screen Structure

The display consists of 12 lines of 24 characters.
Up to 288 characters can be displayed.
The number of characters that can be displayed is less than the 288 maximum when enlarged characters are displayed.
Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses.

Display Screen Structure (display memory addresses)

No. 6526-32/38

LC74731W,74732W

24 Characters

00
00
01
02
03
04
05
06
07
08
09
10
11

0
1
2
3
4
5
6
7
8

9
A
B

HEX

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17

HEX

12 Rows

Composite Video Signal Output Levels (internally generated levels)

• CVOUT Output Level Waveform (VDD2 = 5.00 V)

No. 6526-33/38

LC74731W,74732W

1H

V

BK1

VBK2

VCBL

[V]

3.303.002.80

3.152.852.65

2.872.572.37

2.582.282.08

2.512.212.01

2.171.871.67

2.021.721.52

2.001.701.50

1.871.571.37

1.731.431.23

1.671.271.07

1.401.000.80

③②①

V

SN

VCBH

VRSH3 VRSH2

VPD

VRSL1

VCHA1

VCHA2

VCHA3

VBK3

VRSH1

VRSL3

VRSL2

Output level Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V]

V

CHA1

: Character 1 2.65 2.85 3.25

V

RSH2

: Background color 2: high 2.37 2.57 2.97

V

CHA3

: Character 3 2.23 2.43 2.83

V

BK3

: Outlining: 3 2.08 2.28 2.68

V

RSH1

: Background color 1: high 2.01 2.21 2.61

V

BK2

: Outlining: 2 1.80 2.00 2.40

V

CBH

: Color burst: high 1.67 1.87 2.27

V

RSL1

: Background color 1: low 1.52 1.72 2.12

V

BK1

: Outlining: 1 1.50 1.70 2.10

V

PD

: Pedestal 1.37 1.57 1.97

V

RSL2

: Background color 2: low 1.23 1.43 1.83

V

CBL

: Color burst: low 1.07 1.27 1.67

V

SN

: Sync 0.80 1.00 1.40

BCOL01: RSL1
BCOL0: CBH
BCOL11:RSH1

No. 6526-34/38

LC74731W,74732W

YOUT Output Level Waveform (VDD2 = 5.00 V)

BCOL01: YBK1
BCOL10: YRS1
BCOL11: YRS3

[V]

③②①

1.401.000.80

1.871.571.37

2.001.701.50

2.582.282.08

3.152.852.65

3.303.002.80

1H

Y

SN

YPD

YCB

YRS2

YBK2

YBK3

YRS3

YRS1

YCHA1

YCHA2

YCHA3

YBK1

Output level Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V]

Y

CHA1

: Character 1 2.65 2.85 3.25

Y

CHA2

: Character 2 2.37 2.57 2.97

Y

CHA3

: Character 3 2.23 2.43 2.83

Y

BK3

: Outlining: 3 2.08 2.28 2.68

Y

RS3

: Background color 3 2.02 2.22 2.62

Y

RS2

: Background color 2 1.80 2.00 2.40

Y

RS1

: Background color 1 1.76 1.96 2.36

Y

BK1

: Outlining: 1 1.50 1.70 2.10

Y

CB

: Color burst 1.37 1.57 1.97

Y

PD

: Pedestal 1.37 1.57 1.97

Y

SN

: Sync 0.80 1.00 1.40

No. 6526-35/38

LC74731W,74732W

• COUT Output Level Waveform (VDD2 = 5.00 V)

BCOL01, 10, 11: CBIAS

CCBH

CBIAS

2.50 V

CCBL CRSL3

CRSL2

CRSH2

CRSL1

CRSH1

Output level Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V]

C

RSH2

: Background color 2: high 3.07 3.07 3.07

C

CBH

: Color burst: high 2.80 2.80 2.80

C

RSH1

: Background color 1: low 2.74 2.74 2.74

C

BIAS

: Bias 2.50 2.50 2.50

C

RSL1

: Background color 2: low 2.25 2.25 2.25

C

CBL

: Color burst: low 2.20 2.20 2.20

C

RSL2

: Background color 2: low 1.93 1.93 1.93

Sample Application Circuit

• Cvideo, Y/C

No. 6526-36/38

LC74731W,74732W

V

SS1

A6

D0

D1D2D3

D4

D5D6D7

CE

OE

A0

A1

A2

A3A4A5

V

DD

2

COUT

NC

CIN

CBIAS

NC

YOUT

NC

YIN

V

SS

2

CVOUT

NC

CVIN

CVCR

HFTIN

SYNIN

148

To external ROM

From external ROM

3316

3217

+5 V

Buffer

Clamp Clamp

Buffer

Clamp

Buffer

64 49

Xtal

IN

Xtal

OUT

CTRL1
OSCIN
OSCOUT

MUTE
CDLR

SYNCJDG/ROUT
CHARA/GOUT
BLANK/BOUT

IBOUT/BLKOUT
OUTMOD

CS
SIN

SCLK

A7
A8

A9
A10
A11
A12
A13
A14
A15
A16
A17

V

DD

1

RST

SEPIN

SEPOUT

No. 6526-37/38

LC74731W,74732W

• RGB

VSS1

A6

D0D1D2

D3D4D5D6D7

CE

OE

A0

A1A2A3

A4

A5

V

DD

2

COUT

NC

CIN

CBIAS

NC

YOUT

NC

YIN

V

SS

2

CVOUT

NC

CVIN

CVCR

HFTIN

SYNIN

148

To external ROM

From external ROM

3316

3217

+5 V

64 49

Xtal

IN

Xtal

OUT

CTRL1
OSCIN
OSCOUT

MUTE
CDLR

SYNCJDG/ROUT
CHARA/GOUT
BLANK/BOUT

IBOUT/BLKOUT
OUTMOD

vsync

hsync

CS
SIN

SCLK

A7
A8

A9
A10
A11
A12
A13
A14
A15
A16
A17

V

DD

1

RST

SEPIN

SEPOUT

PS No. 6526-38/38

LC74731W,74732W

This catalog provides information as of June, 2000. Specifications and information herein are subject to
change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
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