Datasheet LC74730M Datasheet (SANYO)

Page 1

Ordering number : EN*4247A

D3095HA (OT) No. 4247-1/14

Overview

The LC74730M is a CMOS LSI for on-screen display, a function that displays characters and patterns on a TV screen under microprocessor control. (The LC74730M supports the S-VCR format.) The characters displayed have an 8 × 8 dots structure and a dot interpolation function is provided. The LC74730M display 10 lines of 24 characters each.

Features

• Screen format: 10 lines × 24 characters (up to 240

characters)

• Character format: 8 (horizontal) × 8 (vertical) (inter-

polation function provided)

• Character sizes: Three horizontal sizes and 3 vertical sizes

• Number of characters in font: 64 characters

• Display start position — Horizontal: 64 positions — Vertical: 64 positions

• Blinking: In character units

• Types of blinking: Two types with approximately

1.0 sec. and 0.5 sec.

• Background color: Four background colors (in internal synchronization mode) (For the PAL-M format: 1 color; blue background)

• External control input: 8-bit serial data input format

• Built-in sync separator circuit

• Built-in synchronization recognition circuit: Recognizes whether or not external synchronizing signals are present

• Video output: NTSC and PAL-M format composite outputs, Y-C output

Package Dimensions

unit: mm

3073A-MFP30S

Preliminary

SANYO: MFP30S

[LC74730M]

LC74730M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

On-Screen Display Controller LSI

CMOS LSI

Page 2

Pin Assignment

Specifications

Absolute Maximum Ratings at Ta = 25°C

Allowable Operating Ranges at Ta = –30 to +70°C

Electrical Characteristics at Ta = –30 to +70°C, unless otherwise specified VDD1 = 5 V

No. 4247-2/14

LC74730M

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max VDD1, VDD2 VSS– 0.3 to VSS+ 7.0 V

Maximum input voltage V

max All input pins VSS– 0.3 to VDD+ 0.3 V

Maximum output voltage V

OUT

max CSYN

OUT

, SYNC

JDG

, SEP

OUT

VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max 300 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C

Parameter Symbol Conditions min typ max Unit

Supply voltage

1 VDD1 4.5 5.0 5.5 V

2 VDD2 4.5 5.0 1.27 VDD1 V

Input high-level voltage

1 RST, CS, SIN, SCLK 0.8 VDD1 VDD1 + 0.3 V

2 CTRL1 to CTRL3, SEP

0.7 VDD1 VDD1 + 0.3 V

Input low-level voltage

1 RST, CS, SIN, SCLK VSS– 0.3 0.2 VDD1 V

2 CTRL1 to CTRL3, SEP

VSS– 0.3 0.3 VDD1 V

Composite video input voltage

1 CV

2 Vp-p V

2 SYN

2 Vp-p 2.5 Vp-p V

Input voltage V

The Xtal

oscillator pin (in external clock input mode)

140 mV

Expected value (design target value)

Oscillator frequency

OSC

1 The XtalINand Xtal

OUT

oscillator pins (2fsc) 7.159 MHz

OSC

2 The OSCINand OSC

OUT

oscillator pins (LC oscillator) 5 8 12 MHz

Parameter Symbol Conditions min typ max Unit

Output off leakage current I

leak

1 C

OUT

, Y

OUT

, CV

OUT

10 µA

Input off leakage current I

leak

2 CIN, YIN, CV

10 µA

Output high-level voltage V

CSYN

OUT

, SYNC

JDG

, SEP

OUT

;

3.5 V

1 = 4.5 V, IOH= 1.0 mA

Output low-level voltage V

CSYN

OUT

, SYNC

JDG

, SEP

OUT

;

1.0 V

1 = 4.5 V, IOL= 1.0 mA

RST, CS, SIN, SCLK, CTRL1 to CTRL3, SEPIN;

1 µA

Input current

= VDD1

CTRL1 to CTRL3, OSCIN: VIN= VSS1 –1 µA

1; all outputs open, crystal: 7.159 MHz,

15 mA

Operating current drain

LC: 8 MHz

2 VDD2; VDD2 = 5 V 20 mA

Page 3

Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V

Pin Functions

No. 4247-3/14

LC74730M

Parameter Symbol Conditions min typ max Unit

Minimum input pulse width

W (SCLK)

SCLK 200 ns

W (CS)

CS pin (during the period that CS is high) 1 µs

Data setup time

SU (CS)

CS 200 ns

SU (SIN)

SIN 200 ns

Data hold time

h (CS)

CS 2 µs

h (SIN)

SIN 200 ns

One word write time

word

The 8-bit data write time 4.2 µs

The RAM data write time 1 µs

Pin No. Symbol Function Description

1 V

1 Ground Ground connection

2 Xtal

Crystal oscillator element Used to connect the external crystal and capacitors for the crystal oscillator that generates

3 Xtal

OUT

connection the internal synchronizing signal. Also used for an external clock input. (2fsc: 7.159 MHz)

4 CTRL1

Crystal oscillator input Switches between the external 2f

clock input mode and the crystal resonator driving mode.

switching Low: crystal oscillator, high: external clock input

5 CSYN

OUT

Composite synchronizing Outputs the composite synchronizing signal. Outputs the crystal oscillator clock on a reset due signal output to a low level on the RST pin. Does not output any signal on a command reset.

6 OSC

LC oscillator

Connections for the coil and capacitor that form the oscillator that generates the character

7 OSC

OUT

output dot clock.

External synchronizing signal

Outputs the judgment as to whether or not an external synchronizing signal is present. Outputs

8 SYNC

JDG

state judgment output

a high level when a synchronizing signal is present. Outputs the dot clock (LC oscillator) on a reset due to a low level on the RST pin. Does not output any signal on a command reset.

9 CS Enable input

Enable input for serial data input. Serial data input is enabled by a low level. A pull-up resistor is

built in. (This input has hysteresis characteristics.) 10 SCLK Clock input Serial data input clock input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 11 SIN Data input Serial data input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 12 V

2 Power supply Video signal level adjustment power supply. (Analog system power supply)

13 C

OUT

Color signal output Color (C) signal output 14 NC This pin must be level open or connected to ground. 15 C

Color signal input Color (C) signal input 16 CBIAS Chrominance bias output Chrominance signal bias level output 17 Y

OUT

Luminance signal output Luminance signal (Y) output 18 NC This pin must be level open or connected to ground. 19 Y

Luminance signal input Luminance signal (Y) input 20 CTRL2 NTSC/PAL-M switching input

Switches the synchronizing signal generator between NTSC and PAL-M formats. Low: NTSC, high: PAL-M

21 CV

OUT

Composite video signal output Outputs a composite video signal. 22 NC This pin must be level open or connected to ground. 23 CV

Composite video signal input Inputs a composite video signal. 24 CTRL3 SEP

input control

Controls whether the VSYNC signal is input to the SEP

input. Low: VSYNC is input,

high: VSYNC is not input.

25 SYN

Sync separator circuit input

Video signal input to the built-in sync separator circuit. (Input either a horizontal or composite synchronizing signal to this pin if the built-in sync separator circuit is not used.)

26 SEP

Sync separator circuit Adjusts the built-in sync separator circuit. (Connect a capacitor to this pin.)

adjustment (Leave this pin open if the built-in sync separator circuit is not used.) 27 SEP

OUT

Composite synchronizing Outputs the built-in sync separator circuit composite synchronizing signal.

signal output (Outputs the SYN

input signal if the built-in sync separator circuit is not used.)

Vertical synchronizing

Integrates the SEP

OUT

output signal and inputs a vertical synchronizing signal.

28 SEP

signal input

An integration circuit must be connected between this pin and the SEP

OUT

pin. This pin must

be tied to V

1 if it is not used. 29 RST Reset input The system reset input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 30 V

1 Power supply (+5 V) Power supply (+5 V: digital system power supply)

Page 4

Block Diagram

No. 4247-4/14

LC74730M

Page 5

Serial Data Input Timing

Display Control Commands

The display control commands have an 8-bit serial input format. Commands consist of a first byte, which includes the command identification code, and data in the second and following bytes. The LC74730M supports the following commands:

① COMMAND 0: Display memory (VRAM) write address setup command ② COMMAND 1: Display character data write command ③ COMMAND 2: Vertical display start position and vertical size setup command ④ COMMAND 3: Horizontal display start position and horizontal size setup command ⑤ COMMAND 4: Display control setup command ⑥ COMMAND 5: Synchronizing signal control setup command

Display Control Command Table

The command identification code in a first byte is retained until the next first byte is written. However, if a display character data write command (COMMAND 1) is written, the LC74730M locks in display character data write mode, and the first byte cannot be overwritten. The command state is reset to the COMMAND 0 state (display memory address setup mode) when the CS pin is set high.

No. 4247-5/14

LC74730M

First byte Second byte

Command

Command identification code

Data Data

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

COMMAND 0 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 Set write address

COMMAND 1 1 0 0 1 0 0 0 0 at 0 c5 c4 c3 c2 c1 c0 Write character

COMMAND 2

1 0 1 0 VS VS VS VS 0 0 VP VP VP VP VP VP

Set vertical display start position and

21 20 11 10 5 4 3 2 1 0

vertical character size COMMAND 3

1 0 1 1 HS HS HS HS 0 0 HP HP HP HP HP HP

Set horizontal display start position

21 20 11 10 5 4 3 2 1 0

and horizontal character size COMMAND 4 1 1 0 0 TST CB OSC SYS 0 0 NON EG BK BK RV DSP

Display control MOD STP RST 1 0 ON COMMAND 5 1 1 0 1 PH PH BCL INT 0 0 0 0 SN SN SN SN

Synchronizing signal control 1 0 3 2 1 0

Page 6

① COMMAND 0 (Display memory write address setup command)

First byte

Second byte

Note: All these registers are set to 0 by a reset due to the RST pin.

② COMMAND 1 (Display character data write setup command)

First byte

No. 4247-6/14

LC74730M

DA0 to DA7 Register name

State Function

Note

7 — 1 6 — 0

Command 0 identification code

5 — 0 Set the display memory write address. 4 — 0

3 V3

0 1

2 V2

0 1

Display memory line address (0 to 9 hexadecimal)

1 V1

0 1

0 V0

0 1

DA0 to DA7 Register name

State Function

Note

7 — 0 Second byte identification bit 6 — 0 5 — 0

4 H4

0 1

3 H3

0 1

2 H2

Display memory character address (0 to 17 hexadecimal)

1 H1

0 1

0 H0

0 1

DA0 to DA7 Register name

State Function

Note

7 — 1 6 — 0

Command 1 identification code

5 — 0

Sets up a display character data write operation

4 — 1 3 — 0 2 — 0 1 — 0 0 — 0

When this command is issued, the LC74730M is locked in display character data write mode until the CS pin goes high.

Page 7

Second byte

Note: All these registers are set to 0 by a reset due to the RST pin.

③ COMMAND 2 (Vertical display start position and vertical size setup command)

First byte

No. 4247-7/14

LC74730M

DA0 to DA7 Register name

State Function

Note

7 at

0 Character attributes off 1 Character attributes on

6 — 0

5 c5

0 1

4 c4

0 1

3 c3

0 1

Character code (00 to 3F hexadecimal)

2 c2

0 1

1 c1

0 1

0 c0

0 1

DA0 to DA7 Register name

State Function

Note

7 — 1 6 — 0

Command 2 identification code

5 — 1

Sets up the vertical display position and the character size

4 — 0

in the vertical direction.

3 VS21

0 1

Vertical character size for the second line

2 VS20

0 1

1 VS11

0 1

Vertical character size for the first line

0 VS10

0 1

VS21

VS20

0 1

0 1 H per dot 2 H per dot 1 3 H per dot 1 H per dot

VS11

VS10

0 1

0 1 H per dot 2 H per dot 1 3 H per dot 1 H per dot

Page 8

Second byte

Note: All these registers are set to 0 by a reset due to the RST pin.

④ COMMAND 3 (Horizontal display start position and horizontal size setup command)

First byte

Second byte

Note: All these registers are set to 0 by a reset due to the RST pin.

No. 4247-8/14

LC74730M

DA0 to DA7 Register name

State Function

Note

7 — 0 Second byte identification bit 6 — 0

HP5

(MSB)

4 HP4

0 1

3 HP3

0 1

2 HP2

0 1

1 HP1

0 1

HP0

(LSB)

The horizontal display start position is specified by the 6 bits HP0 to HP5.

The weight of the low-order bit is 2 Tc.

If HS is the horizontal start position then:

HS = Tc × (2Σ 2nHPn)

n = 0

Where Tc is a single period of the LC oscillator connected the OSC

and OSC

OUT

pins.

DA0 to DA7 Register name

State Function

Note

7 — 0 Second byte identification bit 6 — 0

VP5

(MSB)

4 VP4

0 1

3 VP3

0 1

2 VP2

0 1

1 VP1

0 1

VP0

(LSB)

The vertical display start position is specified by the 6 bits VP0 to VP5.

The weight of the low-order bit is 2 H.

If VS is the vertical display start position then:

VS = H × (2Σ 2nVPn)

n = 0

Where H is horizontal period pulse period.

DA0 to DA7 Register name

State Function

Note

7 — 1 6 — 0

Command 3 identification code

5 — 1

Sets up the horizontal display position and the character size

4 — 1

in the horizontal direction.

3 HS21

0 1

Horizontal character size for the

2 HS20

second line

1 HS11

0 1

Horizontal character size for the first line

0 HS10

0 1

HS21

HS20

0 1

0 1 Tc per dot 2 Tc per dot 1 3 Tc per dot 1 Tc per dot

HS11

HS10

0 1

0 1 Tc per dot 2 Tc per dot 1 3 Tc per dot 1 Tc per dot

Page 9

⑤ COMMAND 4 (Display control setup command)

First byte

Second byte

Note: All these registers are set to 0 by a reset due to the RST pin.

No. 4247-9/14

LC74730M

DA0 to DA7 Register name

State Function

Note

7 — 0 Second byte identification code 6 — 0

5 NON

0 Interlace (262.5 H per field)

Switches between interlaced and

1 Non-interlaced (263 H per field)

non-interlaced display

4 EG

0 Border off 1 Border on

3 BK1

0 Blinking period: about 0.5 s

Switches the blinking period

1 Blinking period: about 1 s 0 Blinking off

Blinking during reversed video character

2 BK0

display switches the character display

1 Blinking on

between normal display and reversed video display.

1 RV

0 Reverse video character display off 1 Reverse video character display on

0 DSPON

0 Character display off 1 Character display on

DA0 to DA7 Register name

State Function

Note

7 — 1 6 — 1

Command 4 identification code

5 — 0 Sets up the display control state. 4 — 0

3 TSTMOD

0 Normal operating mode

Must be set to 0.

1 Test mode

2 CB

0 Output the color burst signal.

Valid only when BCL is high.

1 Stop color burst signal output.

1 OSCSTP

0 Does not stop the crystal and LC oscillators.

Valid in external synchronization mode

1 Stops the crystal and LC oscillators.

when character display is off.

0 SYSRST

Reset occurs when the CS pin is low, and

1 Resets all registers and turns off display.

the reset is cleared when CS goes high.

Page 10

⑥ COMMAND 5 (Synchronizing signal control setup command)

First byte

Second byte

Note: All these registers are set to 0 by a reset due to the RST pin.

Display Screen Organization

The display screen consists of 10 lines of 24 characters each. Thus the maximum number of characters that can be displayed is 240 characters. However, the maximum number of characters that can be displayed may be fewer than 240 when characters are enlarged. The display memory address consists of a line address (with values from 0 to 9 decimal), and a column (character position) address (with values from 0 to 23 decimal).

No. 4247-10/14

LC74730M

DA0 to DA7 Register name

State Function

Note

7 — 0 Second byte identification bit 6 — 0 5 — 0 4 — 0

3 SN3

0 1

2 SN2

0 1

1 SN1

0 1

0 SN0

0 1

External synchronizing signal detection control

SN3 SN2 SN1 SN0 Number of times HSYNC detected

0 0 0 0 Not detected 0 0 0 1 16 times 0 0 1 0 32 times 0 1 0 0 64 times 1 0 0 0 128 times

DA0 to DA7 Register name

State Function

Note

7 — 1 6 — 1

Command 5 identification code

5 — 0

Sets up control of the synchronizing signals

4 — 1

3 PH1

2 PH0

1 BCL

0 Background color displayed.

Valid only in internal synchronization

1 No background color (only the background level is set).

mode

0 INT

0 External synchronization

Switches between internal and external

1 Internal synchronization

synchronization.

Sets the background color (one of 4 colors). There is only one background color (blue) in PAL-M mode.

PHASE1 PHASE0 Background color (phase)

0 0 π/2 0 1 π 1 0 3π/2 1 1 In phase

Page 11

Display Screen Organization (Display memory address)

No. 4247-11/14

LC74730M

Page 12

Composite Video Signal Output Levels (internally generated levels)

Note: VDD2 = 5.000 V

No. 4247-12/14

LC74730M

Output level (IRE) Output voltage (VDC)

100 3.000

90 2.857 46 2.228 20 1.857 10 1.714

8 1.685

0 1.571 –20 1.285 –40 1.000

Page 13

Video Signal Output Levels (Y (luminance) signal: internally generated levels)

Note: VDD2 = 5.000 V

No. 4247-13/14

LC74730M

Output level (IRE) Output voltage (VDC)

100 3.000

90 2.857 28 1.971 20 1.857

8 1.685

0 1.571 –40 1.000

Page 14

No. 4247-14/14

LC74730M

Video Signal Output Levels (chrominance signal: internally generated levels)

Note: VDD2 = 5.000 V

This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

Output level (IRE) Output voltage (VDC)

40 3.071 20 2.786

0 2.500 –20 2.214 –40 1.928