Datasheet LC72709W, LC72709E Datasheet (SANYO)

Overview

The LC72709E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. This IC includes a built-in bandpass filter
that extracts the DARC signal from the FM baseband
signal. Since this IC supports all of the FM multiplex
broadcast frame structures (methods A, A', B, and C) from
the ITU-R recommendations, it is optimal for use in radios
for worldwide use that support FM multiplex reception.

Functions

• SCF-based adjustment-free 76-kHz bandpass filter

• Support for the FM multiplex broadcast frame structures
(methods A, B, and C) using serial data control.

• MSK delay detection circuit based on a 1T delay

• Error correction function based on a 2T delay (in the
MSK detector stage)

• Digital PLL based clock regeneration circuit

• Shift-register type 1T and 2T delay circuits

• Block and frame synchronization detection circuit

• Function for setting the number of allowable BIC errors,
the number of synchronization protection.

• Error correction using (272, 190) codes

• Layer 4 CRC code checking circuit

• On-chip frame memory and memory control circuit for
vertical correction

• 7.2-MHz crystal oscillator circuit

• Two power saving functions (Standby and EC stop)

Package Dimensions

unit: mm

3148-QIP44MA

unit: mm

3190-SQFP64

CMOS IC

71598RM (OT) No. 5876-1/16

SANYO: QIP44MA

[LC72709E]

SANYO: SQFP64

[LC72709W]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

FM Multiplex Reception IC for Mobile Systems

LC72709E, 72709W

Ordering number : EN5876

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

No. 5876-2/16

LC72709E, 72709W

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max –0.3 to +7.0 V

Input voltage

V

IN

1 CE, CL, DI, RST, STNBY –0.3 to +7.0 V

V

IN

2 Pins other than VIN1 –0.3 to VDD+0.3 V

Output voltage

V

OUT

1 DO –0.3 to +7.0 V

V

OUT

2 Pins other than V

OUT

1 –0.3 to VDD+0.3 V

Output current I

OUT

BLOCK, FLOCK, BCK, FCK, DO 0 to 4.0 mA

Allowable power dissipation Pd max

LC72709E 250 mW

LC72709W 200 mW
Operating temperature Topr Ta ≤ 85°C –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DD

4.5 5.5 V

Input high-level voltage V

IH

CL, CE, DI, RST, STNBY 0.7 V

DD

5.5 V

Input low-level voltage V

IL

CL, CE, DI, RST, STNBY V

SS

0.3 V

DD

V

Oscillator frequency F

OSC

This IC operates at frequencies within a

7.2 MHz

±250 ppm precision

Input sensitivity V

XI

With a capacitance-coupled sine wave input

400 1500 mVrms

to X

IN

Input amplitude V

MPX

MPXIN, 100% modulation composite 150 500 mVrms

[Serial I/O*]

Clock low-level time t

CL

CL 0.7 µs

Clock high-level time t

CH

CL 0.7 µs

Data setup time t

SU

CL, DI 0.7 µs

Data hold time t

HD

CL, DI 0.7 µs

CE wait time t

EL

CL, CE 0.7 µs

CE setup time t

ES

CL, CE 0.7 µs

CE hold time t

EH

CL, CE 0.7 µs

Data latch change time t

LC

CE 0.7 µs

Data output time t

DD0

DO, CL 277 555 ns

Layer 4 CRC change time t

CRC

CRC4, CL 0.7 µs

Allowable Operating Ranges at Ta = –40 to +80°C, VSS= 0 V

Note *: See the serial data timing chart.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Output high-level voltage V

OH

1

I

O

= 2 mA, BCK, FCK, BLOCK, FLOCK,

V

DD

– 0.4 V

CRC4, INT, CLK16, DATA, IC1, IC2

Output low-level voltage

V

OL

1 IO= 2 mA, applies to the same pins as VOH1 0.4 V

V

OL

2 IO= 2 mA, DO 0.4 V

Input high-level current

I

IH

1 VIN= 5.5 V, CE, CL, DI, RST, STNBY 1.0 µA

I

IH

2 VIN= VDDD, input pins other than IIH1 1.0 µA

Input low-level current I

IL

VIN= VSSD, CL, CE, DI, RST, STNBY,

–1.0 µA

TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST

Input resistance R

MPX

MPXIN-Vssa, f = 0 to 100 kHz 50 kΩ

Reference supply voltage output V

REFVREF

, Vdda = 5 V 2.5 V

Bandpass filter center frequency F

C

FLOOUT 76.0 kHz

–3 dB bandwidth F

BW

FLOUT 19.0 kHz

In-band delay time difference D

GD

FLOUT ±5 µs

Gain Gain MPXIN-FLOUT, f = 76 kHz 20 dB

ATT1 FLOUT, f = 50 kHz 25 dB

Stop band attenuation

ATT2 FLOUT, f = 100 kHz 15 dB
ATT3 FLOUT, f = 30 kHz 50 dB
ATT4 FLOUT, f = 150 kHz 50 dB

Electrical Characteristics at VDD= 4.5 to 5.5 V, in the allowable operating ranges

Continued on next page.

No. 5876-3/16

LC72709E, 72709W

Block Diagram

Pin Assignments

1T delay

Synchronization

regeneration

PN

decoding

Output control

(CPU interface)

Antialiasing

filter

Timing control

Memory array

Error

correction

Layer 2 CRC

Data

Address

Layer 4 CRC

2T delay

Clock

regeneration

MSK

correction

Parameter Symbol Conditions

Ratings

Unit

min typ max

Output off leakage current I

OFFVO

= VDDD, DO 5 µA

Hysteresis voltage V

HIS

CL, CE, DI, RST, STNBY 0.1 V

DD

V

Internal feedback resistor R

f

XIN, X

OUT

1.0 MΩ

Current drain I

DD

18 25 mA

Continued from preceding page.

No. 5876-4/16

LC72709E, 72709W

Pin Descriptions

Pin No.

Pin Name Function I/O Circuit type

LC72709E LC72709W

CL
CE

DI

RST

STNBY

TEST

28
29
30
33
32
40

CCB serial interface Clock input

Data control input

Data input
System reset input (active low)
Standby mode (active high)
Test (Must be connected to ground during normal operation.)

Input

Input

TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7

TP8
TPC1
TPC2

TOSEL1
TOSEL2

9
12
13
14
15
16
17
18
19
41
42

5

6

Must be connected to either V

DD

or VSS.

Output

Output

CLK16

DATA

FCK

BCK
FLOCK
BLOCK

CRC4

INT

7

8
20
21
22
25
26
27

Clock regeneration monitor
Demodulated data monitor
Frame start signal output
Block start signal output
Outputs a high level during frame synchronization.
Outputs a high level during block synchronization.
Layer 4 CRCC check result output

External CPU interrupt signal
IC1
IC2

3
4

Internal connections. These pins must be left open.

DO31 Data output used by the CCB serial interface

Input

Output

XIN

XOUT

44

1

System clock generation crystal oscillator element

connections

InputMPXIN36 Baseband (multiplex) signal input

OutputFLOUT38 Subcarrier output (76-kHz filter output)

InputCIN39 Subcarrier input (comparator input)

40
42
43
47
46
58
13
18
19
20
22
23
24
26
27
59
61

7

9
10
11
29
30
31
36
38
39

5

6

44

63

2

52

55

57

Continued on next page.

No. 5876-5/16

LC72709E, 72709W

Continued from preceding page.

Pin No.

Pin Name Function I/O Circuit type

LC72709E LC72709W

Output

VDDA
V

SS

A

V

DD

D

V

SS

D

54
50

3, 14, 35,

15, 34, 62

37
34

2, 10, 24

11,23, 43

Analog system power supply
Analog system ground
Digital system power supply (4.5 to 5.5 V)
Digital system ground

—
—
—
—

NC

1, 4, 8,
12, 16,
17, 21,
25, 28,
32, 33,
37, 41,
45, 48,
49, 53,
56, 60,

64

– Not connection

Note: A capacitor of at least 2000 pF must be inserted between VDDD and VSSD when using this IC.

V

REF

35 Reference voltage output (Vdda/2)51

Data I/O Techniques

• CCB Technique
Sanyo audio ICs input and output data using the Sanyo CCB (computer control bus) standard, which is a serial bus
format. This IC uses an 8-bit address CCB and uses the following addresses.

• Data Input Timing

I/O mode

Address

Function

B0 B1 B2 B3 A0 A1 A2 A3

Input 0 1 0 1 1 1 1 1 16-bit control data input

Output 1 1 0 1 1 1 1 1 Data output for the input clock (CL)

Input 0 0 1 1 1 1 1 1 Data input (in 8-bit units) for the layer 4 CRC check circuit

Internal data latching

A10595

• Data Output Timing

A10596

Note:The DO pin is normally left open.

Since the DO pin is an n-channel open drain pin, the time required for the data to change from the low level to the high level depends on the value of
the pull-up resistor.

No. 5876-6/16

LC72709E, 72709W

• Layer 4 CRC Data Input Timing

Serial Control Data Input Settings

The input data consists of 16 bits (DI0 to DI15). The upper 8 bits (DI8 to DI15) are the control address and the lower 8
bits (DI0 to DI7) are the input data. Bits DI12 to DI15 are ignored.

• Number of Allowed BIC Errors
This IC’s synchronization circuit operates by recognizing a 16-bit BIC code. The number of allowed errors is the
number of allowed error bits in the 16 bits used for BIC recognition. This data item allows the forward protection mode
(used when synchronized) and the backward protection mode (used when not synchronized) values to be set
independently. The default value is to allow up to 2 error bits in both the forward and backward directions. We
recommend setting the backward protection mode number of allowable BIC errors to 1 or 0 if the block
synchronization recognition output (the BLOCK pin) is used to recognize the presence or absence of FM multiplex
data.

• Block Synchronization Error Protection Count
The synchronization protection count can be set independently in the forward and backward directions. The protection
count conditions are as follows.
— Backward protection (unsynchronized, BLOCK = low)

When the timing of the IC’s internal synchronization free-running counter matches that of the received BIC, the
protection count is incremented by 1. Similarly, if the IC internal counter and the received BIC do not match, the
counter is cleared to 0. The count timing is the timing of the IC internal counter.

— Forward protection (synchronized, BLOCK = high)

Operation is the opposite of the backward case, namely, the protection count is incremented when the timing of the
IC’s internal synchronization free-running counter does not match that of the received BIC, and the protection
count is cleared to zero when the timing matches.

Figure 1 shows the protection counter when both the forward and backward protection counts are set to 3.
This IC defines the protection counter value to be 1 at the point where a match or a mismatch occurs between the IC
internal timing and the received BIC timing. For example, a backward protection count of 2 corresponds to the case
where the IC internal timing and the received BIC timing match two times consecutively. To set the protection data to
new values, applications must send data in which 1 has been subtracted from the desired values, e.g. to set up protection
counts of 3 as shown in figure 1, applications must send the value 22H. Similarly, if the value set is 00, due to the

CRC4 pin output

Note: The N items are 8-bit units.

CRC4 output after N items transferred

Register

Address

Data

Default

DI11 DI10 DI9 DI8 setting

Number of allowable BIC errors 0 0 0 0

Upper 4 bits Allowed error bits backward 2
Lower 4 bits Allowed error bits forward 2

Number of block error protection states 0 0 0 1

Upper 4 bits Block backward protection 1
Lower 4 bits Block forward protection 7

Number of frame error protection states 0 0 1 0

Upper 4 bits Frame backward protection 1
Lower 4 bits Frame forward protection 7

Control register 0 0 1 1 See the control register description on page 8.

Continued on next page.

definition, the protection counts for both the forward and backward directions will be set to 1. However, from an
operation standpoint, this corresponds to operation equivalent to there being no protection circuit. The default values are
a forward protection count of 8 and a backward protection count of 2. We recommend resetting the block synchronization
backward protection count to a value stricter than the default, e.g. to a value of 3 or more as opposed to the default of 2, if
the block synchronization recognition output (the BLOCK pin, pin 23) is used to recognize the presence or absence of
FM multiplex data.

• Frame Synchronization Error Protection Count

This IC detects the four unique BIC inflection points that exist in a single frame, and increments or decrements the
protection counter depending on whether or not the IC internal frame synchronization counter matches. The data values
are set in the same way as those for the block synchronization protection count are set, namely data in which 1 has been
subtracted from the desired protection count must be transferred. The frame synchronization default values are 8 for
forward protection and 2 for backward protection.

• Control Registers

These registers are used to set the IC operating mode. These are described later.

• Notes

— The address bits DI12 to DI15 are ignored.
— Addresses other than those listed above (for example location 0110) are special addresses used for test mode and

other special IC functions. Do not set these locations.

— The default values are the values reloaded into the internal registers when a reset signal (RST) is received. These

values are the recommended values for normal operation, and normally do not need to be modified. If only the

default values are used, there is no need to provide data transfer routines in the external CPU.

Layer 4 CRC Check Circuit

This is a function provided for data group error detection, i.e. layer 4 CRC. After the stipulated number of bytes of data
group data and a 16-bit CRC error check word are transferred, the CRC4 pin outputs a high level if there were no errors.
The CRC4 pin outputs a high level if all the bits in the IC internal CRC check register were 0. When using this function
to perform the layer 4 CRC check, the IC internal CRC check register must be initialized before a single data group data
unit is transferred. This register is initialized by sending bit 7 of the control register. Note that since this flag is not
automatically reset to 0, the application must return it to 0 before transferring layer 4 CRC check data. If there were no
errors in any of the received data groups, the CRC register will always be all zeros after the CRC check of a single data
group. Therefore, the above control register initialization will not be necessary as long as there are no errors in the layer 4
CRC. The data length of the transferred data group data is in unit of 8 bits. Also note that while there is no upper limit on
the amount of data transferred in a single operation, data transfers can also be divided into multiple transfer operations.

No. 5876-7/16

LC72709E, 72709W

Received data

Synchronization
counter BIC position

Reset

: Both forward and backward protection counts are 3.

Figure 1 Block Synchronization Protection Operation

(forward → backward → forward)

Block

Continued from preceding page.

No. 5876-8/16

LC72709E, 72709W

Detailed Descriptions

• VEC HALT

Setting this flag stops all IC operations related to vertical and second horizontal correction. Data output is limited to
data following the first horizontal correction.

• EC STOP

This flag stops all operations (including RAM access) related to error correction and all data output operations. While
all IC operations are stopped in standby mode, MSK demodulation, the synchronization circuit, the serial data input
circuit, and the layer 4 CRC circuit continue to operate in this mode.

• SYNC RST

Clears the synchronization state and the synchronization protection state in the synchronization block and sets that
block to the unsynchronized state. This allows quick frame synchronization pull in when, during receiver tuning
operations, the frame period of the new reception data after station selection is displaced. While this flag is used for
initialization of synchronization related circuits, it does not initialize the number of allowed BIC errors, the block
synchronization forward and backward protection settings, and the registers of frame synchronization forward and
backward protection settings. During the synchronization block reset, the INT signal is not output and the DO pin
outputs a high level (high impedance). Since this flag is not automatically reset to 0, applications must send data again
to set it to 0.

• INT MOVE

The data output by this IC is fully corrected, and only data received during both block and frame synchronization is
output. (The layer 2 CRC check is included.) This flag must be set to acquire all data in the same manner as the
LC72700.

• DO MOVE

In the LC72700, the DO pin output was linked to and changed with the INT signal so that it could be used in place of
the INT CPU interrupt signal. Set this flag to use that function.

• RTIB

In the method A frame structure in the ITU-R recommendations, a total of 12 data blocks have been inserted in the
parity data area, in which the 82 consecutive blocks of parity information are held. This flag must be set if this IC is
used in systems that do not have these real-time information blocks (RTIB). Note that if the state of this flag is
changed, frame synchronization will be held for the time corresponding to the forward protection count and then will
switch to the unsynchronized state. Applications must use the SYNC RST flag to reset the synchronization circuit to
reestablish frame synchronization more quickly.

Control Register

Control register

FRAME RTIB VEC HALT EC STOP SYNC RST INT MOVE DO MOVE CRC4 RST

0 1 2 3 4 5 6 7

Bit Function Initial value

0

FRAME L Method-B

L

(Frame selection) H Method-A

1

RTIB L Real-time information blocks present (When method A is selected)

L

(RTIB presence) H No real-time information blocks present (When method A is selected)

2

VEC HALT L Vertical correction and second horizontal correction: enabled

L

(Vertical error correction stop) H Vertical correction and second horizontal correction: disabled

3

EC STOP L All functions operate

L

(Error correction stop) H Only the MSK detection and synchronization regeneration circuits operate

4

SYNC RST L

L

(Synchronization block reset) H Only the synchronization circuit is reset

5

INT MOVE L

Only the correction complete, layer 2 CRC complete, and data received while synchronized are output.

L

(INT type) H All data is output. (Operation identical to that of the LC72700)

6

DO MOVE L The high-level (high-impedance) state is held at times other than data output

L

(DO pin operation) H The DO pin changes with the INT pin. (Operation identical to that of the LC72700)

7

CRC4 RST L

L

(Layer 4 CRC) H The layer 4 CRC circuit is reset to its initial state.

Structure of the Output Data

• The output data consists of a total of 288 bits (36 bytes). The first two bytes are status information, and data is output

in a single data block unit.

• CNT1 and CNT2 are output LSB first.

• The corrected data is output starting with the first bit in the data block.

• BIC codes are not output.
Note: The CPU can easily select data by discriminating the status information at first during data readout. Data that is

determined to be unnecessary can be immediately cancelled without reading it out. (The CPU can simply ignore
the data until the next interrupt arrives.)
For example, the CPU can also read out just the first 22 bytes (the data block section) of the corrected data, and
does not have to read out the unrequired 12 bytes (the layer 2 CRC and parity data).

Notes:

• CRC indicates the layer 2 CRC check when the ERR flag is 1.

• The CRC4 result is the data immediately preceding the point when the CCB output address (#FB) was input and CE

was high.

• The HEAD flag is valid only for horizontal correction data output, i.e. when VH is 0.

• See page 12 for details on VH blanking in the horizontal and vertical directions.

• The RTIB flag is valid only for method A.

BLN0 to BLN7: Indicates either the block number for the output data or the parity block number. The data blocks in

a single frame are numbered 0 to 189, and the parity blocks are numbered 0 to 81.
Parity block data is not output for post-vertical correction output.

No. 5876-9/16

LC72709E, 72709W

• CNT1

• CNT2

CNT1 (8 bits) CNT2 (8 bits) Corrected data 176 bits CRC (14 bits) Parity (82 bits)

Indicates the presence of real-time information blocks
Layer 4 CRC shift register: Not all zeros.

Layer 4 CRC shift register: All zeros (no errors)

Data for the first block is being output (block No.0)
Data block data

Parity block data
Error correction and layer 2 CRC check OK

Either an uncorrectable error or the layer 2CRC check NG
Indicates data received with frame synchronization not achieved

Indicates data received with frame synchronization achieved

Indicates data received with block synchronization not achieved

Indicates data received with block synchronization achieved
Output with horizontal correction only

Output with horizontal and vertical corrections

Operation During Reset and in Standby Mode

• The Reset Signal

A reset operation is performed by holding the RST pin input level under VIL for at least 300 ns when the power-supply
voltage (VDD) is over 3.4 V. (See the figure below.) Applications must apply a reset when power is first applied or
when power is reapplied.

• Pin Outputs During a Reset (LC72709E)

Low-level outputs: CLK16 (7), DATA (8), FCK (20), BCK (21), FLOCK (22), BLOCK (25), CRC4 (26), IC1 (3), IC2 (4)
High-level outputs: INT (27), XOUT (1)
Open: DO (31)

• Pin Outputs During a Reset (LC72709W)

Low-level outputs: CLK16 (10), DATA (11), FCK (28), BCK (30), FLOCK (31), BLOCK (36), CRC4 (38), IC1 (4),
IC2 (6)
High-level outputs: INT (39), XOUT (2)
Open: DO (45)

• Reset Operating Range

The output pin states according to the reset signal are stipulated by item “Pin outputs during a reset” above. The IC
internal flip-flops are all reset. Although the delay shift registers are also reset, the memory array is not influenced.
However, since memory refresh operation stops, data cannot be retained. The crystal oscillator circuit does not stop.

• Data Input After a Reset

After a reset completes and at least one full clock cycle (about 278 ns at 3.6 MHz, this is the IC’s main clock) has
elapsed, the serial input control circuit will be able to operate and accept data.

• Standby Mode

The IC can be set to standby mode by setting the STNBY pin high. Since all IC operations are stopped in this mode,
this produces a state essentially equivalent to the power off state. (Note that after standby mode has been cleared, a wait
period is required until the crystal oscillator circuit is operating stably.) The pin output states in standby mode are
identical to the states after a reset as described in item “Pin outputs during a reset” above.

Notes on Post Error Correction Output Data

• The received data is error corrected using (272, 190) codes in single block (272 bits) units. An error check using the

layer 2 CRC is also performed. After error correction, the IC prepares for transfer of the data to the CPU and outputs
the INT signal. This is referred to as horizontal correction output.

• However, the INT signal is not output at this time if the corresponding output data does not meet all of the following

three conditions.
— Error correction completed and it passed the layer 2 CRC check.
— The data was received while both block and frame synchronization were established.
— The data was packet data.
Note that all received packet data can be acquired by setting bit 5 (INT) in the control register.

• If the data could not be corrected by the horizontal correction system, correction using product codes is performed in frame

units. This is called vertical correction. The data that can be acquired at the output of the vertical correction is the following.
— Data that was fully corrected in horizontal correction is not output.
— Packet data that could not be corrected by horizontal correction but that was fully corrected by vertical correction is output.

— Packet data that could not be corrected by either horizontal or vertical correction is not output.
Note that, as is the case for horizontal correction output, all received packet data can be acquired by setting bit 5 (INT) in the
control register. However, the parity packet data corrected by vertical correction cannot be output even if this flag bit is set.

No. 5876-10/16

LC72709E, 72709W

VDDvoltage

• To prevent unnecessary error correction, the vertical correction is not applied to packets that were fully corrected by
horizontal correction or to packets that had no errors.

• Vertical correction is executed when all packet data in the object data was received while frame synchronization was
established and not all of the packet (block) data was corrected by horizontal correction. Vertical correction is not
performed if a whole frame of data with no errors is received, or if the frame was not synchronized. Also, the
corresponding post-vertical correction output data is not output.

• All data can be output, regardless of the correction complete/incomplete, synchronized/unsynchronized reception,
data/packet status or other conditions by setting bit 5 (INT) in the control register to 1. However, there also are cases
where the vertical correction output data is not output as described above.

CPU Interface Basic Restrictions

To save internal memory, this IC uses the smallest possible output buffer. Since the data that the IC receives is written to
memory without any breaks, if data readout is delayed post-correction data that should be read out will be overwritten by
the next data to be output. The output timings in this IC for post-correction (horizontal and vertical) data are stipulated as
follows.

• When preparation of the output data has completed, the IC issues a transfer request by setting the INT pin low.

• For data output, there are periods in which only horizontal data can be output and periods in which both horizontal data
and vertical data can be output.

• Data transfers must be completed within about 9 ms after the INT pin goes low. For periods in which only post­horizontal correction data can be output, data can be transferred over a period of about 18 ms. Even if the CPU is in the
midst of a read operation, the next output data will be written to the output buffer after the specified period elapses.

• Only one block of data can be read for a single transfer request (INT) for both vertical and horizontal correction. After
vertical correction processing completes, the post-vertical correction data is output in order starting with block number
1, and the parity block data is not output.

Figure 2 External Interface Basic Timing

Notes on Data Output Timing (The relationship with the received data)

Figure 3 shows the timing relationship between the received data and the interrupt control signal INT. However, the
delay component relative to the actually received signal due to the demodulation operations in the MSK demodulation
block is ignored. Block synchronization is established by recognizing the BIC code. As shown in figure 3, the data for the
nth packet can be output during the reception of the next packet, packet number n + 1.

Figure 4 shows the output timing for the post-vertical correction data. Vertical correction is executed when the data for a
whole frame is stored in memory, frame synchronization is established, and furthermore horizontal correction was not
able to correct all the packet data. The timing for the start of vertical correction execution is the head of the frame. During
reception of packets 1 to 28 in the nth frame, horizontal correction is performed on each packet, data is passed to the
CPU, and the remaining unused processing time during that interval is used to apply vertical correction to the data from
the previous frame (frame n – 1). The post-vertical correction data (190 blocks of data) is output in order starting when
the 29th packet (block) is received at the rate of one block of output data for every block received. Of the data in the FM
multiplex broadcast frame structure, only the data in the data blocks is output, and the 190th block (the last data block) is
output while the 218th block is being received. As discussed previously (page 11), of the post-vertical correction output
data, the packet data for which horizontal correction completed fully is not output (the INT signal is not issued).
However, it is not the case that the vertical output is speeded up by the amount of the packet data that is not output. For
example, if data packets 1 to 100 were fully corrected in horizontal correction, the point that the 101st post-vertical
correction packet data is output will not be the reception position block number 29 in figure 4, but the reception position
of packet data number 129.

No. 5876-11/16

LC72709E, 72709W

Only horizontal
data output

Horizontal data

output period

Period when

data cannot be

guaranteed

Horizontal data

output period

Vertical data output period

Horizontal and
vertical data output

No. 5876-12/16

LC72709E, 72709W

Figure 3 Timing of Data Reception and Block Synchronization Data Output

Figure 4 Post-Vertical Correction Data Output Timing

Packet (N – 1)

Reception data

Packet data N

Packet (N + 1)

Output period for packet data (N – 1)

Period that data cannot be
guaranteed

Output of packet data N

Frame N – 1

Reception block
number

Frame N

Output period for the post-vertical
correction data from the previous frame

Notes on Output Data Selection During Tuning (Provided for reference purposes.)

A tuning system is required in an FM multiplex broadcast reception system. However, applications must perform the
following processing if it is unacceptable for the IC to output data for the previous station after tuning a new station.

• Set bit 4 (SYNC RST) in the control register during tuning to set the synchronization circuit to the unsynchronized state.

• If bit 5 (INT) in the control register is enabled, do not use the post-vertical correction output (data for which bit 7 in the
status flags CNT1 is 1) until frame synchronization is re-established.

Of the DARC FM multiplex processing, this IC performs the processing through error correction (layer 2) without
requiring any special control operations. The IC itself is not able to recognize whether the content of the received data
has changed or whether the system has been tuned to another station. Therefore the application system must use the
above procedure to command the IC not to output the old data and only to output the new data. The synchronization
relationship between the stations is also problematic; although it is rare that the frames of the previous station and the
next station would be synchronized, applications must also perform the processing described above to cancel the frame
synchronization forward protection period.

Differences in Data Output between this IC and the LC72700E (Provided for reference purposes.)

The LC72700E provided all data that could be provided to the microcontroller in the later stages of the system, and was
designed so that the microcontroller was required to decide whether to accept or discard the data by checking the status
output. For example, a received data packet could be output as post-horizontal correction data and then again, a few
seconds later, could be output as post-vertical correction data. Data with no errors, or data that could be corrected by
horizontal correction was output twice as identical data. This IC implements the conditions shown on page 12 (in “Notes

on Post Error Correction Output Data”) concerning data with no errors. Stated simply, this IC does not output data
unnecessarily. For example, the INT signal will not be output for data from a received station that is not broadcasting
multiplexed data. Also, under good reception conditions where there are no errors, there will be no post-vertical
correction output and the INT signal period will be 18 ms.

There are cases where it may become impossible to acquire the data if the microcontroller software includes the data
acquisition conditions required for the LC72700E. For example, this problem may occur if the software was designed to
use only the post-vertical correction output. Since this IC does not output the same data twice and does not output bad
data at all, applications do not need to select from the input data if they simply acquire all data that starts at every INT
signal. (In other words, it can be also said that this IC does not generate any unnecessary interrupt signals.) To set up this
IC to provide the same output format as that of the LC72700E, applications must set bit 5 (INT MODE) in the control
register to 1. Note that this IC is added a control function that causes the IC not to output post-vertical correction data if
the vertical correction operation was not executed. Since this control function is not influenced by the INT MOVE flag,
post-vertical correction output is not provided during error-free reception even if the INT MOVE flag was set. Thus care
is required in application software design.

Methods for Supporting the Different Frame Formats

Applications can handle the A, A’, B, and C frame formats by setting bits 0 (FRAME), 1 (RTIB), and 2 (VEC HALT) in
the control register appropriately. The default values are appropriate for method B. Note that since the IC itself does not
provide any functions for recognizing the frame structure, applications must set these bits using the serial data transfer
function.

No. 5876-13/16

LC72709E, 72709W

While the VEC HALT flag allows method C to be handled, the information related to the block number and the
information related to frame synchronization in the status output will be invalid.

Invalid status:

CNT1: Bit 5 FIL Frame synchronization information
CNT1: Bit 3 PRI Parity packet information
CNT1: Bit 2 HEAD Frame head information
CNT1: Bit 0 RTIB RTIB information
CNT2: Data block number and parity packet number information

(*) RTIB: Real Time Information Blocks

METHOD FRAME (Bit 0) RTB (Bit 1) VEC HALT (Bit 2)

A H H L No interleaves

A’ H L L A + RTIB (*)

B L — L Interleaving
C — — H Block data only

No. 5876-14/16

LC72709E, 72709W

Sample Application Circuit

Caution: The value of the DO (pin 31) pull-up resistor must be chosen to be appropriate for the frequency of the transfer

clock used.
The power supply bypass capacitors have arbitrary values.
The information presented in this documentation (including circuit designs and circuit constants) is provided
as examples. These designs and values are not guaranteed for use in mass produced end products.

No. 5876-15/16

LC72709E, 72709W

SWIFT Frame Structure (Provided for reference purposes.)

While horizontal correction is performed for the real-time information blocks (RTIB), vertical correction is not. The
vertical correction process uses 272 packets that do not include the RTIB, which consists of 12 packets. The time
required to transmit a single frame is 5.112 seconds, which is 18 ms × 284.

Data blocks (1 to 60)

Data blocks (61 to 130)

Data blocks (131 to 190)

Parity blocks (vertical) 20 blocks

Parity blocks (vertical) 21 blocks

Real time information blocks (4 blocks)

Real time information blocks (4 blocks)

Real time information blocks (4 blocks)

Parity blocks (vertical) 21 blocks

Parity blocks (vertical) 20 blocks

16 bits

14 bits

82 bits190 bits

Parity (horizontal)

Parity (horizontal)

Parity (horizontal)

Parity (horizontal)

Parity (horizontal)

Parity (horizontal)

No. 5876-16/16

LC72709E

This catalog provides information as of July, 1998. Specifications and information herein are subject to change
without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.

Announcement
Sanyo Electric Co., Ltd. reports to NHK-ES data for the
number of units of this IC shipped after October 1997.
(However, this does not apply to samples.)

Address inquiries concerning contracts to:
NHK Engineering Services
Telephone: [phone]

The DARC (Data Radio Channel) FM multiplex broadcast
technology was developed by NHK (Japan Broadcasting
Corporation). DARC is a registered trademark of NHK
Engineering Service (NHK-ES).
A separate contract with NHK-ES is required in advance
for the manufacture and/or sale of electronic equipment
that uses DARC technology. Note that the logo shown
here can be displayed on electronic equipment that uses
DARC technology.